1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 #define isc_txq_select ifc_txrx.ift_txq_select 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 struct ether_addr ifc_mac; 216 }; 217 218 void * 219 iflib_get_softc(if_ctx_t ctx) 220 { 221 222 return (ctx->ifc_softc); 223 } 224 225 device_t 226 iflib_get_dev(if_ctx_t ctx) 227 { 228 229 return (ctx->ifc_dev); 230 } 231 232 if_t 233 iflib_get_ifp(if_ctx_t ctx) 234 { 235 236 return (ctx->ifc_ifp); 237 } 238 239 struct ifmedia * 240 iflib_get_media(if_ctx_t ctx) 241 { 242 243 return (ctx->ifc_mediap); 244 } 245 246 uint32_t 247 iflib_get_flags(if_ctx_t ctx) 248 { 249 return (ctx->ifc_flags); 250 } 251 252 void 253 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 254 { 255 256 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 257 } 258 259 if_softc_ctx_t 260 iflib_get_softc_ctx(if_ctx_t ctx) 261 { 262 263 return (&ctx->ifc_softc_ctx); 264 } 265 266 if_shared_ctx_t 267 iflib_get_sctx(if_ctx_t ctx) 268 { 269 270 return (ctx->ifc_sctx); 271 } 272 273 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 274 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 275 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 276 277 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 278 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 279 280 typedef struct iflib_sw_rx_desc_array { 281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 282 struct mbuf **ifsd_m; /* pkthdr mbufs */ 283 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 284 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 285 } iflib_rxsd_array_t; 286 287 typedef struct iflib_sw_tx_desc_array { 288 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 289 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 290 struct mbuf **ifsd_m; /* pkthdr mbufs */ 291 } if_txsd_vec_t; 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 #define IFLIB_RX_COPY_THRESH 128 296 #define IFLIB_MAX_RX_REFRESH 32 297 /* The minimum descriptors per second before we start coalescing */ 298 #define IFLIB_MIN_DESC_SEC 16384 299 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 300 #define IFLIB_QUEUE_IDLE 0 301 #define IFLIB_QUEUE_HUNG 1 302 #define IFLIB_QUEUE_WORKING 2 303 /* maximum number of txqs that can share an rx interrupt */ 304 #define IFLIB_MAX_TX_SHARED_INTR 4 305 306 /* this should really scale with ring size - this is a fairly arbitrary value */ 307 #define TX_BATCH_SIZE 32 308 309 #define IFLIB_RESTART_BUDGET 8 310 311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 314 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 uint64_t ift_last_timer_tick; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 #ifdef DEV_NETMAP 354 struct callout ift_netmap_timer; 355 #endif /* DEV_NETMAP */ 356 357 if_txsd_vec_t ift_sds; 358 uint8_t ift_qstatus; 359 uint8_t ift_closed; 360 uint8_t ift_update_freq; 361 struct iflib_filter_info ift_filter_info; 362 bus_dma_tag_t ift_buf_tag; 363 bus_dma_tag_t ift_tso_buf_tag; 364 iflib_dma_info_t ift_ifdi; 365 #define MTX_NAME_LEN 32 366 char ift_mtx_name[MTX_NAME_LEN]; 367 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 368 #ifdef IFLIB_DIAGNOSTICS 369 uint64_t ift_cpu_exec_count[256]; 370 #endif 371 } __aligned(CACHE_LINE_SIZE); 372 373 struct iflib_fl { 374 qidx_t ifl_cidx; 375 qidx_t ifl_pidx; 376 qidx_t ifl_credits; 377 uint8_t ifl_gen; 378 uint8_t ifl_rxd_size; 379 #if MEMORY_LOGGING 380 uint64_t ifl_m_enqueued; 381 uint64_t ifl_m_dequeued; 382 uint64_t ifl_cl_enqueued; 383 uint64_t ifl_cl_dequeued; 384 #endif 385 /* implicit pad */ 386 bitstr_t *ifl_rx_bitmap; 387 qidx_t ifl_fragidx; 388 /* constant */ 389 qidx_t ifl_size; 390 uint16_t ifl_buf_size; 391 uint16_t ifl_cltype; 392 uma_zone_t ifl_zone; 393 iflib_rxsd_array_t ifl_sds; 394 iflib_rxq_t ifl_rxq; 395 uint8_t ifl_id; 396 bus_dma_tag_t ifl_buf_tag; 397 iflib_dma_info_t ifl_ifdi; 398 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 400 } __aligned(CACHE_LINE_SIZE); 401 402 static inline qidx_t 403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 404 { 405 qidx_t used; 406 407 if (pidx > cidx) 408 used = pidx - cidx; 409 else if (pidx < cidx) 410 used = size - cidx + pidx; 411 else if (gen == 0 && pidx == cidx) 412 used = 0; 413 else if (gen == 1 && pidx == cidx) 414 used = size; 415 else 416 panic("bad state"); 417 418 return (used); 419 } 420 421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 422 423 #define IDXDIFF(head, tail, wrap) \ 424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 425 426 struct iflib_rxq { 427 if_ctx_t ifr_ctx; 428 iflib_fl_t ifr_fl; 429 uint64_t ifr_rx_irq; 430 struct pfil_head *pfil; 431 /* 432 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 433 * the completion queue consumer index. Otherwise it's unused. 434 */ 435 qidx_t ifr_cq_cidx; 436 uint16_t ifr_id; 437 uint8_t ifr_nfl; 438 uint8_t ifr_ntxqirq; 439 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 440 uint8_t ifr_fl_offset; 441 struct lro_ctrl ifr_lc; 442 struct grouptask ifr_task; 443 struct callout ifr_watchdog; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 iflib_fl_t ifsd_fl; 457 } *if_rxsd_t; 458 459 /* multiple of word size */ 460 #ifdef __LP64__ 461 #define PKT_INFO_SIZE 6 462 #define RXD_INFO_SIZE 5 463 #define PKT_TYPE uint64_t 464 #else 465 #define PKT_INFO_SIZE 11 466 #define RXD_INFO_SIZE 8 467 #define PKT_TYPE uint32_t 468 #endif 469 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 470 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 471 472 typedef struct if_pkt_info_pad { 473 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 474 } *if_pkt_info_pad_t; 475 typedef struct if_rxd_info_pad { 476 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 477 } *if_rxd_info_pad_t; 478 479 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 480 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 481 482 static inline void 483 pkt_info_zero(if_pkt_info_t pi) 484 { 485 if_pkt_info_pad_t pi_pad; 486 487 pi_pad = (if_pkt_info_pad_t)pi; 488 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 489 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 490 #ifndef __LP64__ 491 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 492 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 493 #endif 494 } 495 496 static device_method_t iflib_pseudo_methods[] = { 497 DEVMETHOD(device_attach, noop_attach), 498 DEVMETHOD(device_detach, iflib_pseudo_detach), 499 DEVMETHOD_END 500 }; 501 502 driver_t iflib_pseudodriver = { 503 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 504 }; 505 506 static inline void 507 rxd_info_zero(if_rxd_info_t ri) 508 { 509 if_rxd_info_pad_t ri_pad; 510 int i; 511 512 ri_pad = (if_rxd_info_pad_t)ri; 513 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 514 ri_pad->rxd_val[i] = 0; 515 ri_pad->rxd_val[i+1] = 0; 516 ri_pad->rxd_val[i+2] = 0; 517 ri_pad->rxd_val[i+3] = 0; 518 } 519 #ifdef __LP64__ 520 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 521 #endif 522 } 523 524 /* 525 * Only allow a single packet to take up most 1/nth of the tx ring 526 */ 527 #define MAX_SINGLE_PACKET_FRACTION 12 528 #define IF_BAD_DMA (bus_addr_t)-1 529 530 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 531 532 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 533 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 535 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 536 537 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 538 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 539 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 540 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 541 542 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 543 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 544 545 void 546 iflib_set_detach(if_ctx_t ctx) 547 { 548 STATE_LOCK(ctx); 549 ctx->ifc_flags |= IFC_IN_DETACH; 550 STATE_UNLOCK(ctx); 551 } 552 553 /* Our boot-time initialization hook */ 554 static int iflib_module_event_handler(module_t, int, void *); 555 556 static moduledata_t iflib_moduledata = { 557 "iflib", 558 iflib_module_event_handler, 559 NULL 560 }; 561 562 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 563 MODULE_VERSION(iflib, 1); 564 565 MODULE_DEPEND(iflib, pci, 1, 1, 1); 566 MODULE_DEPEND(iflib, ether, 1, 1, 1); 567 568 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 569 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 570 571 #ifndef IFLIB_DEBUG_COUNTERS 572 #ifdef INVARIANTS 573 #define IFLIB_DEBUG_COUNTERS 1 574 #else 575 #define IFLIB_DEBUG_COUNTERS 0 576 #endif /* !INVARIANTS */ 577 #endif 578 579 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 580 "iflib driver parameters"); 581 582 /* 583 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 584 */ 585 static int iflib_min_tx_latency = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 587 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_no_tx_batch = 0; 589 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 590 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 591 static int iflib_timer_default = 1000; 592 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 593 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 594 595 596 #if IFLIB_DEBUG_COUNTERS 597 598 static int iflib_tx_seen; 599 static int iflib_tx_sent; 600 static int iflib_tx_encap; 601 static int iflib_rx_allocs; 602 static int iflib_fl_refills; 603 static int iflib_fl_refills_large; 604 static int iflib_tx_frees; 605 606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 607 &iflib_tx_seen, 0, "# TX mbufs seen"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 609 &iflib_tx_sent, 0, "# TX mbufs sent"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 611 &iflib_tx_encap, 0, "# TX mbufs encapped"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 613 &iflib_tx_frees, 0, "# TX frees"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 615 &iflib_rx_allocs, 0, "# RX allocations"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 617 &iflib_fl_refills, 0, "# refills"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 619 &iflib_fl_refills_large, 0, "# large refills"); 620 621 static int iflib_txq_drain_flushing; 622 static int iflib_txq_drain_oactive; 623 static int iflib_txq_drain_notready; 624 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 626 &iflib_txq_drain_flushing, 0, "# drain flushes"); 627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 628 &iflib_txq_drain_oactive, 0, "# drain oactives"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 630 &iflib_txq_drain_notready, 0, "# drain notready"); 631 632 static int iflib_encap_load_mbuf_fail; 633 static int iflib_encap_pad_mbuf_fail; 634 static int iflib_encap_txq_avail_fail; 635 static int iflib_encap_txd_encap_fail; 636 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 640 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 642 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 644 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 645 646 static int iflib_task_fn_rxs; 647 static int iflib_rx_intr_enables; 648 static int iflib_fast_intrs; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_if_input; 652 static int iflib_rxd_flush; 653 654 static int iflib_verbose_debug; 655 656 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 657 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 659 &iflib_rx_intr_enables, 0, "# RX intr enables"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 661 &iflib_fast_intrs, 0, "# fast_intr calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 663 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 665 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 667 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 669 &iflib_rxd_flush, 0, "# times rxd_flush called"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 671 &iflib_verbose_debug, 0, "enable verbose debugging"); 672 673 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 674 static void 675 iflib_debug_reset(void) 676 { 677 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 678 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 679 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 680 iflib_txq_drain_notready = 681 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 682 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 683 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 684 iflib_rx_unavail = 685 iflib_rx_ctx_inactive = iflib_rx_if_input = 686 iflib_rxd_flush = 0; 687 } 688 689 #else 690 #define DBG_COUNTER_INC(name) 691 static void iflib_debug_reset(void) {} 692 #endif 693 694 #define IFLIB_DEBUG 0 695 696 static void iflib_tx_structures_free(if_ctx_t ctx); 697 static void iflib_rx_structures_free(if_ctx_t ctx); 698 static int iflib_queues_alloc(if_ctx_t ctx); 699 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 700 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 701 static int iflib_qset_structures_setup(if_ctx_t ctx); 702 static int iflib_msix_init(if_ctx_t ctx); 703 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 704 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 705 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 706 #ifdef ALTQ 707 static void iflib_altq_if_start(if_t ifp); 708 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 709 #endif 710 static int iflib_register(if_ctx_t); 711 static void iflib_deregister(if_ctx_t); 712 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 713 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 714 static void iflib_init_locked(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 716 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 717 static void iflib_ifmp_purge(iflib_txq_t txq); 718 static void _iflib_pre_assert(if_softc_ctx_t scctx); 719 static void iflib_if_init_locked(if_ctx_t ctx); 720 static void iflib_free_intr_mem(if_ctx_t ctx); 721 #ifndef __NO_STRICT_ALIGNMENT 722 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 723 #endif 724 725 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 726 SLIST_HEAD_INITIALIZER(cpu_offsets); 727 struct cpu_offset { 728 SLIST_ENTRY(cpu_offset) entries; 729 cpuset_t set; 730 unsigned int refcount; 731 uint16_t next_cpuid; 732 }; 733 static struct mtx cpu_offset_mtx; 734 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 735 MTX_DEF); 736 737 DEBUGNET_DEFINE(iflib); 738 739 static int 740 iflib_num_rx_descs(if_ctx_t ctx) 741 { 742 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 743 if_shared_ctx_t sctx = ctx->ifc_sctx; 744 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 745 746 return scctx->isc_nrxd[first_rxq]; 747 } 748 749 static int 750 iflib_num_tx_descs(if_ctx_t ctx) 751 { 752 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 753 if_shared_ctx_t sctx = ctx->ifc_sctx; 754 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 755 756 return scctx->isc_ntxd[first_txq]; 757 } 758 759 #ifdef DEV_NETMAP 760 #include <sys/selinfo.h> 761 #include <net/netmap.h> 762 #include <dev/netmap/netmap_kern.h> 763 764 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 765 766 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 767 static void iflib_netmap_timer(void *arg); 768 769 /* 770 * device-specific sysctl variables: 771 * 772 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 773 * During regular operations the CRC is stripped, but on some 774 * hardware reception of frames not multiple of 64 is slower, 775 * so using crcstrip=0 helps in benchmarks. 776 * 777 * iflib_rx_miss, iflib_rx_miss_bufs: 778 * count packets that might be missed due to lost interrupts. 779 */ 780 SYSCTL_DECL(_dev_netmap); 781 /* 782 * The xl driver by default strips CRCs and we do not override it. 783 */ 784 785 int iflib_crcstrip = 1; 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 787 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 788 789 int iflib_rx_miss, iflib_rx_miss_bufs; 790 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 791 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 793 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 794 795 /* 796 * Register/unregister. We are already under netmap lock. 797 * Only called on the first register or the last unregister. 798 */ 799 static int 800 iflib_netmap_register(struct netmap_adapter *na, int onoff) 801 { 802 if_t ifp = na->ifp; 803 if_ctx_t ctx = ifp->if_softc; 804 int status; 805 806 CTX_LOCK(ctx); 807 if (!CTX_IS_VF(ctx)) 808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 809 810 iflib_stop(ctx); 811 812 /* 813 * Enable (or disable) netmap flags, and intercept (or restore) 814 * ifp->if_transmit. This is done once the device has been stopped 815 * to prevent race conditions. Also, this must be done after 816 * calling netmap_disable_all_rings() and before calling 817 * netmap_enable_all_rings(), so that these two functions see the 818 * updated state of the NAF_NETMAP_ON bit. 819 */ 820 if (onoff) { 821 nm_set_native_flags(na); 822 } else { 823 nm_clear_native_flags(na); 824 } 825 826 iflib_init_locked(ctx); 827 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 828 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 829 if (status) 830 nm_clear_native_flags(na); 831 CTX_UNLOCK(ctx); 832 return (status); 833 } 834 835 static int 836 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 837 { 838 if_t ifp = na->ifp; 839 if_ctx_t ctx = ifp->if_softc; 840 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 841 iflib_fl_t fl = &rxq->ifr_fl[0]; 842 843 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 844 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 845 info->num_tx_descs = iflib_num_tx_descs(ctx); 846 info->num_rx_descs = iflib_num_rx_descs(ctx); 847 info->rx_buf_maxsize = fl->ifl_buf_size; 848 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 849 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 850 info->num_rx_descs, info->rx_buf_maxsize); 851 852 return 0; 853 } 854 855 static int 856 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 857 { 858 struct netmap_adapter *na = kring->na; 859 u_int const lim = kring->nkr_num_slots - 1; 860 struct netmap_ring *ring = kring->ring; 861 bus_dmamap_t *map; 862 struct if_rxd_update iru; 863 if_ctx_t ctx = rxq->ifr_ctx; 864 iflib_fl_t fl = &rxq->ifr_fl[0]; 865 u_int nic_i_first, nic_i; 866 u_int nm_i; 867 int i, n; 868 #if IFLIB_DEBUG_COUNTERS 869 int rf_count = 0; 870 #endif 871 872 /* 873 * This function is used both at initialization and in rxsync. 874 * At initialization we need to prepare (with isc_rxd_refill()) 875 * all the netmap buffers currently owned by the kernel, in 876 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 877 * (except for kring->nkr_hwofs). These may be less than 878 * kring->nkr_num_slots if netmap_reset() was called while 879 * an application using the kring that still owned some 880 * buffers. 881 * At rxsync time, both indexes point to the next buffer to be 882 * refilled. 883 * In any case we publish (with isc_rxd_flush()) up to 884 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 885 * pointer to overrun the head/cons pointer, although this is 886 * not necessary for some NICs (e.g. vmx). 887 */ 888 if (__predict_false(init)) { 889 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 890 } else { 891 n = kring->rhead - kring->nr_hwcur; 892 if (n == 0) 893 return (0); /* Nothing to do. */ 894 if (n < 0) 895 n += kring->nkr_num_slots; 896 } 897 898 iru_init(&iru, rxq, 0 /* flid */); 899 map = fl->ifl_sds.ifsd_map; 900 nic_i = fl->ifl_pidx; 901 nm_i = netmap_idx_n2k(kring, nic_i); 902 if (__predict_false(init)) { 903 /* 904 * On init/reset, nic_i must be 0, and we must 905 * start to refill from hwtail (see netmap_reset()). 906 */ 907 MPASS(nic_i == 0); 908 MPASS(nm_i == kring->nr_hwtail); 909 } else 910 MPASS(nm_i == kring->nr_hwcur); 911 DBG_COUNTER_INC(fl_refills); 912 while (n > 0) { 913 #if IFLIB_DEBUG_COUNTERS 914 if (++rf_count == 9) 915 DBG_COUNTER_INC(fl_refills_large); 916 #endif 917 nic_i_first = nic_i; 918 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 919 struct netmap_slot *slot = &ring->slot[nm_i]; 920 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 921 922 MPASS(i < IFLIB_MAX_RX_REFRESH); 923 924 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 925 return netmap_ring_reinit(kring); 926 927 fl->ifl_rxd_idxs[i] = nic_i; 928 929 if (__predict_false(init)) { 930 netmap_load_map(na, fl->ifl_buf_tag, 931 map[nic_i], addr); 932 } else if (slot->flags & NS_BUF_CHANGED) { 933 /* buffer has changed, reload map */ 934 netmap_reload_map(na, fl->ifl_buf_tag, 935 map[nic_i], addr); 936 } 937 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 938 BUS_DMASYNC_PREREAD); 939 slot->flags &= ~NS_BUF_CHANGED; 940 941 nm_i = nm_next(nm_i, lim); 942 nic_i = nm_next(nic_i, lim); 943 } 944 945 iru.iru_pidx = nic_i_first; 946 iru.iru_count = i; 947 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 948 } 949 fl->ifl_pidx = nic_i; 950 /* 951 * At the end of the loop we must have refilled everything 952 * we could possibly refill. 953 */ 954 MPASS(nm_i == kring->rhead); 955 kring->nr_hwcur = nm_i; 956 957 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 959 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 960 nm_prev(nic_i, lim)); 961 DBG_COUNTER_INC(rxd_flush); 962 963 return (0); 964 } 965 966 #define NETMAP_TX_TIMER_US 90 967 968 /* 969 * Reconcile kernel and user view of the transmit ring. 970 * 971 * All information is in the kring. 972 * Userspace wants to send packets up to the one before kring->rhead, 973 * kernel knows kring->nr_hwcur is the first unsent packet. 974 * 975 * Here we push packets out (as many as possible), and possibly 976 * reclaim buffers from previously completed transmission. 977 * 978 * The caller (netmap) guarantees that there is only one instance 979 * running at any time. Any interference with other driver 980 * methods should be handled by the individual drivers. 981 */ 982 static int 983 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 984 { 985 struct netmap_adapter *na = kring->na; 986 if_t ifp = na->ifp; 987 struct netmap_ring *ring = kring->ring; 988 u_int nm_i; /* index into the netmap kring */ 989 u_int nic_i; /* index into the NIC ring */ 990 u_int n; 991 u_int const lim = kring->nkr_num_slots - 1; 992 u_int const head = kring->rhead; 993 struct if_pkt_info pi; 994 int tx_pkts = 0, tx_bytes = 0; 995 996 /* 997 * interrupts on every tx packet are expensive so request 998 * them every half ring, or where NS_REPORT is set 999 */ 1000 u_int report_frequency = kring->nkr_num_slots >> 1; 1001 /* device-specific */ 1002 if_ctx_t ctx = ifp->if_softc; 1003 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1004 1005 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1006 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1007 1008 /* 1009 * First part: process new packets to send. 1010 * nm_i is the current index in the netmap kring, 1011 * nic_i is the corresponding index in the NIC ring. 1012 * 1013 * If we have packets to send (nm_i != head) 1014 * iterate over the netmap ring, fetch length and update 1015 * the corresponding slot in the NIC ring. Some drivers also 1016 * need to update the buffer's physical address in the NIC slot 1017 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1018 * 1019 * The netmap_reload_map() calls is especially expensive, 1020 * even when (as in this case) the tag is 0, so do only 1021 * when the buffer has actually changed. 1022 * 1023 * If possible do not set the report/intr bit on all slots, 1024 * but only a few times per ring or when NS_REPORT is set. 1025 * 1026 * Finally, on 10G and faster drivers, it might be useful 1027 * to prefetch the next slot and txr entry. 1028 */ 1029 1030 nm_i = kring->nr_hwcur; 1031 if (nm_i != head) { /* we have new packets to send */ 1032 uint32_t pkt_len = 0, seg_idx = 0; 1033 int nic_i_start = -1, flags = 0; 1034 pkt_info_zero(&pi); 1035 pi.ipi_segs = txq->ift_segs; 1036 pi.ipi_qsidx = kring->ring_id; 1037 nic_i = netmap_idx_k2n(kring, nm_i); 1038 1039 __builtin_prefetch(&ring->slot[nm_i]); 1040 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1041 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1042 1043 for (n = 0; nm_i != head; n++) { 1044 struct netmap_slot *slot = &ring->slot[nm_i]; 1045 u_int len = slot->len; 1046 uint64_t paddr; 1047 void *addr = PNMB(na, slot, &paddr); 1048 1049 flags |= (slot->flags & NS_REPORT || 1050 nic_i == 0 || nic_i == report_frequency) ? 1051 IPI_TX_INTR : 0; 1052 1053 /* 1054 * If this is the first packet fragment, save the 1055 * index of the first NIC slot for later. 1056 */ 1057 if (nic_i_start < 0) 1058 nic_i_start = nic_i; 1059 1060 pi.ipi_segs[seg_idx].ds_addr = paddr; 1061 pi.ipi_segs[seg_idx].ds_len = len; 1062 if (len) { 1063 pkt_len += len; 1064 seg_idx++; 1065 } 1066 1067 if (!(slot->flags & NS_MOREFRAG)) { 1068 pi.ipi_len = pkt_len; 1069 pi.ipi_nsegs = seg_idx; 1070 pi.ipi_pidx = nic_i_start; 1071 pi.ipi_ndescs = 0; 1072 pi.ipi_flags = flags; 1073 1074 /* Prepare the NIC TX ring. */ 1075 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1076 DBG_COUNTER_INC(tx_encap); 1077 1078 /* Update transmit counters */ 1079 tx_bytes += pi.ipi_len; 1080 tx_pkts++; 1081 1082 /* Reinit per-packet info for the next one. */ 1083 flags = seg_idx = pkt_len = 0; 1084 nic_i_start = -1; 1085 } 1086 1087 /* prefetch for next round */ 1088 __builtin_prefetch(&ring->slot[nm_i + 1]); 1089 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1090 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1091 1092 NM_CHECK_ADDR_LEN(na, addr, len); 1093 1094 if (slot->flags & NS_BUF_CHANGED) { 1095 /* buffer has changed, reload map */ 1096 netmap_reload_map(na, txq->ift_buf_tag, 1097 txq->ift_sds.ifsd_map[nic_i], addr); 1098 } 1099 /* make sure changes to the buffer are synced */ 1100 bus_dmamap_sync(txq->ift_buf_tag, 1101 txq->ift_sds.ifsd_map[nic_i], 1102 BUS_DMASYNC_PREWRITE); 1103 1104 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1105 nm_i = nm_next(nm_i, lim); 1106 nic_i = nm_next(nic_i, lim); 1107 } 1108 kring->nr_hwcur = nm_i; 1109 1110 /* synchronize the NIC ring */ 1111 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1113 1114 /* (re)start the tx unit up to slot nic_i (excluded) */ 1115 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1116 } 1117 1118 /* 1119 * Second part: reclaim buffers for completed transmissions. 1120 * 1121 * If there are unclaimed buffers, attempt to reclaim them. 1122 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1123 * trigger a per-tx-queue timer to try again later. 1124 */ 1125 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1126 if (iflib_tx_credits_update(ctx, txq)) { 1127 /* some tx completed, increment avail */ 1128 nic_i = txq->ift_cidx_processed; 1129 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1130 } 1131 } 1132 1133 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1134 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1135 callout_reset_sbt_on(&txq->ift_netmap_timer, 1136 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1137 iflib_netmap_timer, txq, 1138 txq->ift_netmap_timer.c_cpu, 0); 1139 } 1140 1141 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1142 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1143 1144 return (0); 1145 } 1146 1147 /* 1148 * Reconcile kernel and user view of the receive ring. 1149 * Same as for the txsync, this routine must be efficient. 1150 * The caller guarantees a single invocations, but races against 1151 * the rest of the driver should be handled here. 1152 * 1153 * On call, kring->rhead is the first packet that userspace wants 1154 * to keep, and kring->rcur is the wakeup point. 1155 * The kernel has previously reported packets up to kring->rtail. 1156 * 1157 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1158 * of whether or not we received an interrupt. 1159 */ 1160 static int 1161 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1162 { 1163 struct netmap_adapter *na = kring->na; 1164 struct netmap_ring *ring = kring->ring; 1165 if_t ifp = na->ifp; 1166 uint32_t nm_i; /* index into the netmap ring */ 1167 uint32_t nic_i; /* index into the NIC ring */ 1168 u_int n; 1169 u_int const lim = kring->nkr_num_slots - 1; 1170 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1171 int i = 0, rx_bytes = 0, rx_pkts = 0; 1172 1173 if_ctx_t ctx = ifp->if_softc; 1174 if_shared_ctx_t sctx = ctx->ifc_sctx; 1175 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1176 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1177 iflib_fl_t fl = &rxq->ifr_fl[0]; 1178 struct if_rxd_info ri; 1179 qidx_t *cidxp; 1180 1181 /* 1182 * netmap only uses free list 0, to avoid out of order consumption 1183 * of receive buffers 1184 */ 1185 1186 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1187 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1188 1189 /* 1190 * First part: import newly received packets. 1191 * 1192 * nm_i is the index of the next free slot in the netmap ring, 1193 * nic_i is the index of the next received packet in the NIC ring 1194 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1195 * differ in case if_init() has been called while 1196 * in netmap mode. For the receive ring we have 1197 * 1198 * nic_i = fl->ifl_cidx; 1199 * nm_i = kring->nr_hwtail (previous) 1200 * and 1201 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1202 * 1203 * fl->ifl_cidx is set to 0 on a ring reinit 1204 */ 1205 if (netmap_no_pendintr || force_update) { 1206 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1207 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1208 int crclen = iflib_crcstrip ? 0 : 4; 1209 int error, avail; 1210 1211 /* 1212 * For the free list consumer index, we use the same 1213 * logic as in iflib_rxeof(). 1214 */ 1215 if (have_rxcq) 1216 cidxp = &rxq->ifr_cq_cidx; 1217 else 1218 cidxp = &fl->ifl_cidx; 1219 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1220 rxq->ifr_id, *cidxp, USHRT_MAX); 1221 1222 nic_i = fl->ifl_cidx; 1223 nm_i = netmap_idx_n2k(kring, nic_i); 1224 MPASS(nm_i == kring->nr_hwtail); 1225 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1226 rxd_info_zero(&ri); 1227 ri.iri_frags = rxq->ifr_frags; 1228 ri.iri_qsidx = kring->ring_id; 1229 ri.iri_ifp = ctx->ifc_ifp; 1230 ri.iri_cidx = *cidxp; 1231 1232 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1233 for (i = 0; i < ri.iri_nfrags; i++) { 1234 if (error) { 1235 ring->slot[nm_i].len = 0; 1236 ring->slot[nm_i].flags = 0; 1237 } else { 1238 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1239 if (i == (ri.iri_nfrags - 1)) { 1240 ring->slot[nm_i].len -= crclen; 1241 ring->slot[nm_i].flags = 0; 1242 1243 /* Update receive counters */ 1244 rx_bytes += ri.iri_len; 1245 rx_pkts++; 1246 } else 1247 ring->slot[nm_i].flags = NS_MOREFRAG; 1248 } 1249 1250 bus_dmamap_sync(fl->ifl_buf_tag, 1251 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1252 nm_i = nm_next(nm_i, lim); 1253 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1254 } 1255 1256 if (have_rxcq) { 1257 *cidxp = ri.iri_cidx; 1258 while (*cidxp >= scctx->isc_nrxd[0]) 1259 *cidxp -= scctx->isc_nrxd[0]; 1260 } 1261 1262 } 1263 if (n) { /* update the state variables */ 1264 if (netmap_no_pendintr && !force_update) { 1265 /* diagnostics */ 1266 iflib_rx_miss ++; 1267 iflib_rx_miss_bufs += n; 1268 } 1269 kring->nr_hwtail = nm_i; 1270 } 1271 kring->nr_kflags &= ~NKR_PENDINTR; 1272 } 1273 /* 1274 * Second part: skip past packets that userspace has released. 1275 * (kring->nr_hwcur to head excluded), 1276 * and make the buffers available for reception. 1277 * As usual nm_i is the index in the netmap ring, 1278 * nic_i is the index in the NIC ring, and 1279 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1280 */ 1281 netmap_fl_refill(rxq, kring, false); 1282 1283 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1284 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1285 1286 return (0); 1287 } 1288 1289 static void 1290 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1291 { 1292 if_ctx_t ctx = na->ifp->if_softc; 1293 1294 CTX_LOCK(ctx); 1295 if (onoff) { 1296 IFDI_INTR_ENABLE(ctx); 1297 } else { 1298 IFDI_INTR_DISABLE(ctx); 1299 } 1300 CTX_UNLOCK(ctx); 1301 } 1302 1303 static int 1304 iflib_netmap_attach(if_ctx_t ctx) 1305 { 1306 struct netmap_adapter na; 1307 1308 bzero(&na, sizeof(na)); 1309 1310 na.ifp = ctx->ifc_ifp; 1311 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG; 1312 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1313 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1314 1315 na.num_tx_desc = iflib_num_tx_descs(ctx); 1316 na.num_rx_desc = iflib_num_rx_descs(ctx); 1317 na.nm_txsync = iflib_netmap_txsync; 1318 na.nm_rxsync = iflib_netmap_rxsync; 1319 na.nm_register = iflib_netmap_register; 1320 na.nm_intr = iflib_netmap_intr; 1321 na.nm_config = iflib_netmap_config; 1322 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1323 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1324 return (netmap_attach(&na)); 1325 } 1326 1327 static int 1328 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1329 { 1330 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1331 struct netmap_slot *slot; 1332 1333 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1334 if (slot == NULL) 1335 return (0); 1336 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1337 /* 1338 * In netmap mode, set the map for the packet buffer. 1339 * NOTE: Some drivers (not this one) also need to set 1340 * the physical buffer address in the NIC ring. 1341 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1342 * netmap slot index, si 1343 */ 1344 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1345 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1346 NMB(na, slot + si)); 1347 } 1348 return (1); 1349 } 1350 1351 static int 1352 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1353 { 1354 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1355 struct netmap_kring *kring; 1356 struct netmap_slot *slot; 1357 1358 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1359 if (slot == NULL) 1360 return (0); 1361 kring = na->rx_rings[rxq->ifr_id]; 1362 netmap_fl_refill(rxq, kring, true); 1363 return (1); 1364 } 1365 1366 static void 1367 iflib_netmap_timer(void *arg) 1368 { 1369 iflib_txq_t txq = arg; 1370 if_ctx_t ctx = txq->ift_ctx; 1371 1372 /* 1373 * Wake up the netmap application, to give it a chance to 1374 * call txsync and reclaim more completed TX buffers. 1375 */ 1376 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1377 } 1378 1379 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1380 1381 #else 1382 #define iflib_netmap_txq_init(ctx, txq) (0) 1383 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1384 #define iflib_netmap_detach(ifp) 1385 #define netmap_enable_all_rings(ifp) 1386 #define netmap_disable_all_rings(ifp) 1387 1388 #define iflib_netmap_attach(ctx) (0) 1389 #define netmap_rx_irq(ifp, qid, budget) (0) 1390 #endif 1391 1392 #if defined(__i386__) || defined(__amd64__) 1393 static __inline void 1394 prefetch(void *x) 1395 { 1396 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1397 } 1398 static __inline void 1399 prefetch2cachelines(void *x) 1400 { 1401 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1402 #if (CACHE_LINE_SIZE < 128) 1403 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1404 #endif 1405 } 1406 #else 1407 #define prefetch(x) 1408 #define prefetch2cachelines(x) 1409 #endif 1410 1411 static void 1412 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1413 { 1414 iflib_fl_t fl; 1415 1416 fl = &rxq->ifr_fl[flid]; 1417 iru->iru_paddrs = fl->ifl_bus_addrs; 1418 iru->iru_idxs = fl->ifl_rxd_idxs; 1419 iru->iru_qsidx = rxq->ifr_id; 1420 iru->iru_buf_size = fl->ifl_buf_size; 1421 iru->iru_flidx = fl->ifl_id; 1422 } 1423 1424 static void 1425 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1426 { 1427 if (err) 1428 return; 1429 *(bus_addr_t *) arg = segs[0].ds_addr; 1430 } 1431 1432 int 1433 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1434 { 1435 int err; 1436 device_t dev = ctx->ifc_dev; 1437 1438 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1439 align, 0, /* alignment, bounds */ 1440 BUS_SPACE_MAXADDR, /* lowaddr */ 1441 BUS_SPACE_MAXADDR, /* highaddr */ 1442 NULL, NULL, /* filter, filterarg */ 1443 size, /* maxsize */ 1444 1, /* nsegments */ 1445 size, /* maxsegsize */ 1446 BUS_DMA_ALLOCNOW, /* flags */ 1447 NULL, /* lockfunc */ 1448 NULL, /* lockarg */ 1449 &dma->idi_tag); 1450 if (err) { 1451 device_printf(dev, 1452 "%s: bus_dma_tag_create failed: %d\n", 1453 __func__, err); 1454 goto fail_0; 1455 } 1456 1457 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1458 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1459 if (err) { 1460 device_printf(dev, 1461 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1462 __func__, (uintmax_t)size, err); 1463 goto fail_1; 1464 } 1465 1466 dma->idi_paddr = IF_BAD_DMA; 1467 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1468 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1469 if (err || dma->idi_paddr == IF_BAD_DMA) { 1470 device_printf(dev, 1471 "%s: bus_dmamap_load failed: %d\n", 1472 __func__, err); 1473 goto fail_2; 1474 } 1475 1476 dma->idi_size = size; 1477 return (0); 1478 1479 fail_2: 1480 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1481 fail_1: 1482 bus_dma_tag_destroy(dma->idi_tag); 1483 fail_0: 1484 dma->idi_tag = NULL; 1485 1486 return (err); 1487 } 1488 1489 int 1490 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1491 { 1492 if_shared_ctx_t sctx = ctx->ifc_sctx; 1493 1494 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1495 1496 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1497 } 1498 1499 int 1500 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1501 { 1502 int i, err; 1503 iflib_dma_info_t *dmaiter; 1504 1505 dmaiter = dmalist; 1506 for (i = 0; i < count; i++, dmaiter++) { 1507 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1508 break; 1509 } 1510 if (err) 1511 iflib_dma_free_multi(dmalist, i); 1512 return (err); 1513 } 1514 1515 void 1516 iflib_dma_free(iflib_dma_info_t dma) 1517 { 1518 if (dma->idi_tag == NULL) 1519 return; 1520 if (dma->idi_paddr != IF_BAD_DMA) { 1521 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1522 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1523 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1524 dma->idi_paddr = IF_BAD_DMA; 1525 } 1526 if (dma->idi_vaddr != NULL) { 1527 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1528 dma->idi_vaddr = NULL; 1529 } 1530 bus_dma_tag_destroy(dma->idi_tag); 1531 dma->idi_tag = NULL; 1532 } 1533 1534 void 1535 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1536 { 1537 int i; 1538 iflib_dma_info_t *dmaiter = dmalist; 1539 1540 for (i = 0; i < count; i++, dmaiter++) 1541 iflib_dma_free(*dmaiter); 1542 } 1543 1544 static int 1545 iflib_fast_intr(void *arg) 1546 { 1547 iflib_filter_info_t info = arg; 1548 struct grouptask *gtask = info->ifi_task; 1549 int result; 1550 1551 DBG_COUNTER_INC(fast_intrs); 1552 if (info->ifi_filter != NULL) { 1553 result = info->ifi_filter(info->ifi_filter_arg); 1554 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1555 return (result); 1556 } 1557 1558 GROUPTASK_ENQUEUE(gtask); 1559 return (FILTER_HANDLED); 1560 } 1561 1562 static int 1563 iflib_fast_intr_rxtx(void *arg) 1564 { 1565 iflib_filter_info_t info = arg; 1566 struct grouptask *gtask = info->ifi_task; 1567 if_ctx_t ctx; 1568 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1569 iflib_txq_t txq; 1570 void *sc; 1571 int i, cidx, result; 1572 qidx_t txqid; 1573 bool intr_enable, intr_legacy; 1574 1575 DBG_COUNTER_INC(fast_intrs); 1576 if (info->ifi_filter != NULL) { 1577 result = info->ifi_filter(info->ifi_filter_arg); 1578 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1579 return (result); 1580 } 1581 1582 ctx = rxq->ifr_ctx; 1583 sc = ctx->ifc_softc; 1584 intr_enable = false; 1585 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1586 MPASS(rxq->ifr_ntxqirq); 1587 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1588 txqid = rxq->ifr_txqid[i]; 1589 txq = &ctx->ifc_txqs[txqid]; 1590 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1591 BUS_DMASYNC_POSTREAD); 1592 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1593 if (intr_legacy) 1594 intr_enable = true; 1595 else 1596 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1597 continue; 1598 } 1599 GROUPTASK_ENQUEUE(&txq->ift_task); 1600 } 1601 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1602 cidx = rxq->ifr_cq_cidx; 1603 else 1604 cidx = rxq->ifr_fl[0].ifl_cidx; 1605 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1606 GROUPTASK_ENQUEUE(gtask); 1607 else { 1608 if (intr_legacy) 1609 intr_enable = true; 1610 else 1611 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1612 DBG_COUNTER_INC(rx_intr_enables); 1613 } 1614 if (intr_enable) 1615 IFDI_INTR_ENABLE(ctx); 1616 return (FILTER_HANDLED); 1617 } 1618 1619 static int 1620 iflib_fast_intr_ctx(void *arg) 1621 { 1622 iflib_filter_info_t info = arg; 1623 struct grouptask *gtask = info->ifi_task; 1624 int result; 1625 1626 DBG_COUNTER_INC(fast_intrs); 1627 if (info->ifi_filter != NULL) { 1628 result = info->ifi_filter(info->ifi_filter_arg); 1629 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1630 return (result); 1631 } 1632 1633 GROUPTASK_ENQUEUE(gtask); 1634 return (FILTER_HANDLED); 1635 } 1636 1637 static int 1638 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1639 driver_filter_t filter, driver_intr_t handler, void *arg, 1640 const char *name) 1641 { 1642 struct resource *res; 1643 void *tag = NULL; 1644 device_t dev = ctx->ifc_dev; 1645 int flags, i, rc; 1646 1647 flags = RF_ACTIVE; 1648 if (ctx->ifc_flags & IFC_LEGACY) 1649 flags |= RF_SHAREABLE; 1650 MPASS(rid < 512); 1651 i = rid; 1652 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1653 if (res == NULL) { 1654 device_printf(dev, 1655 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1656 return (ENOMEM); 1657 } 1658 irq->ii_res = res; 1659 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1660 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1661 filter, handler, arg, &tag); 1662 if (rc != 0) { 1663 device_printf(dev, 1664 "failed to setup interrupt for rid %d, name %s: %d\n", 1665 rid, name ? name : "unknown", rc); 1666 return (rc); 1667 } else if (name) 1668 bus_describe_intr(dev, res, tag, "%s", name); 1669 1670 irq->ii_tag = tag; 1671 return (0); 1672 } 1673 1674 /********************************************************************* 1675 * 1676 * Allocate DMA resources for TX buffers as well as memory for the TX 1677 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1678 * iflib_sw_tx_desc_array structure, storing all the information that 1679 * is needed to transmit a packet on the wire. This is called only 1680 * once at attach, setup is done every reset. 1681 * 1682 **********************************************************************/ 1683 static int 1684 iflib_txsd_alloc(iflib_txq_t txq) 1685 { 1686 if_ctx_t ctx = txq->ift_ctx; 1687 if_shared_ctx_t sctx = ctx->ifc_sctx; 1688 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1689 device_t dev = ctx->ifc_dev; 1690 bus_size_t tsomaxsize; 1691 int err, nsegments, ntsosegments; 1692 bool tso; 1693 1694 nsegments = scctx->isc_tx_nsegments; 1695 ntsosegments = scctx->isc_tx_tso_segments_max; 1696 tsomaxsize = scctx->isc_tx_tso_size_max; 1697 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1698 tsomaxsize += sizeof(struct ether_vlan_header); 1699 MPASS(scctx->isc_ntxd[0] > 0); 1700 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1701 MPASS(nsegments > 0); 1702 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1703 MPASS(ntsosegments > 0); 1704 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1705 } 1706 1707 /* 1708 * Set up DMA tags for TX buffers. 1709 */ 1710 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1711 1, 0, /* alignment, bounds */ 1712 BUS_SPACE_MAXADDR, /* lowaddr */ 1713 BUS_SPACE_MAXADDR, /* highaddr */ 1714 NULL, NULL, /* filter, filterarg */ 1715 sctx->isc_tx_maxsize, /* maxsize */ 1716 nsegments, /* nsegments */ 1717 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1718 0, /* flags */ 1719 NULL, /* lockfunc */ 1720 NULL, /* lockfuncarg */ 1721 &txq->ift_buf_tag))) { 1722 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1723 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1724 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1725 goto fail; 1726 } 1727 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1728 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1729 1, 0, /* alignment, bounds */ 1730 BUS_SPACE_MAXADDR, /* lowaddr */ 1731 BUS_SPACE_MAXADDR, /* highaddr */ 1732 NULL, NULL, /* filter, filterarg */ 1733 tsomaxsize, /* maxsize */ 1734 ntsosegments, /* nsegments */ 1735 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1736 0, /* flags */ 1737 NULL, /* lockfunc */ 1738 NULL, /* lockfuncarg */ 1739 &txq->ift_tso_buf_tag))) { 1740 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1741 err); 1742 goto fail; 1743 } 1744 1745 /* Allocate memory for the TX mbuf map. */ 1746 if (!(txq->ift_sds.ifsd_m = 1747 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1748 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1749 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1750 err = ENOMEM; 1751 goto fail; 1752 } 1753 1754 /* 1755 * Create the DMA maps for TX buffers. 1756 */ 1757 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1758 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1759 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1760 device_printf(dev, 1761 "Unable to allocate TX buffer DMA map memory\n"); 1762 err = ENOMEM; 1763 goto fail; 1764 } 1765 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1766 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1767 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1768 device_printf(dev, 1769 "Unable to allocate TSO TX buffer map memory\n"); 1770 err = ENOMEM; 1771 goto fail; 1772 } 1773 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1774 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1775 &txq->ift_sds.ifsd_map[i]); 1776 if (err != 0) { 1777 device_printf(dev, "Unable to create TX DMA map\n"); 1778 goto fail; 1779 } 1780 if (!tso) 1781 continue; 1782 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1783 &txq->ift_sds.ifsd_tso_map[i]); 1784 if (err != 0) { 1785 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1786 goto fail; 1787 } 1788 } 1789 return (0); 1790 fail: 1791 /* We free all, it handles case where we are in the middle */ 1792 iflib_tx_structures_free(ctx); 1793 return (err); 1794 } 1795 1796 static void 1797 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1798 { 1799 bus_dmamap_t map; 1800 1801 if (txq->ift_sds.ifsd_map != NULL) { 1802 map = txq->ift_sds.ifsd_map[i]; 1803 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1804 bus_dmamap_unload(txq->ift_buf_tag, map); 1805 bus_dmamap_destroy(txq->ift_buf_tag, map); 1806 txq->ift_sds.ifsd_map[i] = NULL; 1807 } 1808 1809 if (txq->ift_sds.ifsd_tso_map != NULL) { 1810 map = txq->ift_sds.ifsd_tso_map[i]; 1811 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1812 BUS_DMASYNC_POSTWRITE); 1813 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1814 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1815 txq->ift_sds.ifsd_tso_map[i] = NULL; 1816 } 1817 } 1818 1819 static void 1820 iflib_txq_destroy(iflib_txq_t txq) 1821 { 1822 if_ctx_t ctx = txq->ift_ctx; 1823 1824 for (int i = 0; i < txq->ift_size; i++) 1825 iflib_txsd_destroy(ctx, txq, i); 1826 1827 if (txq->ift_br != NULL) { 1828 ifmp_ring_free(txq->ift_br); 1829 txq->ift_br = NULL; 1830 } 1831 1832 mtx_destroy(&txq->ift_mtx); 1833 1834 if (txq->ift_sds.ifsd_map != NULL) { 1835 free(txq->ift_sds.ifsd_map, M_IFLIB); 1836 txq->ift_sds.ifsd_map = NULL; 1837 } 1838 if (txq->ift_sds.ifsd_tso_map != NULL) { 1839 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1840 txq->ift_sds.ifsd_tso_map = NULL; 1841 } 1842 if (txq->ift_sds.ifsd_m != NULL) { 1843 free(txq->ift_sds.ifsd_m, M_IFLIB); 1844 txq->ift_sds.ifsd_m = NULL; 1845 } 1846 if (txq->ift_buf_tag != NULL) { 1847 bus_dma_tag_destroy(txq->ift_buf_tag); 1848 txq->ift_buf_tag = NULL; 1849 } 1850 if (txq->ift_tso_buf_tag != NULL) { 1851 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1852 txq->ift_tso_buf_tag = NULL; 1853 } 1854 if (txq->ift_ifdi != NULL) { 1855 free(txq->ift_ifdi, M_IFLIB); 1856 } 1857 } 1858 1859 static void 1860 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1861 { 1862 struct mbuf **mp; 1863 1864 mp = &txq->ift_sds.ifsd_m[i]; 1865 if (*mp == NULL) 1866 return; 1867 1868 if (txq->ift_sds.ifsd_map != NULL) { 1869 bus_dmamap_sync(txq->ift_buf_tag, 1870 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1871 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1872 } 1873 if (txq->ift_sds.ifsd_tso_map != NULL) { 1874 bus_dmamap_sync(txq->ift_tso_buf_tag, 1875 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1876 bus_dmamap_unload(txq->ift_tso_buf_tag, 1877 txq->ift_sds.ifsd_tso_map[i]); 1878 } 1879 m_freem(*mp); 1880 DBG_COUNTER_INC(tx_frees); 1881 *mp = NULL; 1882 } 1883 1884 static int 1885 iflib_txq_setup(iflib_txq_t txq) 1886 { 1887 if_ctx_t ctx = txq->ift_ctx; 1888 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1889 if_shared_ctx_t sctx = ctx->ifc_sctx; 1890 iflib_dma_info_t di; 1891 int i; 1892 1893 /* Set number of descriptors available */ 1894 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1895 /* XXX make configurable */ 1896 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1897 1898 /* Reset indices */ 1899 txq->ift_cidx_processed = 0; 1900 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1901 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1902 1903 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1904 bzero((void *)di->idi_vaddr, di->idi_size); 1905 1906 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1907 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1908 bus_dmamap_sync(di->idi_tag, di->idi_map, 1909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1910 return (0); 1911 } 1912 1913 /********************************************************************* 1914 * 1915 * Allocate DMA resources for RX buffers as well as memory for the RX 1916 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1917 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1918 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1919 * Since we use use one entry in iflib_sw_rx_desc_array per received 1920 * packet, the maximum number of entries we'll need is equal to the 1921 * number of hardware receive descriptors that we've allocated. 1922 * 1923 **********************************************************************/ 1924 static int 1925 iflib_rxsd_alloc(iflib_rxq_t rxq) 1926 { 1927 if_ctx_t ctx = rxq->ifr_ctx; 1928 if_shared_ctx_t sctx = ctx->ifc_sctx; 1929 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1930 device_t dev = ctx->ifc_dev; 1931 iflib_fl_t fl; 1932 int err; 1933 1934 MPASS(scctx->isc_nrxd[0] > 0); 1935 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1936 1937 fl = rxq->ifr_fl; 1938 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1939 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1940 /* Set up DMA tag for RX buffers. */ 1941 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1942 1, 0, /* alignment, bounds */ 1943 BUS_SPACE_MAXADDR, /* lowaddr */ 1944 BUS_SPACE_MAXADDR, /* highaddr */ 1945 NULL, NULL, /* filter, filterarg */ 1946 sctx->isc_rx_maxsize, /* maxsize */ 1947 sctx->isc_rx_nsegments, /* nsegments */ 1948 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1949 0, /* flags */ 1950 NULL, /* lockfunc */ 1951 NULL, /* lockarg */ 1952 &fl->ifl_buf_tag); 1953 if (err) { 1954 device_printf(dev, 1955 "Unable to allocate RX DMA tag: %d\n", err); 1956 goto fail; 1957 } 1958 1959 /* Allocate memory for the RX mbuf map. */ 1960 if (!(fl->ifl_sds.ifsd_m = 1961 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1962 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1963 device_printf(dev, 1964 "Unable to allocate RX mbuf map memory\n"); 1965 err = ENOMEM; 1966 goto fail; 1967 } 1968 1969 /* Allocate memory for the direct RX cluster pointer map. */ 1970 if (!(fl->ifl_sds.ifsd_cl = 1971 (caddr_t *) malloc(sizeof(caddr_t) * 1972 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1973 device_printf(dev, 1974 "Unable to allocate RX cluster map memory\n"); 1975 err = ENOMEM; 1976 goto fail; 1977 } 1978 1979 /* Allocate memory for the RX cluster bus address map. */ 1980 if (!(fl->ifl_sds.ifsd_ba = 1981 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1982 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1983 device_printf(dev, 1984 "Unable to allocate RX bus address map memory\n"); 1985 err = ENOMEM; 1986 goto fail; 1987 } 1988 1989 /* 1990 * Create the DMA maps for RX buffers. 1991 */ 1992 if (!(fl->ifl_sds.ifsd_map = 1993 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1994 device_printf(dev, 1995 "Unable to allocate RX buffer DMA map memory\n"); 1996 err = ENOMEM; 1997 goto fail; 1998 } 1999 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2000 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2001 &fl->ifl_sds.ifsd_map[i]); 2002 if (err != 0) { 2003 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2004 goto fail; 2005 } 2006 } 2007 } 2008 return (0); 2009 2010 fail: 2011 iflib_rx_structures_free(ctx); 2012 return (err); 2013 } 2014 2015 /* 2016 * Internal service routines 2017 */ 2018 2019 struct rxq_refill_cb_arg { 2020 int error; 2021 bus_dma_segment_t seg; 2022 int nseg; 2023 }; 2024 2025 static void 2026 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2027 { 2028 struct rxq_refill_cb_arg *cb_arg = arg; 2029 2030 cb_arg->error = error; 2031 cb_arg->seg = segs[0]; 2032 cb_arg->nseg = nseg; 2033 } 2034 2035 /** 2036 * iflib_fl_refill - refill an rxq free-buffer list 2037 * @ctx: the iflib context 2038 * @fl: the free list to refill 2039 * @count: the number of new buffers to allocate 2040 * 2041 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2042 * The caller must assure that @count does not exceed the queue's capacity 2043 * minus one (since we always leave a descriptor unavailable). 2044 */ 2045 static uint8_t 2046 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2047 { 2048 struct if_rxd_update iru; 2049 struct rxq_refill_cb_arg cb_arg; 2050 struct mbuf *m; 2051 caddr_t cl, *sd_cl; 2052 struct mbuf **sd_m; 2053 bus_dmamap_t *sd_map; 2054 bus_addr_t bus_addr, *sd_ba; 2055 int err, frag_idx, i, idx, n, pidx; 2056 qidx_t credits; 2057 2058 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2059 2060 sd_m = fl->ifl_sds.ifsd_m; 2061 sd_map = fl->ifl_sds.ifsd_map; 2062 sd_cl = fl->ifl_sds.ifsd_cl; 2063 sd_ba = fl->ifl_sds.ifsd_ba; 2064 pidx = fl->ifl_pidx; 2065 idx = pidx; 2066 frag_idx = fl->ifl_fragidx; 2067 credits = fl->ifl_credits; 2068 2069 i = 0; 2070 n = count; 2071 MPASS(n > 0); 2072 MPASS(credits + n <= fl->ifl_size); 2073 2074 if (pidx < fl->ifl_cidx) 2075 MPASS(pidx + n <= fl->ifl_cidx); 2076 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2077 MPASS(fl->ifl_gen == 0); 2078 if (pidx > fl->ifl_cidx) 2079 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2080 2081 DBG_COUNTER_INC(fl_refills); 2082 if (n > 8) 2083 DBG_COUNTER_INC(fl_refills_large); 2084 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2085 while (n-- > 0) { 2086 /* 2087 * We allocate an uninitialized mbuf + cluster, mbuf is 2088 * initialized after rx. 2089 * 2090 * If the cluster is still set then we know a minimum sized 2091 * packet was received 2092 */ 2093 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2094 &frag_idx); 2095 if (frag_idx < 0) 2096 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2097 MPASS(frag_idx >= 0); 2098 if ((cl = sd_cl[frag_idx]) == NULL) { 2099 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2100 if (__predict_false(cl == NULL)) 2101 break; 2102 2103 cb_arg.error = 0; 2104 MPASS(sd_map != NULL); 2105 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2106 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2107 BUS_DMA_NOWAIT); 2108 if (__predict_false(err != 0 || cb_arg.error)) { 2109 uma_zfree(fl->ifl_zone, cl); 2110 break; 2111 } 2112 2113 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2114 sd_cl[frag_idx] = cl; 2115 #if MEMORY_LOGGING 2116 fl->ifl_cl_enqueued++; 2117 #endif 2118 } else { 2119 bus_addr = sd_ba[frag_idx]; 2120 } 2121 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2122 BUS_DMASYNC_PREREAD); 2123 2124 if (sd_m[frag_idx] == NULL) { 2125 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2126 if (__predict_false(m == NULL)) 2127 break; 2128 sd_m[frag_idx] = m; 2129 } 2130 bit_set(fl->ifl_rx_bitmap, frag_idx); 2131 #if MEMORY_LOGGING 2132 fl->ifl_m_enqueued++; 2133 #endif 2134 2135 DBG_COUNTER_INC(rx_allocs); 2136 fl->ifl_rxd_idxs[i] = frag_idx; 2137 fl->ifl_bus_addrs[i] = bus_addr; 2138 credits++; 2139 i++; 2140 MPASS(credits <= fl->ifl_size); 2141 if (++idx == fl->ifl_size) { 2142 #ifdef INVARIANTS 2143 fl->ifl_gen = 1; 2144 #endif 2145 idx = 0; 2146 } 2147 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2148 iru.iru_pidx = pidx; 2149 iru.iru_count = i; 2150 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2151 fl->ifl_pidx = idx; 2152 fl->ifl_credits = credits; 2153 pidx = idx; 2154 i = 0; 2155 } 2156 } 2157 2158 if (n < count - 1) { 2159 if (i != 0) { 2160 iru.iru_pidx = pidx; 2161 iru.iru_count = i; 2162 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2163 fl->ifl_pidx = idx; 2164 fl->ifl_credits = credits; 2165 } 2166 DBG_COUNTER_INC(rxd_flush); 2167 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2169 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2170 fl->ifl_id, fl->ifl_pidx); 2171 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2172 fl->ifl_fragidx = frag_idx + 1; 2173 if (fl->ifl_fragidx == fl->ifl_size) 2174 fl->ifl_fragidx = 0; 2175 } else { 2176 fl->ifl_fragidx = frag_idx; 2177 } 2178 } 2179 2180 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2181 } 2182 2183 static inline uint8_t 2184 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2185 { 2186 /* 2187 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2188 * This is important as it confuses most NICs. For instance, 2189 * Intel NICs have (per receive ring) RDH and RDT registers, where 2190 * RDH points to the next receive descriptor to be used by the NIC, 2191 * and RDT for the next receive descriptor to be published by the 2192 * driver to the NIC (RDT - 1 is thus the last valid one). 2193 * The condition RDH == RDT means no descriptors are available to 2194 * the NIC, and thus it would be ambiguous if it also meant that 2195 * all the descriptors are available to the NIC. 2196 */ 2197 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2198 #ifdef INVARIANTS 2199 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2200 #endif 2201 2202 MPASS(fl->ifl_credits <= fl->ifl_size); 2203 MPASS(reclaimable == delta); 2204 2205 if (reclaimable > 0) 2206 return (iflib_fl_refill(ctx, fl, reclaimable)); 2207 return (0); 2208 } 2209 2210 uint8_t 2211 iflib_in_detach(if_ctx_t ctx) 2212 { 2213 bool in_detach; 2214 2215 STATE_LOCK(ctx); 2216 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2217 STATE_UNLOCK(ctx); 2218 return (in_detach); 2219 } 2220 2221 static void 2222 iflib_fl_bufs_free(iflib_fl_t fl) 2223 { 2224 iflib_dma_info_t idi = fl->ifl_ifdi; 2225 bus_dmamap_t sd_map; 2226 uint32_t i; 2227 2228 for (i = 0; i < fl->ifl_size; i++) { 2229 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2230 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2231 2232 if (*sd_cl != NULL) { 2233 sd_map = fl->ifl_sds.ifsd_map[i]; 2234 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2235 BUS_DMASYNC_POSTREAD); 2236 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2237 uma_zfree(fl->ifl_zone, *sd_cl); 2238 *sd_cl = NULL; 2239 if (*sd_m != NULL) { 2240 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2241 m_free_raw(*sd_m); 2242 *sd_m = NULL; 2243 } 2244 } else { 2245 MPASS(*sd_m == NULL); 2246 } 2247 #if MEMORY_LOGGING 2248 fl->ifl_m_dequeued++; 2249 fl->ifl_cl_dequeued++; 2250 #endif 2251 } 2252 #ifdef INVARIANTS 2253 for (i = 0; i < fl->ifl_size; i++) { 2254 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2255 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2256 } 2257 #endif 2258 /* 2259 * Reset free list values 2260 */ 2261 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2262 bzero(idi->idi_vaddr, idi->idi_size); 2263 } 2264 2265 /********************************************************************* 2266 * 2267 * Initialize a free list and its buffers. 2268 * 2269 **********************************************************************/ 2270 static int 2271 iflib_fl_setup(iflib_fl_t fl) 2272 { 2273 iflib_rxq_t rxq = fl->ifl_rxq; 2274 if_ctx_t ctx = rxq->ifr_ctx; 2275 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2276 int qidx; 2277 2278 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2279 /* 2280 ** Free current RX buffer structs and their mbufs 2281 */ 2282 iflib_fl_bufs_free(fl); 2283 /* Now replenish the mbufs */ 2284 MPASS(fl->ifl_credits == 0); 2285 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2286 if (scctx->isc_rxd_buf_size[qidx] != 0) 2287 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2288 else 2289 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2290 /* 2291 * ifl_buf_size may be a driver-supplied value, so pull it up 2292 * to the selected mbuf size. 2293 */ 2294 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2295 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2296 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2297 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2298 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2299 2300 /* 2301 * Avoid pre-allocating zillions of clusters to an idle card 2302 * potentially speeding up attach. In any case make sure 2303 * to leave a descriptor unavailable. See the comment in 2304 * iflib_fl_refill_all(). 2305 */ 2306 MPASS(fl->ifl_size > 0); 2307 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2308 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2309 return (ENOBUFS); 2310 /* 2311 * handle failure 2312 */ 2313 MPASS(rxq != NULL); 2314 MPASS(fl->ifl_ifdi != NULL); 2315 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2317 return (0); 2318 } 2319 2320 /********************************************************************* 2321 * 2322 * Free receive ring data structures 2323 * 2324 **********************************************************************/ 2325 static void 2326 iflib_rx_sds_free(iflib_rxq_t rxq) 2327 { 2328 iflib_fl_t fl; 2329 int i, j; 2330 2331 if (rxq->ifr_fl != NULL) { 2332 for (i = 0; i < rxq->ifr_nfl; i++) { 2333 fl = &rxq->ifr_fl[i]; 2334 if (fl->ifl_buf_tag != NULL) { 2335 if (fl->ifl_sds.ifsd_map != NULL) { 2336 for (j = 0; j < fl->ifl_size; j++) { 2337 bus_dmamap_sync( 2338 fl->ifl_buf_tag, 2339 fl->ifl_sds.ifsd_map[j], 2340 BUS_DMASYNC_POSTREAD); 2341 bus_dmamap_unload( 2342 fl->ifl_buf_tag, 2343 fl->ifl_sds.ifsd_map[j]); 2344 bus_dmamap_destroy( 2345 fl->ifl_buf_tag, 2346 fl->ifl_sds.ifsd_map[j]); 2347 } 2348 } 2349 bus_dma_tag_destroy(fl->ifl_buf_tag); 2350 fl->ifl_buf_tag = NULL; 2351 } 2352 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2353 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2354 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2355 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2356 free(fl->ifl_rx_bitmap, M_IFLIB); 2357 fl->ifl_sds.ifsd_m = NULL; 2358 fl->ifl_sds.ifsd_cl = NULL; 2359 fl->ifl_sds.ifsd_ba = NULL; 2360 fl->ifl_sds.ifsd_map = NULL; 2361 fl->ifl_rx_bitmap = NULL; 2362 } 2363 free(rxq->ifr_fl, M_IFLIB); 2364 rxq->ifr_fl = NULL; 2365 free(rxq->ifr_ifdi, M_IFLIB); 2366 rxq->ifr_ifdi = NULL; 2367 rxq->ifr_cq_cidx = 0; 2368 } 2369 } 2370 2371 /* 2372 * Timer routine 2373 */ 2374 static void 2375 iflib_timer(void *arg) 2376 { 2377 iflib_txq_t txq = arg; 2378 if_ctx_t ctx = txq->ift_ctx; 2379 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2380 uint64_t this_tick = ticks; 2381 2382 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2383 return; 2384 2385 /* 2386 ** Check on the state of the TX queue(s), this 2387 ** can be done without the lock because its RO 2388 ** and the HUNG state will be static if set. 2389 */ 2390 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2391 txq->ift_last_timer_tick = this_tick; 2392 IFDI_TIMER(ctx, txq->ift_id); 2393 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2394 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2395 (sctx->isc_pause_frames == 0))) 2396 goto hung; 2397 2398 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2399 ifmp_ring_is_stalled(txq->ift_br)) { 2400 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2401 ("queue can't be marked as hung if interface is down")); 2402 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2403 } 2404 txq->ift_cleaned_prev = txq->ift_cleaned; 2405 } 2406 /* handle any laggards */ 2407 if (txq->ift_db_pending) 2408 GROUPTASK_ENQUEUE(&txq->ift_task); 2409 2410 sctx->isc_pause_frames = 0; 2411 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2412 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2413 txq, txq->ift_timer.c_cpu); 2414 return; 2415 2416 hung: 2417 device_printf(ctx->ifc_dev, 2418 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2419 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2420 STATE_LOCK(ctx); 2421 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2422 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2423 iflib_admin_intr_deferred(ctx); 2424 STATE_UNLOCK(ctx); 2425 } 2426 2427 static uint16_t 2428 iflib_get_mbuf_size_for(unsigned int size) 2429 { 2430 2431 if (size <= MCLBYTES) 2432 return (MCLBYTES); 2433 else 2434 return (MJUMPAGESIZE); 2435 } 2436 2437 static void 2438 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2439 { 2440 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2441 2442 /* 2443 * XXX don't set the max_frame_size to larger 2444 * than the hardware can handle 2445 */ 2446 ctx->ifc_rx_mbuf_sz = 2447 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2448 } 2449 2450 uint32_t 2451 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2452 { 2453 2454 return (ctx->ifc_rx_mbuf_sz); 2455 } 2456 2457 static void 2458 iflib_init_locked(if_ctx_t ctx) 2459 { 2460 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2462 if_t ifp = ctx->ifc_ifp; 2463 iflib_fl_t fl; 2464 iflib_txq_t txq; 2465 iflib_rxq_t rxq; 2466 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2467 2468 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2469 IFDI_INTR_DISABLE(ctx); 2470 2471 /* 2472 * See iflib_stop(). Useful in case iflib_init_locked() is 2473 * called without first calling iflib_stop(). 2474 */ 2475 netmap_disable_all_rings(ifp); 2476 2477 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2478 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2479 /* Set hardware offload abilities */ 2480 if_clearhwassist(ifp); 2481 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2482 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2483 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2484 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2485 if (if_getcapenable(ifp) & IFCAP_TSO4) 2486 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2487 if (if_getcapenable(ifp) & IFCAP_TSO6) 2488 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2489 2490 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2491 CALLOUT_LOCK(txq); 2492 callout_stop(&txq->ift_timer); 2493 #ifdef DEV_NETMAP 2494 callout_stop(&txq->ift_netmap_timer); 2495 #endif /* DEV_NETMAP */ 2496 CALLOUT_UNLOCK(txq); 2497 iflib_netmap_txq_init(ctx, txq); 2498 } 2499 2500 /* 2501 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2502 * that drivers can use the value when setting up the hardware receive 2503 * buffers. 2504 */ 2505 iflib_calc_rx_mbuf_sz(ctx); 2506 2507 #ifdef INVARIANTS 2508 i = if_getdrvflags(ifp); 2509 #endif 2510 IFDI_INIT(ctx); 2511 MPASS(if_getdrvflags(ifp) == i); 2512 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2513 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2514 /* This rxq is in netmap mode. Skip normal init. */ 2515 continue; 2516 } 2517 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2518 if (iflib_fl_setup(fl)) { 2519 device_printf(ctx->ifc_dev, 2520 "setting up free list %d failed - " 2521 "check cluster settings\n", j); 2522 goto done; 2523 } 2524 } 2525 } 2526 done: 2527 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2528 IFDI_INTR_ENABLE(ctx); 2529 txq = ctx->ifc_txqs; 2530 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2531 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2532 txq->ift_timer.c_cpu); 2533 2534 /* Re-enable txsync/rxsync. */ 2535 netmap_enable_all_rings(ifp); 2536 } 2537 2538 static int 2539 iflib_media_change(if_t ifp) 2540 { 2541 if_ctx_t ctx = if_getsoftc(ifp); 2542 int err; 2543 2544 CTX_LOCK(ctx); 2545 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2546 iflib_if_init_locked(ctx); 2547 CTX_UNLOCK(ctx); 2548 return (err); 2549 } 2550 2551 static void 2552 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2553 { 2554 if_ctx_t ctx = if_getsoftc(ifp); 2555 2556 CTX_LOCK(ctx); 2557 IFDI_UPDATE_ADMIN_STATUS(ctx); 2558 IFDI_MEDIA_STATUS(ctx, ifmr); 2559 CTX_UNLOCK(ctx); 2560 } 2561 2562 void 2563 iflib_stop(if_ctx_t ctx) 2564 { 2565 iflib_txq_t txq = ctx->ifc_txqs; 2566 iflib_rxq_t rxq = ctx->ifc_rxqs; 2567 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2568 if_shared_ctx_t sctx = ctx->ifc_sctx; 2569 iflib_dma_info_t di; 2570 iflib_fl_t fl; 2571 int i, j; 2572 2573 /* Tell the stack that the interface is no longer active */ 2574 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2575 2576 IFDI_INTR_DISABLE(ctx); 2577 DELAY(1000); 2578 IFDI_STOP(ctx); 2579 DELAY(1000); 2580 2581 /* 2582 * Stop any pending txsync/rxsync and prevent new ones 2583 * form starting. Processes blocked in poll() will get 2584 * POLLERR. 2585 */ 2586 netmap_disable_all_rings(ctx->ifc_ifp); 2587 2588 iflib_debug_reset(); 2589 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2590 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2591 /* make sure all transmitters have completed before proceeding XXX */ 2592 2593 CALLOUT_LOCK(txq); 2594 callout_stop(&txq->ift_timer); 2595 #ifdef DEV_NETMAP 2596 callout_stop(&txq->ift_netmap_timer); 2597 #endif /* DEV_NETMAP */ 2598 CALLOUT_UNLOCK(txq); 2599 2600 /* clean any enqueued buffers */ 2601 iflib_ifmp_purge(txq); 2602 /* Free any existing tx buffers. */ 2603 for (j = 0; j < txq->ift_size; j++) { 2604 iflib_txsd_free(ctx, txq, j); 2605 } 2606 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2607 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2608 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2609 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2610 txq->ift_pullups = 0; 2611 ifmp_ring_reset_stats(txq->ift_br); 2612 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2613 bzero((void *)di->idi_vaddr, di->idi_size); 2614 } 2615 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2616 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2617 &rxq->ifr_task.gt_task); 2618 2619 rxq->ifr_cq_cidx = 0; 2620 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2621 bzero((void *)di->idi_vaddr, di->idi_size); 2622 /* also resets the free lists pidx/cidx */ 2623 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2624 iflib_fl_bufs_free(fl); 2625 } 2626 } 2627 2628 static inline caddr_t 2629 calc_next_rxd(iflib_fl_t fl, int cidx) 2630 { 2631 qidx_t size; 2632 int nrxd; 2633 caddr_t start, end, cur, next; 2634 2635 nrxd = fl->ifl_size; 2636 size = fl->ifl_rxd_size; 2637 start = fl->ifl_ifdi->idi_vaddr; 2638 2639 if (__predict_false(size == 0)) 2640 return (start); 2641 cur = start + size*cidx; 2642 end = start + size*nrxd; 2643 next = CACHE_PTR_NEXT(cur); 2644 return (next < end ? next : start); 2645 } 2646 2647 static inline void 2648 prefetch_pkts(iflib_fl_t fl, int cidx) 2649 { 2650 int nextptr; 2651 int nrxd = fl->ifl_size; 2652 caddr_t next_rxd; 2653 2654 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2655 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2656 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2657 next_rxd = calc_next_rxd(fl, cidx); 2658 prefetch(next_rxd); 2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2660 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2661 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2662 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2664 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2665 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2666 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2667 } 2668 2669 static struct mbuf * 2670 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2671 int *pf_rv, if_rxd_info_t ri) 2672 { 2673 bus_dmamap_t map; 2674 iflib_fl_t fl; 2675 caddr_t payload; 2676 struct mbuf *m; 2677 int flid, cidx, len, next; 2678 2679 map = NULL; 2680 flid = irf->irf_flid; 2681 cidx = irf->irf_idx; 2682 fl = &rxq->ifr_fl[flid]; 2683 sd->ifsd_fl = fl; 2684 m = fl->ifl_sds.ifsd_m[cidx]; 2685 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2686 fl->ifl_credits--; 2687 #if MEMORY_LOGGING 2688 fl->ifl_m_dequeued++; 2689 #endif 2690 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2691 prefetch_pkts(fl, cidx); 2692 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2693 prefetch(&fl->ifl_sds.ifsd_map[next]); 2694 map = fl->ifl_sds.ifsd_map[cidx]; 2695 2696 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2697 2698 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2699 irf->irf_len != 0) { 2700 payload = *sd->ifsd_cl; 2701 payload += ri->iri_pad; 2702 len = ri->iri_len - ri->iri_pad; 2703 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2704 len | PFIL_MEMPTR | PFIL_IN, NULL); 2705 switch (*pf_rv) { 2706 case PFIL_DROPPED: 2707 case PFIL_CONSUMED: 2708 /* 2709 * The filter ate it. Everything is recycled. 2710 */ 2711 m = NULL; 2712 unload = 0; 2713 break; 2714 case PFIL_REALLOCED: 2715 /* 2716 * The filter copied it. Everything is recycled. 2717 */ 2718 m = pfil_mem2mbuf(payload); 2719 unload = 0; 2720 break; 2721 case PFIL_PASS: 2722 /* 2723 * Filter said it was OK, so receive like 2724 * normal 2725 */ 2726 fl->ifl_sds.ifsd_m[cidx] = NULL; 2727 break; 2728 default: 2729 MPASS(0); 2730 } 2731 } else { 2732 fl->ifl_sds.ifsd_m[cidx] = NULL; 2733 if (pf_rv != NULL) 2734 *pf_rv = PFIL_PASS; 2735 } 2736 2737 if (unload && irf->irf_len != 0) 2738 bus_dmamap_unload(fl->ifl_buf_tag, map); 2739 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2740 if (__predict_false(fl->ifl_cidx == 0)) 2741 fl->ifl_gen = 0; 2742 bit_clear(fl->ifl_rx_bitmap, cidx); 2743 return (m); 2744 } 2745 2746 static struct mbuf * 2747 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2748 { 2749 struct mbuf *m, *mh, *mt; 2750 caddr_t cl; 2751 int *pf_rv_ptr, flags, i, padlen; 2752 bool consumed; 2753 2754 i = 0; 2755 mh = NULL; 2756 consumed = false; 2757 *pf_rv = PFIL_PASS; 2758 pf_rv_ptr = pf_rv; 2759 do { 2760 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2761 pf_rv_ptr, ri); 2762 2763 MPASS(*sd->ifsd_cl != NULL); 2764 2765 /* 2766 * Exclude zero-length frags & frags from 2767 * packets the filter has consumed or dropped 2768 */ 2769 if (ri->iri_frags[i].irf_len == 0 || consumed || 2770 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2771 if (mh == NULL) { 2772 /* everything saved here */ 2773 consumed = true; 2774 pf_rv_ptr = NULL; 2775 continue; 2776 } 2777 /* XXX we can save the cluster here, but not the mbuf */ 2778 m_init(m, M_NOWAIT, MT_DATA, 0); 2779 m_free(m); 2780 continue; 2781 } 2782 if (mh == NULL) { 2783 flags = M_PKTHDR|M_EXT; 2784 mh = mt = m; 2785 padlen = ri->iri_pad; 2786 } else { 2787 flags = M_EXT; 2788 mt->m_next = m; 2789 mt = m; 2790 /* assuming padding is only on the first fragment */ 2791 padlen = 0; 2792 } 2793 cl = *sd->ifsd_cl; 2794 *sd->ifsd_cl = NULL; 2795 2796 /* Can these two be made one ? */ 2797 m_init(m, M_NOWAIT, MT_DATA, flags); 2798 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2799 /* 2800 * These must follow m_init and m_cljset 2801 */ 2802 m->m_data += padlen; 2803 ri->iri_len -= padlen; 2804 m->m_len = ri->iri_frags[i].irf_len; 2805 } while (++i < ri->iri_nfrags); 2806 2807 return (mh); 2808 } 2809 2810 /* 2811 * Process one software descriptor 2812 */ 2813 static struct mbuf * 2814 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2815 { 2816 struct if_rxsd sd; 2817 struct mbuf *m; 2818 int pf_rv; 2819 2820 /* should I merge this back in now that the two paths are basically duplicated? */ 2821 if (ri->iri_nfrags == 1 && 2822 ri->iri_frags[0].irf_len != 0 && 2823 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2824 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2825 &pf_rv, ri); 2826 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2827 return (m); 2828 if (pf_rv == PFIL_PASS) { 2829 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2830 #ifndef __NO_STRICT_ALIGNMENT 2831 if (!IP_ALIGNED(m)) 2832 m->m_data += 2; 2833 #endif 2834 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2835 m->m_len = ri->iri_frags[0].irf_len; 2836 } 2837 } else { 2838 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2839 if (m == NULL) 2840 return (NULL); 2841 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2842 return (m); 2843 } 2844 m->m_pkthdr.len = ri->iri_len; 2845 m->m_pkthdr.rcvif = ri->iri_ifp; 2846 m->m_flags |= ri->iri_flags; 2847 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2848 m->m_pkthdr.flowid = ri->iri_flowid; 2849 M_HASHTYPE_SET(m, ri->iri_rsstype); 2850 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2851 m->m_pkthdr.csum_data = ri->iri_csum_data; 2852 return (m); 2853 } 2854 2855 #if defined(INET6) || defined(INET) 2856 static void 2857 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2858 { 2859 CURVNET_SET(lc->ifp->if_vnet); 2860 #if defined(INET6) 2861 *v6 = V_ip6_forwarding; 2862 #endif 2863 #if defined(INET) 2864 *v4 = V_ipforwarding; 2865 #endif 2866 CURVNET_RESTORE(); 2867 } 2868 2869 /* 2870 * Returns true if it's possible this packet could be LROed. 2871 * if it returns false, it is guaranteed that tcp_lro_rx() 2872 * would not return zero. 2873 */ 2874 static bool 2875 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2876 { 2877 struct ether_header *eh; 2878 2879 eh = mtod(m, struct ether_header *); 2880 switch (eh->ether_type) { 2881 #if defined(INET6) 2882 case htons(ETHERTYPE_IPV6): 2883 return (!v6_forwarding); 2884 #endif 2885 #if defined (INET) 2886 case htons(ETHERTYPE_IP): 2887 return (!v4_forwarding); 2888 #endif 2889 } 2890 2891 return false; 2892 } 2893 #else 2894 static void 2895 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2896 { 2897 } 2898 #endif 2899 2900 static void 2901 _task_fn_rx_watchdog(void *context) 2902 { 2903 iflib_rxq_t rxq = context; 2904 2905 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2906 } 2907 2908 static uint8_t 2909 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2910 { 2911 if_t ifp; 2912 if_ctx_t ctx = rxq->ifr_ctx; 2913 if_shared_ctx_t sctx = ctx->ifc_sctx; 2914 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2915 int avail, i; 2916 qidx_t *cidxp; 2917 struct if_rxd_info ri; 2918 int err, budget_left, rx_bytes, rx_pkts; 2919 iflib_fl_t fl; 2920 int lro_enabled; 2921 bool v4_forwarding, v6_forwarding, lro_possible; 2922 uint8_t retval = 0; 2923 2924 /* 2925 * XXX early demux data packets so that if_input processing only handles 2926 * acks in interrupt context 2927 */ 2928 struct mbuf *m, *mh, *mt, *mf; 2929 2930 NET_EPOCH_ASSERT(); 2931 2932 lro_possible = v4_forwarding = v6_forwarding = false; 2933 ifp = ctx->ifc_ifp; 2934 mh = mt = NULL; 2935 MPASS(budget > 0); 2936 rx_pkts = rx_bytes = 0; 2937 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2938 cidxp = &rxq->ifr_cq_cidx; 2939 else 2940 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2941 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2942 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2943 retval |= iflib_fl_refill_all(ctx, fl); 2944 DBG_COUNTER_INC(rx_unavail); 2945 return (retval); 2946 } 2947 2948 /* pfil needs the vnet to be set */ 2949 CURVNET_SET_QUIET(ifp->if_vnet); 2950 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2951 if (__predict_false(!CTX_ACTIVE(ctx))) { 2952 DBG_COUNTER_INC(rx_ctx_inactive); 2953 break; 2954 } 2955 /* 2956 * Reset client set fields to their default values 2957 */ 2958 rxd_info_zero(&ri); 2959 ri.iri_qsidx = rxq->ifr_id; 2960 ri.iri_cidx = *cidxp; 2961 ri.iri_ifp = ifp; 2962 ri.iri_frags = rxq->ifr_frags; 2963 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2964 2965 if (err) 2966 goto err; 2967 rx_pkts += 1; 2968 rx_bytes += ri.iri_len; 2969 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2970 *cidxp = ri.iri_cidx; 2971 /* Update our consumer index */ 2972 /* XXX NB: shurd - check if this is still safe */ 2973 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2974 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2975 /* was this only a completion queue message? */ 2976 if (__predict_false(ri.iri_nfrags == 0)) 2977 continue; 2978 } 2979 MPASS(ri.iri_nfrags != 0); 2980 MPASS(ri.iri_len != 0); 2981 2982 /* will advance the cidx on the corresponding free lists */ 2983 m = iflib_rxd_pkt_get(rxq, &ri); 2984 avail--; 2985 budget_left--; 2986 if (avail == 0 && budget_left) 2987 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2988 2989 if (__predict_false(m == NULL)) 2990 continue; 2991 2992 /* imm_pkt: -- cxgb */ 2993 if (mh == NULL) 2994 mh = mt = m; 2995 else { 2996 mt->m_nextpkt = m; 2997 mt = m; 2998 } 2999 } 3000 CURVNET_RESTORE(); 3001 /* make sure that we can refill faster than drain */ 3002 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3003 retval |= iflib_fl_refill_all(ctx, fl); 3004 3005 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3006 if (lro_enabled) 3007 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3008 mt = mf = NULL; 3009 while (mh != NULL) { 3010 m = mh; 3011 mh = mh->m_nextpkt; 3012 m->m_nextpkt = NULL; 3013 #ifndef __NO_STRICT_ALIGNMENT 3014 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3015 continue; 3016 #endif 3017 #if defined(INET6) || defined(INET) 3018 if (lro_enabled) { 3019 if (!lro_possible) { 3020 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3021 if (lro_possible && mf != NULL) { 3022 ifp->if_input(ifp, mf); 3023 DBG_COUNTER_INC(rx_if_input); 3024 mt = mf = NULL; 3025 } 3026 } 3027 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3028 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3029 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3030 continue; 3031 } 3032 } 3033 #endif 3034 if (lro_possible) { 3035 ifp->if_input(ifp, m); 3036 DBG_COUNTER_INC(rx_if_input); 3037 continue; 3038 } 3039 3040 if (mf == NULL) 3041 mf = m; 3042 if (mt != NULL) 3043 mt->m_nextpkt = m; 3044 mt = m; 3045 } 3046 if (mf != NULL) { 3047 ifp->if_input(ifp, mf); 3048 DBG_COUNTER_INC(rx_if_input); 3049 } 3050 3051 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3052 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3053 3054 /* 3055 * Flush any outstanding LRO work 3056 */ 3057 #if defined(INET6) || defined(INET) 3058 tcp_lro_flush_all(&rxq->ifr_lc); 3059 #endif 3060 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3061 retval |= IFLIB_RXEOF_MORE; 3062 return (retval); 3063 err: 3064 STATE_LOCK(ctx); 3065 ctx->ifc_flags |= IFC_DO_RESET; 3066 iflib_admin_intr_deferred(ctx); 3067 STATE_UNLOCK(ctx); 3068 return (0); 3069 } 3070 3071 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3072 static inline qidx_t 3073 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3074 { 3075 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3076 qidx_t minthresh = txq->ift_size / 8; 3077 if (in_use > 4*minthresh) 3078 return (notify_count); 3079 if (in_use > 2*minthresh) 3080 return (notify_count >> 1); 3081 if (in_use > minthresh) 3082 return (notify_count >> 3); 3083 return (0); 3084 } 3085 3086 static inline qidx_t 3087 txq_max_rs_deferred(iflib_txq_t txq) 3088 { 3089 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3090 qidx_t minthresh = txq->ift_size / 8; 3091 if (txq->ift_in_use > 4*minthresh) 3092 return (notify_count); 3093 if (txq->ift_in_use > 2*minthresh) 3094 return (notify_count >> 1); 3095 if (txq->ift_in_use > minthresh) 3096 return (notify_count >> 2); 3097 return (2); 3098 } 3099 3100 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3101 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3102 3103 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3104 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3105 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3106 3107 /* forward compatibility for cxgb */ 3108 #define FIRST_QSET(ctx) 0 3109 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3110 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3111 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3112 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3113 3114 /* XXX we should be setting this to something other than zero */ 3115 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3116 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3117 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3118 3119 static inline bool 3120 iflib_txd_db_check(iflib_txq_t txq, int ring) 3121 { 3122 if_ctx_t ctx = txq->ift_ctx; 3123 qidx_t dbval, max; 3124 3125 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3126 3127 /* force || threshold exceeded || at the edge of the ring */ 3128 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3129 3130 /* 3131 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3132 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3133 * producer index explicitly (INTC). 3134 */ 3135 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3136 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3137 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3138 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3139 3140 /* 3141 * Absent bugs there are zero packets pending so reset pending counts to zero. 3142 */ 3143 txq->ift_db_pending = txq->ift_npending = 0; 3144 return (true); 3145 } 3146 return (false); 3147 } 3148 3149 #ifdef PKT_DEBUG 3150 static void 3151 print_pkt(if_pkt_info_t pi) 3152 { 3153 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3154 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3155 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3156 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3157 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3158 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3159 } 3160 #endif 3161 3162 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3163 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3164 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3165 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3166 3167 static int 3168 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3169 { 3170 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3171 struct ether_vlan_header *eh; 3172 struct mbuf *m; 3173 3174 m = *mp; 3175 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3176 M_WRITABLE(m) == 0) { 3177 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3178 return (ENOMEM); 3179 } else { 3180 m_freem(*mp); 3181 DBG_COUNTER_INC(tx_frees); 3182 *mp = m; 3183 } 3184 } 3185 3186 /* 3187 * Determine where frame payload starts. 3188 * Jump over vlan headers if already present, 3189 * helpful for QinQ too. 3190 */ 3191 if (__predict_false(m->m_len < sizeof(*eh))) { 3192 txq->ift_pullups++; 3193 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3194 return (ENOMEM); 3195 } 3196 eh = mtod(m, struct ether_vlan_header *); 3197 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3198 pi->ipi_etype = ntohs(eh->evl_proto); 3199 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3200 } else { 3201 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3202 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3203 } 3204 3205 switch (pi->ipi_etype) { 3206 #ifdef INET 3207 case ETHERTYPE_IP: 3208 { 3209 struct mbuf *n; 3210 struct ip *ip = NULL; 3211 struct tcphdr *th = NULL; 3212 int minthlen; 3213 3214 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3215 if (__predict_false(m->m_len < minthlen)) { 3216 /* 3217 * if this code bloat is causing too much of a hit 3218 * move it to a separate function and mark it noinline 3219 */ 3220 if (m->m_len == pi->ipi_ehdrlen) { 3221 n = m->m_next; 3222 MPASS(n); 3223 if (n->m_len >= sizeof(*ip)) { 3224 ip = (struct ip *)n->m_data; 3225 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3226 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3227 } else { 3228 txq->ift_pullups++; 3229 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3230 return (ENOMEM); 3231 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3232 } 3233 } else { 3234 txq->ift_pullups++; 3235 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3236 return (ENOMEM); 3237 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3238 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3239 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3240 } 3241 } else { 3242 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3243 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3244 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3245 } 3246 pi->ipi_ip_hlen = ip->ip_hl << 2; 3247 pi->ipi_ipproto = ip->ip_p; 3248 pi->ipi_flags |= IPI_TX_IPV4; 3249 3250 /* TCP checksum offload may require TCP header length */ 3251 if (IS_TX_OFFLOAD4(pi)) { 3252 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3253 if (__predict_false(th == NULL)) { 3254 txq->ift_pullups++; 3255 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3256 return (ENOMEM); 3257 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3258 } 3259 pi->ipi_tcp_hflags = th->th_flags; 3260 pi->ipi_tcp_hlen = th->th_off << 2; 3261 pi->ipi_tcp_seq = th->th_seq; 3262 } 3263 if (IS_TSO4(pi)) { 3264 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3265 return (ENXIO); 3266 /* 3267 * TSO always requires hardware checksum offload. 3268 */ 3269 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3270 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3271 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3272 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3273 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3274 ip->ip_sum = 0; 3275 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3276 } 3277 } 3278 } 3279 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3280 ip->ip_sum = 0; 3281 3282 break; 3283 } 3284 #endif 3285 #ifdef INET6 3286 case ETHERTYPE_IPV6: 3287 { 3288 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3289 struct tcphdr *th; 3290 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3291 3292 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3293 txq->ift_pullups++; 3294 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3295 return (ENOMEM); 3296 } 3297 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3298 3299 /* XXX-BZ this will go badly in case of ext hdrs. */ 3300 pi->ipi_ipproto = ip6->ip6_nxt; 3301 pi->ipi_flags |= IPI_TX_IPV6; 3302 3303 /* TCP checksum offload may require TCP header length */ 3304 if (IS_TX_OFFLOAD6(pi)) { 3305 if (pi->ipi_ipproto == IPPROTO_TCP) { 3306 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3307 txq->ift_pullups++; 3308 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3309 return (ENOMEM); 3310 } 3311 pi->ipi_tcp_hflags = th->th_flags; 3312 pi->ipi_tcp_hlen = th->th_off << 2; 3313 pi->ipi_tcp_seq = th->th_seq; 3314 } 3315 if (IS_TSO6(pi)) { 3316 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3317 return (ENXIO); 3318 /* 3319 * TSO always requires hardware checksum offload. 3320 */ 3321 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3322 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3323 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3324 } 3325 } 3326 break; 3327 } 3328 #endif 3329 default: 3330 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3331 pi->ipi_ip_hlen = 0; 3332 break; 3333 } 3334 *mp = m; 3335 3336 return (0); 3337 } 3338 3339 /* 3340 * If dodgy hardware rejects the scatter gather chain we've handed it 3341 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3342 * m_defrag'd mbufs 3343 */ 3344 static __noinline struct mbuf * 3345 iflib_remove_mbuf(iflib_txq_t txq) 3346 { 3347 int ntxd, pidx; 3348 struct mbuf *m, **ifsd_m; 3349 3350 ifsd_m = txq->ift_sds.ifsd_m; 3351 ntxd = txq->ift_size; 3352 pidx = txq->ift_pidx & (ntxd - 1); 3353 ifsd_m = txq->ift_sds.ifsd_m; 3354 m = ifsd_m[pidx]; 3355 ifsd_m[pidx] = NULL; 3356 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3357 if (txq->ift_sds.ifsd_tso_map != NULL) 3358 bus_dmamap_unload(txq->ift_tso_buf_tag, 3359 txq->ift_sds.ifsd_tso_map[pidx]); 3360 #if MEMORY_LOGGING 3361 txq->ift_dequeued++; 3362 #endif 3363 return (m); 3364 } 3365 3366 static inline caddr_t 3367 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3368 { 3369 qidx_t size; 3370 int ntxd; 3371 caddr_t start, end, cur, next; 3372 3373 ntxd = txq->ift_size; 3374 size = txq->ift_txd_size[qid]; 3375 start = txq->ift_ifdi[qid].idi_vaddr; 3376 3377 if (__predict_false(size == 0)) 3378 return (start); 3379 cur = start + size*cidx; 3380 end = start + size*ntxd; 3381 next = CACHE_PTR_NEXT(cur); 3382 return (next < end ? next : start); 3383 } 3384 3385 /* 3386 * Pad an mbuf to ensure a minimum ethernet frame size. 3387 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3388 */ 3389 static __noinline int 3390 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3391 { 3392 /* 3393 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3394 * and ARP message is the smallest common payload I can think of 3395 */ 3396 static char pad[18]; /* just zeros */ 3397 int n; 3398 struct mbuf *new_head; 3399 3400 if (!M_WRITABLE(*m_head)) { 3401 new_head = m_dup(*m_head, M_NOWAIT); 3402 if (new_head == NULL) { 3403 m_freem(*m_head); 3404 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3405 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3406 DBG_COUNTER_INC(tx_frees); 3407 return ENOMEM; 3408 } 3409 m_freem(*m_head); 3410 *m_head = new_head; 3411 } 3412 3413 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3414 n > 0; n -= sizeof(pad)) 3415 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3416 break; 3417 3418 if (n > 0) { 3419 m_freem(*m_head); 3420 device_printf(dev, "cannot pad short frame\n"); 3421 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3422 DBG_COUNTER_INC(tx_frees); 3423 return (ENOBUFS); 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int 3430 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3431 { 3432 if_ctx_t ctx; 3433 if_shared_ctx_t sctx; 3434 if_softc_ctx_t scctx; 3435 bus_dma_tag_t buf_tag; 3436 bus_dma_segment_t *segs; 3437 struct mbuf *m_head, **ifsd_m; 3438 void *next_txd; 3439 bus_dmamap_t map; 3440 struct if_pkt_info pi; 3441 int remap = 0; 3442 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3443 3444 ctx = txq->ift_ctx; 3445 sctx = ctx->ifc_sctx; 3446 scctx = &ctx->ifc_softc_ctx; 3447 segs = txq->ift_segs; 3448 ntxd = txq->ift_size; 3449 m_head = *m_headp; 3450 map = NULL; 3451 3452 /* 3453 * If we're doing TSO the next descriptor to clean may be quite far ahead 3454 */ 3455 cidx = txq->ift_cidx; 3456 pidx = txq->ift_pidx; 3457 if (ctx->ifc_flags & IFC_PREFETCH) { 3458 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3459 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3460 next_txd = calc_next_txd(txq, cidx, 0); 3461 prefetch(next_txd); 3462 } 3463 3464 /* prefetch the next cache line of mbuf pointers and flags */ 3465 prefetch(&txq->ift_sds.ifsd_m[next]); 3466 prefetch(&txq->ift_sds.ifsd_map[next]); 3467 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3468 } 3469 map = txq->ift_sds.ifsd_map[pidx]; 3470 ifsd_m = txq->ift_sds.ifsd_m; 3471 3472 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3473 buf_tag = txq->ift_tso_buf_tag; 3474 max_segs = scctx->isc_tx_tso_segments_max; 3475 map = txq->ift_sds.ifsd_tso_map[pidx]; 3476 MPASS(buf_tag != NULL); 3477 MPASS(max_segs > 0); 3478 } else { 3479 buf_tag = txq->ift_buf_tag; 3480 max_segs = scctx->isc_tx_nsegments; 3481 map = txq->ift_sds.ifsd_map[pidx]; 3482 } 3483 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3484 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3485 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3486 if (err) { 3487 DBG_COUNTER_INC(encap_txd_encap_fail); 3488 return err; 3489 } 3490 } 3491 m_head = *m_headp; 3492 3493 pkt_info_zero(&pi); 3494 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3495 pi.ipi_pidx = pidx; 3496 pi.ipi_qsidx = txq->ift_id; 3497 pi.ipi_len = m_head->m_pkthdr.len; 3498 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3499 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3500 3501 /* deliberate bitwise OR to make one condition */ 3502 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3503 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3504 DBG_COUNTER_INC(encap_txd_encap_fail); 3505 return (err); 3506 } 3507 m_head = *m_headp; 3508 } 3509 3510 retry: 3511 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3512 BUS_DMA_NOWAIT); 3513 defrag: 3514 if (__predict_false(err)) { 3515 switch (err) { 3516 case EFBIG: 3517 /* try collapse once and defrag once */ 3518 if (remap == 0) { 3519 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3520 /* try defrag if collapsing fails */ 3521 if (m_head == NULL) 3522 remap++; 3523 } 3524 if (remap == 1) { 3525 txq->ift_mbuf_defrag++; 3526 m_head = m_defrag(*m_headp, M_NOWAIT); 3527 } 3528 /* 3529 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3530 * failed to map an mbuf that was run through m_defrag 3531 */ 3532 MPASS(remap <= 1); 3533 if (__predict_false(m_head == NULL || remap > 1)) 3534 goto defrag_failed; 3535 remap++; 3536 *m_headp = m_head; 3537 goto retry; 3538 break; 3539 case ENOMEM: 3540 txq->ift_no_tx_dma_setup++; 3541 break; 3542 default: 3543 txq->ift_no_tx_dma_setup++; 3544 m_freem(*m_headp); 3545 DBG_COUNTER_INC(tx_frees); 3546 *m_headp = NULL; 3547 break; 3548 } 3549 txq->ift_map_failed++; 3550 DBG_COUNTER_INC(encap_load_mbuf_fail); 3551 DBG_COUNTER_INC(encap_txd_encap_fail); 3552 return (err); 3553 } 3554 ifsd_m[pidx] = m_head; 3555 /* 3556 * XXX assumes a 1 to 1 relationship between segments and 3557 * descriptors - this does not hold true on all drivers, e.g. 3558 * cxgb 3559 */ 3560 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3561 txq->ift_no_desc_avail++; 3562 bus_dmamap_unload(buf_tag, map); 3563 DBG_COUNTER_INC(encap_txq_avail_fail); 3564 DBG_COUNTER_INC(encap_txd_encap_fail); 3565 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3566 GROUPTASK_ENQUEUE(&txq->ift_task); 3567 return (ENOBUFS); 3568 } 3569 /* 3570 * On Intel cards we can greatly reduce the number of TX interrupts 3571 * we see by only setting report status on every Nth descriptor. 3572 * However, this also means that the driver will need to keep track 3573 * of the descriptors that RS was set on to check them for the DD bit. 3574 */ 3575 txq->ift_rs_pending += nsegs + 1; 3576 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3577 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3578 pi.ipi_flags |= IPI_TX_INTR; 3579 txq->ift_rs_pending = 0; 3580 } 3581 3582 pi.ipi_segs = segs; 3583 pi.ipi_nsegs = nsegs; 3584 3585 MPASS(pidx >= 0 && pidx < txq->ift_size); 3586 #ifdef PKT_DEBUG 3587 print_pkt(&pi); 3588 #endif 3589 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3590 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3591 DBG_COUNTER_INC(tx_encap); 3592 MPASS(pi.ipi_new_pidx < txq->ift_size); 3593 3594 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3595 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3596 ndesc += txq->ift_size; 3597 txq->ift_gen = 1; 3598 } 3599 /* 3600 * drivers can need as many as 3601 * two sentinels 3602 */ 3603 MPASS(ndesc <= pi.ipi_nsegs + 2); 3604 MPASS(pi.ipi_new_pidx != pidx); 3605 MPASS(ndesc > 0); 3606 txq->ift_in_use += ndesc; 3607 txq->ift_db_pending += ndesc; 3608 3609 /* 3610 * We update the last software descriptor again here because there may 3611 * be a sentinel and/or there may be more mbufs than segments 3612 */ 3613 txq->ift_pidx = pi.ipi_new_pidx; 3614 txq->ift_npending += pi.ipi_ndescs; 3615 } else { 3616 *m_headp = m_head = iflib_remove_mbuf(txq); 3617 if (err == EFBIG) { 3618 txq->ift_txd_encap_efbig++; 3619 if (remap < 2) { 3620 remap = 1; 3621 goto defrag; 3622 } 3623 } 3624 goto defrag_failed; 3625 } 3626 /* 3627 * err can't possibly be non-zero here, so we don't neet to test it 3628 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3629 */ 3630 return (err); 3631 3632 defrag_failed: 3633 txq->ift_mbuf_defrag_failed++; 3634 txq->ift_map_failed++; 3635 m_freem(*m_headp); 3636 DBG_COUNTER_INC(tx_frees); 3637 *m_headp = NULL; 3638 DBG_COUNTER_INC(encap_txd_encap_fail); 3639 return (ENOMEM); 3640 } 3641 3642 static void 3643 iflib_tx_desc_free(iflib_txq_t txq, int n) 3644 { 3645 uint32_t qsize, cidx, mask, gen; 3646 struct mbuf *m, **ifsd_m; 3647 bool do_prefetch; 3648 3649 cidx = txq->ift_cidx; 3650 gen = txq->ift_gen; 3651 qsize = txq->ift_size; 3652 mask = qsize-1; 3653 ifsd_m = txq->ift_sds.ifsd_m; 3654 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3655 3656 while (n-- > 0) { 3657 if (do_prefetch) { 3658 prefetch(ifsd_m[(cidx + 3) & mask]); 3659 prefetch(ifsd_m[(cidx + 4) & mask]); 3660 } 3661 if ((m = ifsd_m[cidx]) != NULL) { 3662 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3663 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3664 bus_dmamap_sync(txq->ift_tso_buf_tag, 3665 txq->ift_sds.ifsd_tso_map[cidx], 3666 BUS_DMASYNC_POSTWRITE); 3667 bus_dmamap_unload(txq->ift_tso_buf_tag, 3668 txq->ift_sds.ifsd_tso_map[cidx]); 3669 } else { 3670 bus_dmamap_sync(txq->ift_buf_tag, 3671 txq->ift_sds.ifsd_map[cidx], 3672 BUS_DMASYNC_POSTWRITE); 3673 bus_dmamap_unload(txq->ift_buf_tag, 3674 txq->ift_sds.ifsd_map[cidx]); 3675 } 3676 /* XXX we don't support any drivers that batch packets yet */ 3677 MPASS(m->m_nextpkt == NULL); 3678 m_freem(m); 3679 ifsd_m[cidx] = NULL; 3680 #if MEMORY_LOGGING 3681 txq->ift_dequeued++; 3682 #endif 3683 DBG_COUNTER_INC(tx_frees); 3684 } 3685 if (__predict_false(++cidx == qsize)) { 3686 cidx = 0; 3687 gen = 0; 3688 } 3689 } 3690 txq->ift_cidx = cidx; 3691 txq->ift_gen = gen; 3692 } 3693 3694 static __inline int 3695 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3696 { 3697 int reclaim; 3698 if_ctx_t ctx = txq->ift_ctx; 3699 3700 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3701 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3702 3703 /* 3704 * Need a rate-limiting check so that this isn't called every time 3705 */ 3706 iflib_tx_credits_update(ctx, txq); 3707 reclaim = DESC_RECLAIMABLE(txq); 3708 3709 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3710 #ifdef INVARIANTS 3711 if (iflib_verbose_debug) { 3712 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3713 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3714 reclaim, thresh); 3715 } 3716 #endif 3717 return (0); 3718 } 3719 iflib_tx_desc_free(txq, reclaim); 3720 txq->ift_cleaned += reclaim; 3721 txq->ift_in_use -= reclaim; 3722 3723 return (reclaim); 3724 } 3725 3726 static struct mbuf ** 3727 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3728 { 3729 int next, size; 3730 struct mbuf **items; 3731 3732 size = r->size; 3733 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3734 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3735 3736 prefetch(items[(cidx + offset) & (size-1)]); 3737 if (remaining > 1) { 3738 prefetch2cachelines(&items[next]); 3739 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3740 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3741 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3742 } 3743 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3744 } 3745 3746 static void 3747 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3748 { 3749 3750 ifmp_ring_check_drainage(txq->ift_br, budget); 3751 } 3752 3753 static uint32_t 3754 iflib_txq_can_drain(struct ifmp_ring *r) 3755 { 3756 iflib_txq_t txq = r->cookie; 3757 if_ctx_t ctx = txq->ift_ctx; 3758 3759 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3760 return (1); 3761 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3762 BUS_DMASYNC_POSTREAD); 3763 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3764 false)); 3765 } 3766 3767 static uint32_t 3768 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3769 { 3770 iflib_txq_t txq = r->cookie; 3771 if_ctx_t ctx = txq->ift_ctx; 3772 if_t ifp = ctx->ifc_ifp; 3773 struct mbuf *m, **mp; 3774 int avail, bytes_sent, skipped, count, err, i; 3775 int mcast_sent, pkt_sent, reclaimed; 3776 bool do_prefetch, rang, ring; 3777 3778 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3779 !LINK_ACTIVE(ctx))) { 3780 DBG_COUNTER_INC(txq_drain_notready); 3781 return (0); 3782 } 3783 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3784 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3785 avail = IDXDIFF(pidx, cidx, r->size); 3786 3787 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3788 /* 3789 * The driver is unloading so we need to free all pending packets. 3790 */ 3791 DBG_COUNTER_INC(txq_drain_flushing); 3792 for (i = 0; i < avail; i++) { 3793 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3794 m_freem(r->items[(cidx + i) & (r->size-1)]); 3795 r->items[(cidx + i) & (r->size-1)] = NULL; 3796 } 3797 return (avail); 3798 } 3799 3800 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3801 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3802 CALLOUT_LOCK(txq); 3803 callout_stop(&txq->ift_timer); 3804 CALLOUT_UNLOCK(txq); 3805 DBG_COUNTER_INC(txq_drain_oactive); 3806 return (0); 3807 } 3808 3809 /* 3810 * If we've reclaimed any packets this queue cannot be hung. 3811 */ 3812 if (reclaimed) 3813 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3814 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3815 count = MIN(avail, TX_BATCH_SIZE); 3816 #ifdef INVARIANTS 3817 if (iflib_verbose_debug) 3818 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3819 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3820 #endif 3821 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3822 err = 0; 3823 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3824 int rem = do_prefetch ? count - i : 0; 3825 3826 mp = _ring_peek_one(r, cidx, i, rem); 3827 MPASS(mp != NULL && *mp != NULL); 3828 3829 /* 3830 * Completion interrupts will use the address of the txq 3831 * as a sentinel to enqueue _something_ in order to acquire 3832 * the lock on the mp_ring (there's no direct lock call). 3833 * We obviously whave to check for these sentinel cases 3834 * and skip them. 3835 */ 3836 if (__predict_false(*mp == (struct mbuf *)txq)) { 3837 skipped++; 3838 continue; 3839 } 3840 err = iflib_encap(txq, mp); 3841 if (__predict_false(err)) { 3842 /* no room - bail out */ 3843 if (err == ENOBUFS) 3844 break; 3845 skipped++; 3846 /* we can't send this packet - skip it */ 3847 continue; 3848 } 3849 pkt_sent++; 3850 m = *mp; 3851 DBG_COUNTER_INC(tx_sent); 3852 bytes_sent += m->m_pkthdr.len; 3853 mcast_sent += !!(m->m_flags & M_MCAST); 3854 3855 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3856 break; 3857 ETHER_BPF_MTAP(ifp, m); 3858 rang = iflib_txd_db_check(txq, false); 3859 } 3860 3861 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3862 ring = rang ? false : (iflib_min_tx_latency | err); 3863 iflib_txd_db_check(txq, ring); 3864 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3865 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3866 if (mcast_sent) 3867 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3868 #ifdef INVARIANTS 3869 if (iflib_verbose_debug) 3870 printf("consumed=%d\n", skipped + pkt_sent); 3871 #endif 3872 return (skipped + pkt_sent); 3873 } 3874 3875 static uint32_t 3876 iflib_txq_drain_always(struct ifmp_ring *r) 3877 { 3878 return (1); 3879 } 3880 3881 static uint32_t 3882 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3883 { 3884 int i, avail; 3885 struct mbuf **mp; 3886 iflib_txq_t txq; 3887 3888 txq = r->cookie; 3889 3890 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3891 CALLOUT_LOCK(txq); 3892 callout_stop(&txq->ift_timer); 3893 CALLOUT_UNLOCK(txq); 3894 3895 avail = IDXDIFF(pidx, cidx, r->size); 3896 for (i = 0; i < avail; i++) { 3897 mp = _ring_peek_one(r, cidx, i, avail - i); 3898 if (__predict_false(*mp == (struct mbuf *)txq)) 3899 continue; 3900 m_freem(*mp); 3901 DBG_COUNTER_INC(tx_frees); 3902 } 3903 MPASS(ifmp_ring_is_stalled(r) == 0); 3904 return (avail); 3905 } 3906 3907 static void 3908 iflib_ifmp_purge(iflib_txq_t txq) 3909 { 3910 struct ifmp_ring *r; 3911 3912 r = txq->ift_br; 3913 r->drain = iflib_txq_drain_free; 3914 r->can_drain = iflib_txq_drain_always; 3915 3916 ifmp_ring_check_drainage(r, r->size); 3917 3918 r->drain = iflib_txq_drain; 3919 r->can_drain = iflib_txq_can_drain; 3920 } 3921 3922 static void 3923 _task_fn_tx(void *context) 3924 { 3925 iflib_txq_t txq = context; 3926 if_ctx_t ctx = txq->ift_ctx; 3927 if_t ifp = ctx->ifc_ifp; 3928 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3929 3930 #ifdef IFLIB_DIAGNOSTICS 3931 txq->ift_cpu_exec_count[curcpu]++; 3932 #endif 3933 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3934 return; 3935 #ifdef DEV_NETMAP 3936 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3937 netmap_tx_irq(ifp, txq->ift_id)) 3938 goto skip_ifmp; 3939 #endif 3940 #ifdef ALTQ 3941 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3942 iflib_altq_if_start(ifp); 3943 #endif 3944 if (txq->ift_db_pending) 3945 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3946 else if (!abdicate) 3947 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3948 /* 3949 * When abdicating, we always need to check drainage, not just when we don't enqueue 3950 */ 3951 if (abdicate) 3952 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3953 #ifdef DEV_NETMAP 3954 skip_ifmp: 3955 #endif 3956 if (ctx->ifc_flags & IFC_LEGACY) 3957 IFDI_INTR_ENABLE(ctx); 3958 else 3959 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3960 } 3961 3962 static void 3963 _task_fn_rx(void *context) 3964 { 3965 iflib_rxq_t rxq = context; 3966 if_ctx_t ctx = rxq->ifr_ctx; 3967 uint8_t more; 3968 uint16_t budget; 3969 #ifdef DEV_NETMAP 3970 u_int work = 0; 3971 int nmirq; 3972 #endif 3973 3974 #ifdef IFLIB_DIAGNOSTICS 3975 rxq->ifr_cpu_exec_count[curcpu]++; 3976 #endif 3977 DBG_COUNTER_INC(task_fn_rxs); 3978 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3979 return; 3980 #ifdef DEV_NETMAP 3981 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3982 if (nmirq != NM_IRQ_PASS) { 3983 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3984 goto skip_rxeof; 3985 } 3986 #endif 3987 budget = ctx->ifc_sysctl_rx_budget; 3988 if (budget == 0) 3989 budget = 16; /* XXX */ 3990 more = iflib_rxeof(rxq, budget); 3991 #ifdef DEV_NETMAP 3992 skip_rxeof: 3993 #endif 3994 if ((more & IFLIB_RXEOF_MORE) == 0) { 3995 if (ctx->ifc_flags & IFC_LEGACY) 3996 IFDI_INTR_ENABLE(ctx); 3997 else 3998 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3999 DBG_COUNTER_INC(rx_intr_enables); 4000 } 4001 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4002 return; 4003 4004 if (more & IFLIB_RXEOF_MORE) 4005 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4006 else if (more & IFLIB_RXEOF_EMPTY) 4007 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4008 } 4009 4010 static void 4011 _task_fn_admin(void *context) 4012 { 4013 if_ctx_t ctx = context; 4014 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4015 iflib_txq_t txq; 4016 int i; 4017 bool oactive, running, do_reset, do_watchdog, in_detach; 4018 4019 STATE_LOCK(ctx); 4020 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4021 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4022 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4023 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4024 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4025 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4026 STATE_UNLOCK(ctx); 4027 4028 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4029 return; 4030 if (in_detach) 4031 return; 4032 4033 CTX_LOCK(ctx); 4034 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4035 CALLOUT_LOCK(txq); 4036 callout_stop(&txq->ift_timer); 4037 CALLOUT_UNLOCK(txq); 4038 } 4039 if (do_watchdog) { 4040 ctx->ifc_watchdog_events++; 4041 IFDI_WATCHDOG_RESET(ctx); 4042 } 4043 IFDI_UPDATE_ADMIN_STATUS(ctx); 4044 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4045 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4046 txq->ift_timer.c_cpu); 4047 } 4048 IFDI_LINK_INTR_ENABLE(ctx); 4049 if (do_reset) 4050 iflib_if_init_locked(ctx); 4051 CTX_UNLOCK(ctx); 4052 4053 if (LINK_ACTIVE(ctx) == 0) 4054 return; 4055 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4056 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4057 } 4058 4059 static void 4060 _task_fn_iov(void *context) 4061 { 4062 if_ctx_t ctx = context; 4063 4064 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4065 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4066 return; 4067 4068 CTX_LOCK(ctx); 4069 IFDI_VFLR_HANDLE(ctx); 4070 CTX_UNLOCK(ctx); 4071 } 4072 4073 static int 4074 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4075 { 4076 int err; 4077 if_int_delay_info_t info; 4078 if_ctx_t ctx; 4079 4080 info = (if_int_delay_info_t)arg1; 4081 ctx = info->iidi_ctx; 4082 info->iidi_req = req; 4083 info->iidi_oidp = oidp; 4084 CTX_LOCK(ctx); 4085 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4086 CTX_UNLOCK(ctx); 4087 return (err); 4088 } 4089 4090 /********************************************************************* 4091 * 4092 * IFNET FUNCTIONS 4093 * 4094 **********************************************************************/ 4095 4096 static void 4097 iflib_if_init_locked(if_ctx_t ctx) 4098 { 4099 iflib_stop(ctx); 4100 iflib_init_locked(ctx); 4101 } 4102 4103 static void 4104 iflib_if_init(void *arg) 4105 { 4106 if_ctx_t ctx = arg; 4107 4108 CTX_LOCK(ctx); 4109 iflib_if_init_locked(ctx); 4110 CTX_UNLOCK(ctx); 4111 } 4112 4113 static int 4114 iflib_if_transmit(if_t ifp, struct mbuf *m) 4115 { 4116 if_ctx_t ctx = if_getsoftc(ifp); 4117 4118 iflib_txq_t txq; 4119 int err, qidx; 4120 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4121 4122 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4123 DBG_COUNTER_INC(tx_frees); 4124 m_freem(m); 4125 return (ENETDOWN); 4126 } 4127 4128 MPASS(m->m_nextpkt == NULL); 4129 /* ALTQ-enabled interfaces always use queue 0. */ 4130 qidx = 0; 4131 /* Use driver-supplied queue selection method if it exists */ 4132 if (ctx->isc_txq_select) 4133 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4134 /* If not, use iflib's standard method */ 4135 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4136 qidx = QIDX(ctx, m); 4137 4138 /* Set TX queue */ 4139 txq = &ctx->ifc_txqs[qidx]; 4140 4141 #ifdef DRIVER_BACKPRESSURE 4142 if (txq->ift_closed) { 4143 while (m != NULL) { 4144 next = m->m_nextpkt; 4145 m->m_nextpkt = NULL; 4146 m_freem(m); 4147 DBG_COUNTER_INC(tx_frees); 4148 m = next; 4149 } 4150 return (ENOBUFS); 4151 } 4152 #endif 4153 #ifdef notyet 4154 qidx = count = 0; 4155 mp = marr; 4156 next = m; 4157 do { 4158 count++; 4159 next = next->m_nextpkt; 4160 } while (next != NULL); 4161 4162 if (count > nitems(marr)) 4163 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4164 /* XXX check nextpkt */ 4165 m_freem(m); 4166 /* XXX simplify for now */ 4167 DBG_COUNTER_INC(tx_frees); 4168 return (ENOBUFS); 4169 } 4170 for (next = m, i = 0; next != NULL; i++) { 4171 mp[i] = next; 4172 next = next->m_nextpkt; 4173 mp[i]->m_nextpkt = NULL; 4174 } 4175 #endif 4176 DBG_COUNTER_INC(tx_seen); 4177 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4178 4179 if (abdicate) 4180 GROUPTASK_ENQUEUE(&txq->ift_task); 4181 if (err) { 4182 if (!abdicate) 4183 GROUPTASK_ENQUEUE(&txq->ift_task); 4184 /* support forthcoming later */ 4185 #ifdef DRIVER_BACKPRESSURE 4186 txq->ift_closed = TRUE; 4187 #endif 4188 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4189 m_freem(m); 4190 DBG_COUNTER_INC(tx_frees); 4191 } 4192 4193 return (err); 4194 } 4195 4196 #ifdef ALTQ 4197 /* 4198 * The overall approach to integrating iflib with ALTQ is to continue to use 4199 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4200 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4201 * is redundant/unnecessary, but doing so minimizes the amount of 4202 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4203 * redundantly queueing to an intermediate mp_ring is swamped by the 4204 * performance limitations inherent in using ALTQ. 4205 * 4206 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4207 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4208 * given interface. If ALTQ is enabled for an interface, then all 4209 * transmitted packets for that interface will be submitted to the ALTQ 4210 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4211 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4212 * update stats that the iflib machinery handles, and which is sensitve to 4213 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4214 * will be installed as the start routine for use by ALTQ facilities that 4215 * need to trigger queue drains on a scheduled basis. 4216 * 4217 */ 4218 static void 4219 iflib_altq_if_start(if_t ifp) 4220 { 4221 struct ifaltq *ifq = &ifp->if_snd; 4222 struct mbuf *m; 4223 4224 IFQ_LOCK(ifq); 4225 IFQ_DEQUEUE_NOLOCK(ifq, m); 4226 while (m != NULL) { 4227 iflib_if_transmit(ifp, m); 4228 IFQ_DEQUEUE_NOLOCK(ifq, m); 4229 } 4230 IFQ_UNLOCK(ifq); 4231 } 4232 4233 static int 4234 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4235 { 4236 int err; 4237 4238 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4239 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4240 if (err == 0) 4241 iflib_altq_if_start(ifp); 4242 } else 4243 err = iflib_if_transmit(ifp, m); 4244 4245 return (err); 4246 } 4247 #endif /* ALTQ */ 4248 4249 static void 4250 iflib_if_qflush(if_t ifp) 4251 { 4252 if_ctx_t ctx = if_getsoftc(ifp); 4253 iflib_txq_t txq = ctx->ifc_txqs; 4254 int i; 4255 4256 STATE_LOCK(ctx); 4257 ctx->ifc_flags |= IFC_QFLUSH; 4258 STATE_UNLOCK(ctx); 4259 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4260 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4261 iflib_txq_check_drain(txq, 0); 4262 STATE_LOCK(ctx); 4263 ctx->ifc_flags &= ~IFC_QFLUSH; 4264 STATE_UNLOCK(ctx); 4265 4266 /* 4267 * When ALTQ is enabled, this will also take care of purging the 4268 * ALTQ queue(s). 4269 */ 4270 if_qflush(ifp); 4271 } 4272 4273 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4274 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4275 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4276 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4277 4278 static int 4279 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4280 { 4281 if_ctx_t ctx = if_getsoftc(ifp); 4282 struct ifreq *ifr = (struct ifreq *)data; 4283 #if defined(INET) || defined(INET6) 4284 struct ifaddr *ifa = (struct ifaddr *)data; 4285 #endif 4286 bool avoid_reset = false; 4287 int err = 0, reinit = 0, bits; 4288 4289 switch (command) { 4290 case SIOCSIFADDR: 4291 #ifdef INET 4292 if (ifa->ifa_addr->sa_family == AF_INET) 4293 avoid_reset = true; 4294 #endif 4295 #ifdef INET6 4296 if (ifa->ifa_addr->sa_family == AF_INET6) 4297 avoid_reset = true; 4298 #endif 4299 /* 4300 ** Calling init results in link renegotiation, 4301 ** so we avoid doing it when possible. 4302 */ 4303 if (avoid_reset) { 4304 if_setflagbits(ifp, IFF_UP,0); 4305 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4306 reinit = 1; 4307 #ifdef INET 4308 if (!(if_getflags(ifp) & IFF_NOARP)) 4309 arp_ifinit(ifp, ifa); 4310 #endif 4311 } else 4312 err = ether_ioctl(ifp, command, data); 4313 break; 4314 case SIOCSIFMTU: 4315 CTX_LOCK(ctx); 4316 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4317 CTX_UNLOCK(ctx); 4318 break; 4319 } 4320 bits = if_getdrvflags(ifp); 4321 /* stop the driver and free any clusters before proceeding */ 4322 iflib_stop(ctx); 4323 4324 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4325 STATE_LOCK(ctx); 4326 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4327 ctx->ifc_flags |= IFC_MULTISEG; 4328 else 4329 ctx->ifc_flags &= ~IFC_MULTISEG; 4330 STATE_UNLOCK(ctx); 4331 err = if_setmtu(ifp, ifr->ifr_mtu); 4332 } 4333 iflib_init_locked(ctx); 4334 STATE_LOCK(ctx); 4335 if_setdrvflags(ifp, bits); 4336 STATE_UNLOCK(ctx); 4337 CTX_UNLOCK(ctx); 4338 break; 4339 case SIOCSIFFLAGS: 4340 CTX_LOCK(ctx); 4341 if (if_getflags(ifp) & IFF_UP) { 4342 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4343 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4344 (IFF_PROMISC | IFF_ALLMULTI)) { 4345 CTX_UNLOCK(ctx); 4346 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4347 CTX_LOCK(ctx); 4348 } 4349 } else 4350 reinit = 1; 4351 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4352 iflib_stop(ctx); 4353 } 4354 ctx->ifc_if_flags = if_getflags(ifp); 4355 CTX_UNLOCK(ctx); 4356 break; 4357 case SIOCADDMULTI: 4358 case SIOCDELMULTI: 4359 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4360 CTX_LOCK(ctx); 4361 IFDI_INTR_DISABLE(ctx); 4362 IFDI_MULTI_SET(ctx); 4363 IFDI_INTR_ENABLE(ctx); 4364 CTX_UNLOCK(ctx); 4365 } 4366 break; 4367 case SIOCSIFMEDIA: 4368 CTX_LOCK(ctx); 4369 IFDI_MEDIA_SET(ctx); 4370 CTX_UNLOCK(ctx); 4371 /* FALLTHROUGH */ 4372 case SIOCGIFMEDIA: 4373 case SIOCGIFXMEDIA: 4374 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4375 break; 4376 case SIOCGI2C: 4377 { 4378 struct ifi2creq i2c; 4379 4380 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4381 if (err != 0) 4382 break; 4383 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4384 err = EINVAL; 4385 break; 4386 } 4387 if (i2c.len > sizeof(i2c.data)) { 4388 err = EINVAL; 4389 break; 4390 } 4391 4392 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4393 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4394 sizeof(i2c)); 4395 break; 4396 } 4397 case SIOCSIFCAP: 4398 { 4399 int mask, setmask, oldmask; 4400 4401 oldmask = if_getcapenable(ifp); 4402 mask = ifr->ifr_reqcap ^ oldmask; 4403 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4404 setmask = 0; 4405 #ifdef TCP_OFFLOAD 4406 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4407 #endif 4408 setmask |= (mask & IFCAP_FLAGS); 4409 setmask |= (mask & IFCAP_WOL); 4410 4411 /* 4412 * If any RX csum has changed, change all the ones that 4413 * are supported by the driver. 4414 */ 4415 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4416 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4417 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4418 } 4419 4420 /* 4421 * want to ensure that traffic has stopped before we change any of the flags 4422 */ 4423 if (setmask) { 4424 CTX_LOCK(ctx); 4425 bits = if_getdrvflags(ifp); 4426 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4427 iflib_stop(ctx); 4428 STATE_LOCK(ctx); 4429 if_togglecapenable(ifp, setmask); 4430 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4431 STATE_UNLOCK(ctx); 4432 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4433 iflib_init_locked(ctx); 4434 STATE_LOCK(ctx); 4435 if_setdrvflags(ifp, bits); 4436 STATE_UNLOCK(ctx); 4437 CTX_UNLOCK(ctx); 4438 } 4439 if_vlancap(ifp); 4440 break; 4441 } 4442 case SIOCGPRIVATE_0: 4443 case SIOCSDRVSPEC: 4444 case SIOCGDRVSPEC: 4445 CTX_LOCK(ctx); 4446 err = IFDI_PRIV_IOCTL(ctx, command, data); 4447 CTX_UNLOCK(ctx); 4448 break; 4449 default: 4450 err = ether_ioctl(ifp, command, data); 4451 break; 4452 } 4453 if (reinit) 4454 iflib_if_init(ctx); 4455 return (err); 4456 } 4457 4458 static uint64_t 4459 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4460 { 4461 if_ctx_t ctx = if_getsoftc(ifp); 4462 4463 return (IFDI_GET_COUNTER(ctx, cnt)); 4464 } 4465 4466 /********************************************************************* 4467 * 4468 * OTHER FUNCTIONS EXPORTED TO THE STACK 4469 * 4470 **********************************************************************/ 4471 4472 static void 4473 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4474 { 4475 if_ctx_t ctx = if_getsoftc(ifp); 4476 4477 if ((void *)ctx != arg) 4478 return; 4479 4480 if ((vtag == 0) || (vtag > 4095)) 4481 return; 4482 4483 if (iflib_in_detach(ctx)) 4484 return; 4485 4486 CTX_LOCK(ctx); 4487 /* Driver may need all untagged packets to be flushed */ 4488 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4489 iflib_stop(ctx); 4490 IFDI_VLAN_REGISTER(ctx, vtag); 4491 /* Re-init to load the changes, if required */ 4492 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4493 iflib_init_locked(ctx); 4494 CTX_UNLOCK(ctx); 4495 } 4496 4497 static void 4498 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4499 { 4500 if_ctx_t ctx = if_getsoftc(ifp); 4501 4502 if ((void *)ctx != arg) 4503 return; 4504 4505 if ((vtag == 0) || (vtag > 4095)) 4506 return; 4507 4508 CTX_LOCK(ctx); 4509 /* Driver may need all tagged packets to be flushed */ 4510 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4511 iflib_stop(ctx); 4512 IFDI_VLAN_UNREGISTER(ctx, vtag); 4513 /* Re-init to load the changes, if required */ 4514 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4515 iflib_init_locked(ctx); 4516 CTX_UNLOCK(ctx); 4517 } 4518 4519 static void 4520 iflib_led_func(void *arg, int onoff) 4521 { 4522 if_ctx_t ctx = arg; 4523 4524 CTX_LOCK(ctx); 4525 IFDI_LED_FUNC(ctx, onoff); 4526 CTX_UNLOCK(ctx); 4527 } 4528 4529 /********************************************************************* 4530 * 4531 * BUS FUNCTION DEFINITIONS 4532 * 4533 **********************************************************************/ 4534 4535 int 4536 iflib_device_probe(device_t dev) 4537 { 4538 const pci_vendor_info_t *ent; 4539 if_shared_ctx_t sctx; 4540 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4541 uint16_t pci_vendor_id; 4542 4543 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4544 return (ENOTSUP); 4545 4546 pci_vendor_id = pci_get_vendor(dev); 4547 pci_device_id = pci_get_device(dev); 4548 pci_subvendor_id = pci_get_subvendor(dev); 4549 pci_subdevice_id = pci_get_subdevice(dev); 4550 pci_rev_id = pci_get_revid(dev); 4551 if (sctx->isc_parse_devinfo != NULL) 4552 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4553 4554 ent = sctx->isc_vendor_info; 4555 while (ent->pvi_vendor_id != 0) { 4556 if (pci_vendor_id != ent->pvi_vendor_id) { 4557 ent++; 4558 continue; 4559 } 4560 if ((pci_device_id == ent->pvi_device_id) && 4561 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4562 (ent->pvi_subvendor_id == 0)) && 4563 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4564 (ent->pvi_subdevice_id == 0)) && 4565 ((pci_rev_id == ent->pvi_rev_id) || 4566 (ent->pvi_rev_id == 0))) { 4567 device_set_desc_copy(dev, ent->pvi_name); 4568 /* this needs to be changed to zero if the bus probing code 4569 * ever stops re-probing on best match because the sctx 4570 * may have its values over written by register calls 4571 * in subsequent probes 4572 */ 4573 return (BUS_PROBE_DEFAULT); 4574 } 4575 ent++; 4576 } 4577 return (ENXIO); 4578 } 4579 4580 int 4581 iflib_device_probe_vendor(device_t dev) 4582 { 4583 int probe; 4584 4585 probe = iflib_device_probe(dev); 4586 if (probe == BUS_PROBE_DEFAULT) 4587 return (BUS_PROBE_VENDOR); 4588 else 4589 return (probe); 4590 } 4591 4592 static void 4593 iflib_reset_qvalues(if_ctx_t ctx) 4594 { 4595 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4596 if_shared_ctx_t sctx = ctx->ifc_sctx; 4597 device_t dev = ctx->ifc_dev; 4598 int i; 4599 4600 if (ctx->ifc_sysctl_ntxqs != 0) 4601 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4602 if (ctx->ifc_sysctl_nrxqs != 0) 4603 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4604 4605 for (i = 0; i < sctx->isc_ntxqs; i++) { 4606 if (ctx->ifc_sysctl_ntxds[i] != 0) 4607 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4608 else 4609 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4610 } 4611 4612 for (i = 0; i < sctx->isc_nrxqs; i++) { 4613 if (ctx->ifc_sysctl_nrxds[i] != 0) 4614 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4615 else 4616 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4617 } 4618 4619 for (i = 0; i < sctx->isc_nrxqs; i++) { 4620 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4621 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4622 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4623 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4624 } 4625 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4626 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4627 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4628 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4629 } 4630 if (!powerof2(scctx->isc_nrxd[i])) { 4631 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4632 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4633 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4634 } 4635 } 4636 4637 for (i = 0; i < sctx->isc_ntxqs; i++) { 4638 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4639 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4640 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4641 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4642 } 4643 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4644 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4645 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4646 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4647 } 4648 if (!powerof2(scctx->isc_ntxd[i])) { 4649 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4650 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4651 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4652 } 4653 } 4654 } 4655 4656 static void 4657 iflib_add_pfil(if_ctx_t ctx) 4658 { 4659 struct pfil_head *pfil; 4660 struct pfil_head_args pa; 4661 iflib_rxq_t rxq; 4662 int i; 4663 4664 pa.pa_version = PFIL_VERSION; 4665 pa.pa_flags = PFIL_IN; 4666 pa.pa_type = PFIL_TYPE_ETHERNET; 4667 pa.pa_headname = ctx->ifc_ifp->if_xname; 4668 pfil = pfil_head_register(&pa); 4669 4670 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4671 rxq->pfil = pfil; 4672 } 4673 } 4674 4675 static void 4676 iflib_rem_pfil(if_ctx_t ctx) 4677 { 4678 struct pfil_head *pfil; 4679 iflib_rxq_t rxq; 4680 int i; 4681 4682 rxq = ctx->ifc_rxqs; 4683 pfil = rxq->pfil; 4684 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4685 rxq->pfil = NULL; 4686 } 4687 pfil_head_unregister(pfil); 4688 } 4689 4690 4691 /* 4692 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4693 * cpuid and wrapping as necessary. 4694 */ 4695 static unsigned int 4696 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4697 { 4698 unsigned int first_valid; 4699 unsigned int last_valid; 4700 4701 /* cpuid should always be in the valid set */ 4702 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4703 4704 /* valid set should never be empty */ 4705 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4706 4707 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4708 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4709 n = n % CPU_COUNT(&ctx->ifc_cpus); 4710 while (n > 0) { 4711 do { 4712 cpuid++; 4713 if (cpuid > last_valid) 4714 cpuid = first_valid; 4715 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4716 n--; 4717 } 4718 4719 return (cpuid); 4720 } 4721 4722 #if defined(SMP) && defined(SCHED_ULE) 4723 extern struct cpu_group *cpu_top; /* CPU topology */ 4724 4725 static int 4726 find_child_with_core(int cpu, struct cpu_group *grp) 4727 { 4728 int i; 4729 4730 if (grp->cg_children == 0) 4731 return -1; 4732 4733 MPASS(grp->cg_child); 4734 for (i = 0; i < grp->cg_children; i++) { 4735 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4736 return i; 4737 } 4738 4739 return -1; 4740 } 4741 4742 4743 /* 4744 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4745 * does not distinguish among multiple L2 neighbors if the given CPU has 4746 * more than one (it will always return the same result in that case). 4747 */ 4748 static int 4749 find_l2_neighbor(int cpu) 4750 { 4751 struct cpu_group *grp; 4752 int i; 4753 4754 grp = cpu_top; 4755 if (grp == NULL) 4756 return -1; 4757 4758 /* 4759 * Find the smallest CPU group that contains the given core. 4760 */ 4761 i = 0; 4762 while ((i = find_child_with_core(cpu, grp)) != -1) { 4763 /* 4764 * If the smallest group containing the given CPU has less 4765 * than two members, we conclude the given CPU has no 4766 * L2 neighbor. 4767 */ 4768 if (grp->cg_child[i].cg_count <= 1) 4769 return (-1); 4770 grp = &grp->cg_child[i]; 4771 } 4772 4773 /* Must share L2. */ 4774 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4775 return -1; 4776 4777 /* 4778 * Select the first member of the set that isn't the reference 4779 * CPU, which at this point is guaranteed to exist. 4780 */ 4781 for (i = 0; i < CPU_SETSIZE; i++) { 4782 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4783 return (i); 4784 } 4785 4786 /* Should never be reached */ 4787 return (-1); 4788 } 4789 4790 #else 4791 static int 4792 find_l2_neighbor(int cpu) 4793 { 4794 4795 return (-1); 4796 } 4797 #endif 4798 4799 /* 4800 * CPU mapping behaviors 4801 * --------------------- 4802 * 'separate txrx' refers to the separate_txrx sysctl 4803 * 'use logical' refers to the use_logical_cores sysctl 4804 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4805 * 4806 * separate use INTR 4807 * txrx logical CPUS result 4808 * ---------- --------- ------ ------------------------------------------------ 4809 * - - X RX and TX queues mapped to consecutive physical 4810 * cores with RX/TX pairs on same core and excess 4811 * of either following 4812 * - X X RX and TX queues mapped to consecutive cores 4813 * of any type with RX/TX pairs on same core and 4814 * excess of either following 4815 * X - X RX and TX queues mapped to consecutive physical 4816 * cores; all RX then all TX 4817 * X X X RX queues mapped to consecutive physical cores 4818 * first, then TX queues mapped to L2 neighbor of 4819 * the corresponding RX queue if one exists, 4820 * otherwise to consecutive physical cores 4821 * - n/a - RX and TX queues mapped to consecutive cores of 4822 * any type with RX/TX pairs on same core and excess 4823 * of either following 4824 * X n/a - RX and TX queues mapped to consecutive cores of 4825 * any type; all RX then all TX 4826 */ 4827 static unsigned int 4828 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4829 bool is_tx) 4830 { 4831 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4832 unsigned int core_index; 4833 4834 if (ctx->ifc_sysctl_separate_txrx) { 4835 /* 4836 * When using separate CPUs for TX and RX, the assignment 4837 * will always be of a consecutive CPU out of the set of 4838 * context CPUs, except for the specific case where the 4839 * context CPUs are phsyical cores, the use of logical cores 4840 * has been enabled, the assignment is for TX, the TX qid 4841 * corresponds to an RX qid, and the CPU assigned to the 4842 * corresponding RX queue has an L2 neighbor. 4843 */ 4844 if (ctx->ifc_sysctl_use_logical_cores && 4845 ctx->ifc_cpus_are_physical_cores && 4846 is_tx && qid < scctx->isc_nrxqsets) { 4847 int l2_neighbor; 4848 unsigned int rx_cpuid; 4849 4850 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4851 l2_neighbor = find_l2_neighbor(rx_cpuid); 4852 if (l2_neighbor != -1) { 4853 return (l2_neighbor); 4854 } 4855 /* 4856 * ... else fall through to the normal 4857 * consecutive-after-RX assignment scheme. 4858 * 4859 * Note that we are assuming that all RX queue CPUs 4860 * have an L2 neighbor, or all do not. If a mixed 4861 * scenario is possible, we will have to keep track 4862 * separately of how many queues prior to this one 4863 * were not able to be assigned to an L2 neighbor. 4864 */ 4865 } 4866 if (is_tx) 4867 core_index = scctx->isc_nrxqsets + qid; 4868 else 4869 core_index = qid; 4870 } else { 4871 core_index = qid; 4872 } 4873 4874 return (cpuid_advance(ctx, base_cpuid, core_index)); 4875 } 4876 4877 static uint16_t 4878 get_ctx_core_offset(if_ctx_t ctx) 4879 { 4880 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4881 struct cpu_offset *op; 4882 cpuset_t assigned_cpus; 4883 unsigned int cores_consumed; 4884 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4885 unsigned int first_valid; 4886 unsigned int last_valid; 4887 unsigned int i; 4888 4889 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4890 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4891 4892 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4893 /* 4894 * Align the user-chosen base CPU ID to the next valid CPU 4895 * for this device. If the chosen base CPU ID is smaller 4896 * than the first valid CPU or larger than the last valid 4897 * CPU, we assume the user does not know what the valid 4898 * range is for this device and is thinking in terms of a 4899 * zero-based reference frame, and so we shift the given 4900 * value into the valid range (and wrap accordingly) so the 4901 * intent is translated to the proper frame of reference. 4902 * If the base CPU ID is within the valid first/last, but 4903 * does not correspond to a valid CPU, it is advanced to the 4904 * next valid CPU (wrapping if necessary). 4905 */ 4906 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4907 /* shift from zero-based to first_valid-based */ 4908 base_cpuid += first_valid; 4909 /* wrap to range [first_valid, last_valid] */ 4910 base_cpuid = (base_cpuid - first_valid) % 4911 (last_valid - first_valid + 1); 4912 } 4913 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4914 /* 4915 * base_cpuid is in [first_valid, last_valid], but 4916 * not a member of the valid set. In this case, 4917 * there will always be a member of the valid set 4918 * with a CPU ID that is greater than base_cpuid, 4919 * and we simply advance to it. 4920 */ 4921 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4922 base_cpuid++; 4923 } 4924 return (base_cpuid); 4925 } 4926 4927 /* 4928 * Determine how many cores will be consumed by performing the CPU 4929 * assignments and counting how many of the assigned CPUs correspond 4930 * to CPUs in the set of context CPUs. This is done using the CPU 4931 * ID first_valid as the base CPU ID, as the base CPU must be within 4932 * the set of context CPUs. 4933 * 4934 * Note not all assigned CPUs will be in the set of context CPUs 4935 * when separate CPUs are being allocated to TX and RX queues, 4936 * assignment to logical cores has been enabled, the set of context 4937 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4938 * neighbors of CPUs that RX queues have been mapped to - in this 4939 * case we do only want to count how many CPUs in the set of context 4940 * CPUs have been consumed, as that determines the next CPU in that 4941 * set to start allocating at for the next device for which 4942 * core_offset is not set. 4943 */ 4944 CPU_ZERO(&assigned_cpus); 4945 for (i = 0; i < scctx->isc_ntxqsets; i++) 4946 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4947 &assigned_cpus); 4948 for (i = 0; i < scctx->isc_nrxqsets; i++) 4949 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4950 &assigned_cpus); 4951 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 4952 cores_consumed = CPU_COUNT(&assigned_cpus); 4953 4954 mtx_lock(&cpu_offset_mtx); 4955 SLIST_FOREACH(op, &cpu_offsets, entries) { 4956 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4957 base_cpuid = op->next_cpuid; 4958 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4959 cores_consumed); 4960 MPASS(op->refcount < UINT_MAX); 4961 op->refcount++; 4962 break; 4963 } 4964 } 4965 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4966 base_cpuid = first_valid; 4967 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4968 M_NOWAIT | M_ZERO); 4969 if (op == NULL) { 4970 device_printf(ctx->ifc_dev, 4971 "allocation for cpu offset failed.\n"); 4972 } else { 4973 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 4974 cores_consumed); 4975 op->refcount = 1; 4976 CPU_COPY(&ctx->ifc_cpus, &op->set); 4977 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4978 } 4979 } 4980 mtx_unlock(&cpu_offset_mtx); 4981 4982 return (base_cpuid); 4983 } 4984 4985 static void 4986 unref_ctx_core_offset(if_ctx_t ctx) 4987 { 4988 struct cpu_offset *op, *top; 4989 4990 mtx_lock(&cpu_offset_mtx); 4991 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4992 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4993 MPASS(op->refcount > 0); 4994 op->refcount--; 4995 if (op->refcount == 0) { 4996 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4997 free(op, M_IFLIB); 4998 } 4999 break; 5000 } 5001 } 5002 mtx_unlock(&cpu_offset_mtx); 5003 } 5004 5005 int 5006 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5007 { 5008 if_ctx_t ctx; 5009 if_t ifp; 5010 if_softc_ctx_t scctx; 5011 kobjop_desc_t kobj_desc; 5012 kobj_method_t *kobj_method; 5013 int err, msix, rid; 5014 int num_txd, num_rxd; 5015 5016 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5017 5018 if (sc == NULL) { 5019 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5020 device_set_softc(dev, ctx); 5021 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5022 } 5023 5024 ctx->ifc_sctx = sctx; 5025 ctx->ifc_dev = dev; 5026 ctx->ifc_softc = sc; 5027 5028 if ((err = iflib_register(ctx)) != 0) { 5029 device_printf(dev, "iflib_register failed %d\n", err); 5030 goto fail_ctx_free; 5031 } 5032 iflib_add_device_sysctl_pre(ctx); 5033 5034 scctx = &ctx->ifc_softc_ctx; 5035 ifp = ctx->ifc_ifp; 5036 5037 iflib_reset_qvalues(ctx); 5038 IFNET_WLOCK(); 5039 CTX_LOCK(ctx); 5040 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5041 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5042 goto fail_unlock; 5043 } 5044 _iflib_pre_assert(scctx); 5045 ctx->ifc_txrx = *scctx->isc_txrx; 5046 5047 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5048 ctx->ifc_mediap = scctx->isc_media; 5049 5050 #ifdef INVARIANTS 5051 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5052 MPASS(scctx->isc_tx_csum_flags); 5053 #endif 5054 5055 if_setcapabilities(ifp, 5056 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5057 if_setcapenable(ifp, 5058 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5059 5060 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5061 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5062 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5063 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5064 5065 num_txd = iflib_num_tx_descs(ctx); 5066 num_rxd = iflib_num_rx_descs(ctx); 5067 5068 /* XXX change for per-queue sizes */ 5069 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5070 num_txd, num_rxd); 5071 5072 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5073 scctx->isc_tx_nsegments = max(1, num_txd / 5074 MAX_SINGLE_PACKET_FRACTION); 5075 if (scctx->isc_tx_tso_segments_max > num_txd / 5076 MAX_SINGLE_PACKET_FRACTION) 5077 scctx->isc_tx_tso_segments_max = max(1, 5078 num_txd / MAX_SINGLE_PACKET_FRACTION); 5079 5080 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5081 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5082 /* 5083 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5084 * but some MACs do. 5085 */ 5086 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5087 IP_MAXPACKET)); 5088 /* 5089 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5090 * into account. In the worst case, each of these calls will 5091 * add another mbuf and, thus, the requirement for another DMA 5092 * segment. So for best performance, it doesn't make sense to 5093 * advertize a maximum of TSO segments that typically will 5094 * require defragmentation in iflib_encap(). 5095 */ 5096 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5097 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5098 } 5099 if (scctx->isc_rss_table_size == 0) 5100 scctx->isc_rss_table_size = 64; 5101 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5102 5103 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5104 /* XXX format name */ 5105 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5106 NULL, NULL, "admin"); 5107 5108 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5109 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5110 device_printf(dev, "Unable to fetch CPU list\n"); 5111 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5112 ctx->ifc_cpus_are_physical_cores = false; 5113 } else 5114 ctx->ifc_cpus_are_physical_cores = true; 5115 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5116 5117 /* 5118 ** Now set up MSI or MSI-X, should return us the number of supported 5119 ** vectors (will be 1 for a legacy interrupt and MSI). 5120 */ 5121 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5122 msix = scctx->isc_vectors; 5123 } else if (scctx->isc_msix_bar != 0) 5124 /* 5125 * The simple fact that isc_msix_bar is not 0 does not mean we 5126 * we have a good value there that is known to work. 5127 */ 5128 msix = iflib_msix_init(ctx); 5129 else { 5130 scctx->isc_vectors = 1; 5131 scctx->isc_ntxqsets = 1; 5132 scctx->isc_nrxqsets = 1; 5133 scctx->isc_intr = IFLIB_INTR_LEGACY; 5134 msix = 0; 5135 } 5136 /* Get memory for the station queues */ 5137 if ((err = iflib_queues_alloc(ctx))) { 5138 device_printf(dev, "Unable to allocate queue memory\n"); 5139 goto fail_intr_free; 5140 } 5141 5142 if ((err = iflib_qset_structures_setup(ctx))) 5143 goto fail_queues; 5144 5145 /* 5146 * Now that we know how many queues there are, get the core offset. 5147 */ 5148 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5149 5150 if (msix > 1) { 5151 /* 5152 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5153 * aren't the default NULL implementation. 5154 */ 5155 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5156 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5157 kobj_desc); 5158 if (kobj_method == &kobj_desc->deflt) { 5159 device_printf(dev, 5160 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5161 err = EOPNOTSUPP; 5162 goto fail_queues; 5163 } 5164 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5165 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5166 kobj_desc); 5167 if (kobj_method == &kobj_desc->deflt) { 5168 device_printf(dev, 5169 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5170 err = EOPNOTSUPP; 5171 goto fail_queues; 5172 } 5173 5174 /* 5175 * Assign the MSI-X vectors. 5176 * Note that the default NULL ifdi_msix_intr_assign method will 5177 * fail here, too. 5178 */ 5179 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5180 if (err != 0) { 5181 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5182 err); 5183 goto fail_queues; 5184 } 5185 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5186 rid = 0; 5187 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5188 MPASS(msix == 1); 5189 rid = 1; 5190 } 5191 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5192 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5193 goto fail_queues; 5194 } 5195 } else { 5196 device_printf(dev, 5197 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5198 err = ENODEV; 5199 goto fail_queues; 5200 } 5201 5202 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5203 5204 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5205 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5206 goto fail_detach; 5207 } 5208 5209 /* 5210 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5211 * This must appear after the call to ether_ifattach() because 5212 * ether_ifattach() sets if_hdrlen to the default value. 5213 */ 5214 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5215 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5216 5217 if ((err = iflib_netmap_attach(ctx))) { 5218 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5219 goto fail_detach; 5220 } 5221 *ctxp = ctx; 5222 5223 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5224 5225 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5226 iflib_add_device_sysctl_post(ctx); 5227 iflib_add_pfil(ctx); 5228 ctx->ifc_flags |= IFC_INIT_DONE; 5229 CTX_UNLOCK(ctx); 5230 IFNET_WUNLOCK(); 5231 5232 return (0); 5233 5234 fail_detach: 5235 ether_ifdetach(ctx->ifc_ifp); 5236 fail_queues: 5237 iflib_tqg_detach(ctx); 5238 iflib_tx_structures_free(ctx); 5239 iflib_rx_structures_free(ctx); 5240 IFDI_DETACH(ctx); 5241 IFDI_QUEUES_FREE(ctx); 5242 fail_intr_free: 5243 iflib_free_intr_mem(ctx); 5244 fail_unlock: 5245 CTX_UNLOCK(ctx); 5246 IFNET_WUNLOCK(); 5247 iflib_deregister(ctx); 5248 fail_ctx_free: 5249 device_set_softc(ctx->ifc_dev, NULL); 5250 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5251 free(ctx->ifc_softc, M_IFLIB); 5252 free(ctx, M_IFLIB); 5253 return (err); 5254 } 5255 5256 int 5257 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5258 struct iflib_cloneattach_ctx *clctx) 5259 { 5260 int num_txd, num_rxd; 5261 int err; 5262 if_ctx_t ctx; 5263 if_t ifp; 5264 if_softc_ctx_t scctx; 5265 int i; 5266 void *sc; 5267 5268 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5269 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5270 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5271 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5272 ctx->ifc_flags |= IFC_PSEUDO; 5273 5274 ctx->ifc_sctx = sctx; 5275 ctx->ifc_softc = sc; 5276 ctx->ifc_dev = dev; 5277 5278 if ((err = iflib_register(ctx)) != 0) { 5279 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5280 goto fail_ctx_free; 5281 } 5282 iflib_add_device_sysctl_pre(ctx); 5283 5284 scctx = &ctx->ifc_softc_ctx; 5285 ifp = ctx->ifc_ifp; 5286 5287 iflib_reset_qvalues(ctx); 5288 CTX_LOCK(ctx); 5289 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5290 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5291 goto fail_unlock; 5292 } 5293 if (sctx->isc_flags & IFLIB_GEN_MAC) 5294 ether_gen_addr(ifp, &ctx->ifc_mac); 5295 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5296 clctx->cc_params)) != 0) { 5297 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5298 goto fail_unlock; 5299 } 5300 #ifdef INVARIANTS 5301 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5302 MPASS(scctx->isc_tx_csum_flags); 5303 #endif 5304 5305 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5306 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5307 5308 ifp->if_flags |= IFF_NOGROUP; 5309 if (sctx->isc_flags & IFLIB_PSEUDO) { 5310 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5311 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5312 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5313 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5314 } else { 5315 if_attach(ctx->ifc_ifp); 5316 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5317 } 5318 5319 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5320 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5321 goto fail_detach; 5322 } 5323 *ctxp = ctx; 5324 5325 /* 5326 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5327 * This must appear after the call to ether_ifattach() because 5328 * ether_ifattach() sets if_hdrlen to the default value. 5329 */ 5330 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5331 if_setifheaderlen(ifp, 5332 sizeof(struct ether_vlan_header)); 5333 5334 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5335 iflib_add_device_sysctl_post(ctx); 5336 ctx->ifc_flags |= IFC_INIT_DONE; 5337 CTX_UNLOCK(ctx); 5338 return (0); 5339 } 5340 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5341 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5342 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5343 5344 _iflib_pre_assert(scctx); 5345 ctx->ifc_txrx = *scctx->isc_txrx; 5346 5347 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5348 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5349 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5350 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5351 5352 num_txd = iflib_num_tx_descs(ctx); 5353 num_rxd = iflib_num_rx_descs(ctx); 5354 5355 /* XXX change for per-queue sizes */ 5356 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5357 num_txd, num_rxd); 5358 5359 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5360 scctx->isc_tx_nsegments = max(1, num_txd / 5361 MAX_SINGLE_PACKET_FRACTION); 5362 if (scctx->isc_tx_tso_segments_max > num_txd / 5363 MAX_SINGLE_PACKET_FRACTION) 5364 scctx->isc_tx_tso_segments_max = max(1, 5365 num_txd / MAX_SINGLE_PACKET_FRACTION); 5366 5367 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5368 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5369 /* 5370 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5371 * but some MACs do. 5372 */ 5373 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5374 IP_MAXPACKET)); 5375 /* 5376 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5377 * into account. In the worst case, each of these calls will 5378 * add another mbuf and, thus, the requirement for another DMA 5379 * segment. So for best performance, it doesn't make sense to 5380 * advertize a maximum of TSO segments that typically will 5381 * require defragmentation in iflib_encap(). 5382 */ 5383 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5384 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5385 } 5386 if (scctx->isc_rss_table_size == 0) 5387 scctx->isc_rss_table_size = 64; 5388 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5389 5390 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5391 /* XXX format name */ 5392 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5393 NULL, NULL, "admin"); 5394 5395 /* XXX --- can support > 1 -- but keep it simple for now */ 5396 scctx->isc_intr = IFLIB_INTR_LEGACY; 5397 5398 /* Get memory for the station queues */ 5399 if ((err = iflib_queues_alloc(ctx))) { 5400 device_printf(dev, "Unable to allocate queue memory\n"); 5401 goto fail_iflib_detach; 5402 } 5403 5404 if ((err = iflib_qset_structures_setup(ctx))) { 5405 device_printf(dev, "qset structure setup failed %d\n", err); 5406 goto fail_queues; 5407 } 5408 5409 /* 5410 * XXX What if anything do we want to do about interrupts? 5411 */ 5412 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5413 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5414 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5415 goto fail_detach; 5416 } 5417 5418 /* 5419 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5420 * This must appear after the call to ether_ifattach() because 5421 * ether_ifattach() sets if_hdrlen to the default value. 5422 */ 5423 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5424 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5425 5426 /* XXX handle more than one queue */ 5427 for (i = 0; i < scctx->isc_nrxqsets; i++) 5428 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5429 5430 *ctxp = ctx; 5431 5432 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5433 iflib_add_device_sysctl_post(ctx); 5434 ctx->ifc_flags |= IFC_INIT_DONE; 5435 CTX_UNLOCK(ctx); 5436 5437 return (0); 5438 fail_detach: 5439 ether_ifdetach(ctx->ifc_ifp); 5440 fail_queues: 5441 iflib_tqg_detach(ctx); 5442 iflib_tx_structures_free(ctx); 5443 iflib_rx_structures_free(ctx); 5444 fail_iflib_detach: 5445 IFDI_DETACH(ctx); 5446 IFDI_QUEUES_FREE(ctx); 5447 fail_unlock: 5448 CTX_UNLOCK(ctx); 5449 iflib_deregister(ctx); 5450 fail_ctx_free: 5451 free(ctx->ifc_softc, M_IFLIB); 5452 free(ctx, M_IFLIB); 5453 return (err); 5454 } 5455 5456 int 5457 iflib_pseudo_deregister(if_ctx_t ctx) 5458 { 5459 if_t ifp = ctx->ifc_ifp; 5460 if_shared_ctx_t sctx = ctx->ifc_sctx; 5461 5462 /* Unregister VLAN event handlers early */ 5463 iflib_unregister_vlan_handlers(ctx); 5464 5465 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5466 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5467 bpfdetach(ifp); 5468 if_detach(ifp); 5469 } else { 5470 ether_ifdetach(ifp); 5471 } 5472 5473 iflib_tqg_detach(ctx); 5474 iflib_tx_structures_free(ctx); 5475 iflib_rx_structures_free(ctx); 5476 IFDI_DETACH(ctx); 5477 IFDI_QUEUES_FREE(ctx); 5478 5479 iflib_deregister(ctx); 5480 5481 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5482 free(ctx->ifc_softc, M_IFLIB); 5483 free(ctx, M_IFLIB); 5484 return (0); 5485 } 5486 5487 int 5488 iflib_device_attach(device_t dev) 5489 { 5490 if_ctx_t ctx; 5491 if_shared_ctx_t sctx; 5492 5493 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5494 return (ENOTSUP); 5495 5496 pci_enable_busmaster(dev); 5497 5498 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5499 } 5500 5501 int 5502 iflib_device_deregister(if_ctx_t ctx) 5503 { 5504 if_t ifp = ctx->ifc_ifp; 5505 device_t dev = ctx->ifc_dev; 5506 5507 /* Make sure VLANS are not using driver */ 5508 if (if_vlantrunkinuse(ifp)) { 5509 device_printf(dev, "Vlan in use, detach first\n"); 5510 return (EBUSY); 5511 } 5512 #ifdef PCI_IOV 5513 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5514 device_printf(dev, "SR-IOV in use; detach first.\n"); 5515 return (EBUSY); 5516 } 5517 #endif 5518 5519 STATE_LOCK(ctx); 5520 ctx->ifc_flags |= IFC_IN_DETACH; 5521 STATE_UNLOCK(ctx); 5522 5523 /* Unregister VLAN handlers before calling iflib_stop() */ 5524 iflib_unregister_vlan_handlers(ctx); 5525 5526 iflib_netmap_detach(ifp); 5527 ether_ifdetach(ifp); 5528 5529 CTX_LOCK(ctx); 5530 iflib_stop(ctx); 5531 CTX_UNLOCK(ctx); 5532 5533 iflib_rem_pfil(ctx); 5534 if (ctx->ifc_led_dev != NULL) 5535 led_destroy(ctx->ifc_led_dev); 5536 5537 iflib_tqg_detach(ctx); 5538 iflib_tx_structures_free(ctx); 5539 iflib_rx_structures_free(ctx); 5540 5541 CTX_LOCK(ctx); 5542 IFDI_DETACH(ctx); 5543 IFDI_QUEUES_FREE(ctx); 5544 CTX_UNLOCK(ctx); 5545 5546 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5547 iflib_free_intr_mem(ctx); 5548 5549 bus_generic_detach(dev); 5550 5551 iflib_deregister(ctx); 5552 5553 device_set_softc(ctx->ifc_dev, NULL); 5554 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5555 free(ctx->ifc_softc, M_IFLIB); 5556 unref_ctx_core_offset(ctx); 5557 free(ctx, M_IFLIB); 5558 return (0); 5559 } 5560 5561 static void 5562 iflib_tqg_detach(if_ctx_t ctx) 5563 { 5564 iflib_txq_t txq; 5565 iflib_rxq_t rxq; 5566 int i; 5567 struct taskqgroup *tqg; 5568 5569 /* XXX drain any dependent tasks */ 5570 tqg = qgroup_if_io_tqg; 5571 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5572 callout_drain(&txq->ift_timer); 5573 #ifdef DEV_NETMAP 5574 callout_drain(&txq->ift_netmap_timer); 5575 #endif /* DEV_NETMAP */ 5576 if (txq->ift_task.gt_uniq != NULL) 5577 taskqgroup_detach(tqg, &txq->ift_task); 5578 } 5579 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5580 if (rxq->ifr_task.gt_uniq != NULL) 5581 taskqgroup_detach(tqg, &rxq->ifr_task); 5582 } 5583 tqg = qgroup_if_config_tqg; 5584 if (ctx->ifc_admin_task.gt_uniq != NULL) 5585 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5586 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5587 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5588 } 5589 5590 static void 5591 iflib_free_intr_mem(if_ctx_t ctx) 5592 { 5593 5594 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5595 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5596 } 5597 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5598 pci_release_msi(ctx->ifc_dev); 5599 } 5600 if (ctx->ifc_msix_mem != NULL) { 5601 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5602 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5603 ctx->ifc_msix_mem = NULL; 5604 } 5605 } 5606 5607 int 5608 iflib_device_detach(device_t dev) 5609 { 5610 if_ctx_t ctx = device_get_softc(dev); 5611 5612 return (iflib_device_deregister(ctx)); 5613 } 5614 5615 int 5616 iflib_device_suspend(device_t dev) 5617 { 5618 if_ctx_t ctx = device_get_softc(dev); 5619 5620 CTX_LOCK(ctx); 5621 IFDI_SUSPEND(ctx); 5622 CTX_UNLOCK(ctx); 5623 5624 return bus_generic_suspend(dev); 5625 } 5626 int 5627 iflib_device_shutdown(device_t dev) 5628 { 5629 if_ctx_t ctx = device_get_softc(dev); 5630 5631 CTX_LOCK(ctx); 5632 IFDI_SHUTDOWN(ctx); 5633 CTX_UNLOCK(ctx); 5634 5635 return bus_generic_suspend(dev); 5636 } 5637 5638 int 5639 iflib_device_resume(device_t dev) 5640 { 5641 if_ctx_t ctx = device_get_softc(dev); 5642 iflib_txq_t txq = ctx->ifc_txqs; 5643 5644 CTX_LOCK(ctx); 5645 IFDI_RESUME(ctx); 5646 iflib_if_init_locked(ctx); 5647 CTX_UNLOCK(ctx); 5648 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5649 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5650 5651 return (bus_generic_resume(dev)); 5652 } 5653 5654 int 5655 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5656 { 5657 int error; 5658 if_ctx_t ctx = device_get_softc(dev); 5659 5660 CTX_LOCK(ctx); 5661 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5662 CTX_UNLOCK(ctx); 5663 5664 return (error); 5665 } 5666 5667 void 5668 iflib_device_iov_uninit(device_t dev) 5669 { 5670 if_ctx_t ctx = device_get_softc(dev); 5671 5672 CTX_LOCK(ctx); 5673 IFDI_IOV_UNINIT(ctx); 5674 CTX_UNLOCK(ctx); 5675 } 5676 5677 int 5678 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5679 { 5680 int error; 5681 if_ctx_t ctx = device_get_softc(dev); 5682 5683 CTX_LOCK(ctx); 5684 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5685 CTX_UNLOCK(ctx); 5686 5687 return (error); 5688 } 5689 5690 /********************************************************************* 5691 * 5692 * MODULE FUNCTION DEFINITIONS 5693 * 5694 **********************************************************************/ 5695 5696 /* 5697 * - Start a fast taskqueue thread for each core 5698 * - Start a taskqueue for control operations 5699 */ 5700 static int 5701 iflib_module_init(void) 5702 { 5703 iflib_timer_default = hz / 2; 5704 return (0); 5705 } 5706 5707 static int 5708 iflib_module_event_handler(module_t mod, int what, void *arg) 5709 { 5710 int err; 5711 5712 switch (what) { 5713 case MOD_LOAD: 5714 if ((err = iflib_module_init()) != 0) 5715 return (err); 5716 break; 5717 case MOD_UNLOAD: 5718 return (EBUSY); 5719 default: 5720 return (EOPNOTSUPP); 5721 } 5722 5723 return (0); 5724 } 5725 5726 /********************************************************************* 5727 * 5728 * PUBLIC FUNCTION DEFINITIONS 5729 * ordered as in iflib.h 5730 * 5731 **********************************************************************/ 5732 5733 static void 5734 _iflib_assert(if_shared_ctx_t sctx) 5735 { 5736 int i; 5737 5738 MPASS(sctx->isc_tx_maxsize); 5739 MPASS(sctx->isc_tx_maxsegsize); 5740 5741 MPASS(sctx->isc_rx_maxsize); 5742 MPASS(sctx->isc_rx_nsegments); 5743 MPASS(sctx->isc_rx_maxsegsize); 5744 5745 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5746 for (i = 0; i < sctx->isc_nrxqs; i++) { 5747 MPASS(sctx->isc_nrxd_min[i]); 5748 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5749 MPASS(sctx->isc_nrxd_max[i]); 5750 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5751 MPASS(sctx->isc_nrxd_default[i]); 5752 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5753 } 5754 5755 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5756 for (i = 0; i < sctx->isc_ntxqs; i++) { 5757 MPASS(sctx->isc_ntxd_min[i]); 5758 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5759 MPASS(sctx->isc_ntxd_max[i]); 5760 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5761 MPASS(sctx->isc_ntxd_default[i]); 5762 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5763 } 5764 } 5765 5766 static void 5767 _iflib_pre_assert(if_softc_ctx_t scctx) 5768 { 5769 5770 MPASS(scctx->isc_txrx->ift_txd_encap); 5771 MPASS(scctx->isc_txrx->ift_txd_flush); 5772 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5773 MPASS(scctx->isc_txrx->ift_rxd_available); 5774 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5775 MPASS(scctx->isc_txrx->ift_rxd_refill); 5776 MPASS(scctx->isc_txrx->ift_rxd_flush); 5777 } 5778 5779 static int 5780 iflib_register(if_ctx_t ctx) 5781 { 5782 if_shared_ctx_t sctx = ctx->ifc_sctx; 5783 driver_t *driver = sctx->isc_driver; 5784 device_t dev = ctx->ifc_dev; 5785 if_t ifp; 5786 u_char type; 5787 int iflags; 5788 5789 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5790 _iflib_assert(sctx); 5791 5792 CTX_LOCK_INIT(ctx); 5793 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5794 if (sctx->isc_flags & IFLIB_PSEUDO) { 5795 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5796 type = IFT_ETHER; 5797 else 5798 type = IFT_PPP; 5799 } else 5800 type = IFT_ETHER; 5801 ifp = ctx->ifc_ifp = if_alloc(type); 5802 if (ifp == NULL) { 5803 device_printf(dev, "can not allocate ifnet structure\n"); 5804 return (ENOMEM); 5805 } 5806 5807 /* 5808 * Initialize our context's device specific methods 5809 */ 5810 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5811 kobj_class_compile((kobj_class_t) driver); 5812 5813 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5814 if_setsoftc(ifp, ctx); 5815 if_setdev(ifp, dev); 5816 if_setinitfn(ifp, iflib_if_init); 5817 if_setioctlfn(ifp, iflib_if_ioctl); 5818 #ifdef ALTQ 5819 if_setstartfn(ifp, iflib_altq_if_start); 5820 if_settransmitfn(ifp, iflib_altq_if_transmit); 5821 if_setsendqready(ifp); 5822 #else 5823 if_settransmitfn(ifp, iflib_if_transmit); 5824 #endif 5825 if_setqflushfn(ifp, iflib_if_qflush); 5826 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5827 5828 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5829 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5830 iflags |= IFF_POINTOPOINT; 5831 else 5832 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5833 if_setflags(ifp, iflags); 5834 ctx->ifc_vlan_attach_event = 5835 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5836 EVENTHANDLER_PRI_FIRST); 5837 ctx->ifc_vlan_detach_event = 5838 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5839 EVENTHANDLER_PRI_FIRST); 5840 5841 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5842 ctx->ifc_mediap = &ctx->ifc_media; 5843 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5844 iflib_media_change, iflib_media_status); 5845 } 5846 return (0); 5847 } 5848 5849 static void 5850 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5851 { 5852 /* Unregister VLAN events */ 5853 if (ctx->ifc_vlan_attach_event != NULL) { 5854 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5855 ctx->ifc_vlan_attach_event = NULL; 5856 } 5857 if (ctx->ifc_vlan_detach_event != NULL) { 5858 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5859 ctx->ifc_vlan_detach_event = NULL; 5860 } 5861 5862 } 5863 5864 static void 5865 iflib_deregister(if_ctx_t ctx) 5866 { 5867 if_t ifp = ctx->ifc_ifp; 5868 5869 /* Remove all media */ 5870 ifmedia_removeall(&ctx->ifc_media); 5871 5872 /* Ensure that VLAN event handlers are unregistered */ 5873 iflib_unregister_vlan_handlers(ctx); 5874 5875 /* Release kobject reference */ 5876 kobj_delete((kobj_t) ctx, NULL); 5877 5878 /* Free the ifnet structure */ 5879 if_free(ifp); 5880 5881 STATE_LOCK_DESTROY(ctx); 5882 5883 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5884 CTX_LOCK_DESTROY(ctx); 5885 } 5886 5887 static int 5888 iflib_queues_alloc(if_ctx_t ctx) 5889 { 5890 if_shared_ctx_t sctx = ctx->ifc_sctx; 5891 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5892 device_t dev = ctx->ifc_dev; 5893 int nrxqsets = scctx->isc_nrxqsets; 5894 int ntxqsets = scctx->isc_ntxqsets; 5895 iflib_txq_t txq; 5896 iflib_rxq_t rxq; 5897 iflib_fl_t fl = NULL; 5898 int i, j, cpu, err, txconf, rxconf; 5899 iflib_dma_info_t ifdip; 5900 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5901 uint32_t *txqsizes = scctx->isc_txqsizes; 5902 uint8_t nrxqs = sctx->isc_nrxqs; 5903 uint8_t ntxqs = sctx->isc_ntxqs; 5904 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5905 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5906 caddr_t *vaddrs; 5907 uint64_t *paddrs; 5908 5909 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5910 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5911 KASSERT(nrxqs >= fl_offset + nfree_lists, 5912 ("there must be at least a rxq for each free list")); 5913 5914 /* Allocate the TX ring struct memory */ 5915 if (!(ctx->ifc_txqs = 5916 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5917 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5918 device_printf(dev, "Unable to allocate TX ring memory\n"); 5919 err = ENOMEM; 5920 goto fail; 5921 } 5922 5923 /* Now allocate the RX */ 5924 if (!(ctx->ifc_rxqs = 5925 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5926 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5927 device_printf(dev, "Unable to allocate RX ring memory\n"); 5928 err = ENOMEM; 5929 goto rx_fail; 5930 } 5931 5932 txq = ctx->ifc_txqs; 5933 rxq = ctx->ifc_rxqs; 5934 5935 /* 5936 * XXX handle allocation failure 5937 */ 5938 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5939 /* Set up some basics */ 5940 5941 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5942 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5943 device_printf(dev, 5944 "Unable to allocate TX DMA info memory\n"); 5945 err = ENOMEM; 5946 goto err_tx_desc; 5947 } 5948 txq->ift_ifdi = ifdip; 5949 for (j = 0; j < ntxqs; j++, ifdip++) { 5950 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5951 device_printf(dev, 5952 "Unable to allocate TX descriptors\n"); 5953 err = ENOMEM; 5954 goto err_tx_desc; 5955 } 5956 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5957 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5958 } 5959 txq->ift_ctx = ctx; 5960 txq->ift_id = i; 5961 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5962 txq->ift_br_offset = 1; 5963 } else { 5964 txq->ift_br_offset = 0; 5965 } 5966 5967 if (iflib_txsd_alloc(txq)) { 5968 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5969 err = ENOMEM; 5970 goto err_tx_desc; 5971 } 5972 5973 /* Initialize the TX lock */ 5974 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5975 device_get_nameunit(dev), txq->ift_id); 5976 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5977 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5978 txq->ift_timer.c_cpu = cpu; 5979 #ifdef DEV_NETMAP 5980 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5981 txq->ift_netmap_timer.c_cpu = cpu; 5982 #endif /* DEV_NETMAP */ 5983 5984 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5985 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5986 if (err) { 5987 /* XXX free any allocated rings */ 5988 device_printf(dev, "Unable to allocate buf_ring\n"); 5989 goto err_tx_desc; 5990 } 5991 } 5992 5993 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5994 /* Set up some basics */ 5995 callout_init(&rxq->ifr_watchdog, 1); 5996 5997 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5998 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5999 device_printf(dev, 6000 "Unable to allocate RX DMA info memory\n"); 6001 err = ENOMEM; 6002 goto err_tx_desc; 6003 } 6004 6005 rxq->ifr_ifdi = ifdip; 6006 /* XXX this needs to be changed if #rx queues != #tx queues */ 6007 rxq->ifr_ntxqirq = 1; 6008 rxq->ifr_txqid[0] = i; 6009 for (j = 0; j < nrxqs; j++, ifdip++) { 6010 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6011 device_printf(dev, 6012 "Unable to allocate RX descriptors\n"); 6013 err = ENOMEM; 6014 goto err_tx_desc; 6015 } 6016 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6017 } 6018 rxq->ifr_ctx = ctx; 6019 rxq->ifr_id = i; 6020 rxq->ifr_fl_offset = fl_offset; 6021 rxq->ifr_nfl = nfree_lists; 6022 if (!(fl = 6023 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6024 device_printf(dev, "Unable to allocate free list memory\n"); 6025 err = ENOMEM; 6026 goto err_tx_desc; 6027 } 6028 rxq->ifr_fl = fl; 6029 for (j = 0; j < nfree_lists; j++) { 6030 fl[j].ifl_rxq = rxq; 6031 fl[j].ifl_id = j; 6032 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6033 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6034 } 6035 /* Allocate receive buffers for the ring */ 6036 if (iflib_rxsd_alloc(rxq)) { 6037 device_printf(dev, 6038 "Critical Failure setting up receive buffers\n"); 6039 err = ENOMEM; 6040 goto err_rx_desc; 6041 } 6042 6043 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6044 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6045 M_WAITOK); 6046 } 6047 6048 /* TXQs */ 6049 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6050 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6051 for (i = 0; i < ntxqsets; i++) { 6052 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6053 6054 for (j = 0; j < ntxqs; j++, di++) { 6055 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6056 paddrs[i*ntxqs + j] = di->idi_paddr; 6057 } 6058 } 6059 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6060 device_printf(ctx->ifc_dev, 6061 "Unable to allocate device TX queue\n"); 6062 iflib_tx_structures_free(ctx); 6063 free(vaddrs, M_IFLIB); 6064 free(paddrs, M_IFLIB); 6065 goto err_rx_desc; 6066 } 6067 free(vaddrs, M_IFLIB); 6068 free(paddrs, M_IFLIB); 6069 6070 /* RXQs */ 6071 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6072 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6073 for (i = 0; i < nrxqsets; i++) { 6074 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6075 6076 for (j = 0; j < nrxqs; j++, di++) { 6077 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6078 paddrs[i*nrxqs + j] = di->idi_paddr; 6079 } 6080 } 6081 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6082 device_printf(ctx->ifc_dev, 6083 "Unable to allocate device RX queue\n"); 6084 iflib_tx_structures_free(ctx); 6085 free(vaddrs, M_IFLIB); 6086 free(paddrs, M_IFLIB); 6087 goto err_rx_desc; 6088 } 6089 free(vaddrs, M_IFLIB); 6090 free(paddrs, M_IFLIB); 6091 6092 return (0); 6093 6094 /* XXX handle allocation failure changes */ 6095 err_rx_desc: 6096 err_tx_desc: 6097 rx_fail: 6098 if (ctx->ifc_rxqs != NULL) 6099 free(ctx->ifc_rxqs, M_IFLIB); 6100 ctx->ifc_rxqs = NULL; 6101 if (ctx->ifc_txqs != NULL) 6102 free(ctx->ifc_txqs, M_IFLIB); 6103 ctx->ifc_txqs = NULL; 6104 fail: 6105 return (err); 6106 } 6107 6108 static int 6109 iflib_tx_structures_setup(if_ctx_t ctx) 6110 { 6111 iflib_txq_t txq = ctx->ifc_txqs; 6112 int i; 6113 6114 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6115 iflib_txq_setup(txq); 6116 6117 return (0); 6118 } 6119 6120 static void 6121 iflib_tx_structures_free(if_ctx_t ctx) 6122 { 6123 iflib_txq_t txq = ctx->ifc_txqs; 6124 if_shared_ctx_t sctx = ctx->ifc_sctx; 6125 int i, j; 6126 6127 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6128 for (j = 0; j < sctx->isc_ntxqs; j++) 6129 iflib_dma_free(&txq->ift_ifdi[j]); 6130 iflib_txq_destroy(txq); 6131 } 6132 free(ctx->ifc_txqs, M_IFLIB); 6133 ctx->ifc_txqs = NULL; 6134 } 6135 6136 /********************************************************************* 6137 * 6138 * Initialize all receive rings. 6139 * 6140 **********************************************************************/ 6141 static int 6142 iflib_rx_structures_setup(if_ctx_t ctx) 6143 { 6144 iflib_rxq_t rxq = ctx->ifc_rxqs; 6145 int q; 6146 #if defined(INET6) || defined(INET) 6147 int err, i; 6148 #endif 6149 6150 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6151 #if defined(INET6) || defined(INET) 6152 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 6153 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6154 TCP_LRO_ENTRIES, min(1024, 6155 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6156 if (err != 0) { 6157 device_printf(ctx->ifc_dev, 6158 "LRO Initialization failed!\n"); 6159 goto fail; 6160 } 6161 } 6162 #endif 6163 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6164 } 6165 return (0); 6166 #if defined(INET6) || defined(INET) 6167 fail: 6168 /* 6169 * Free LRO resources allocated so far, we will only handle 6170 * the rings that completed, the failing case will have 6171 * cleaned up for itself. 'q' failed, so its the terminus. 6172 */ 6173 rxq = ctx->ifc_rxqs; 6174 for (i = 0; i < q; ++i, rxq++) { 6175 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 6176 tcp_lro_free(&rxq->ifr_lc); 6177 } 6178 return (err); 6179 #endif 6180 } 6181 6182 /********************************************************************* 6183 * 6184 * Free all receive rings. 6185 * 6186 **********************************************************************/ 6187 static void 6188 iflib_rx_structures_free(if_ctx_t ctx) 6189 { 6190 iflib_rxq_t rxq = ctx->ifc_rxqs; 6191 if_shared_ctx_t sctx = ctx->ifc_sctx; 6192 int i, j; 6193 6194 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6195 for (j = 0; j < sctx->isc_nrxqs; j++) 6196 iflib_dma_free(&rxq->ifr_ifdi[j]); 6197 iflib_rx_sds_free(rxq); 6198 #if defined(INET6) || defined(INET) 6199 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 6200 tcp_lro_free(&rxq->ifr_lc); 6201 #endif 6202 } 6203 free(ctx->ifc_rxqs, M_IFLIB); 6204 ctx->ifc_rxqs = NULL; 6205 } 6206 6207 static int 6208 iflib_qset_structures_setup(if_ctx_t ctx) 6209 { 6210 int err; 6211 6212 /* 6213 * It is expected that the caller takes care of freeing queues if this 6214 * fails. 6215 */ 6216 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6217 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6218 return (err); 6219 } 6220 6221 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6222 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6223 6224 return (err); 6225 } 6226 6227 int 6228 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6229 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6230 { 6231 6232 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6233 } 6234 6235 /* Just to avoid copy/paste */ 6236 static inline int 6237 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6238 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6239 const char *name) 6240 { 6241 device_t dev; 6242 unsigned int base_cpuid, cpuid; 6243 int err; 6244 6245 dev = ctx->ifc_dev; 6246 base_cpuid = ctx->ifc_sysctl_core_offset; 6247 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6248 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6249 irq ? irq->ii_res : NULL, name); 6250 if (err) { 6251 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6252 return (err); 6253 } 6254 #ifdef notyet 6255 if (cpuid > ctx->ifc_cpuid_highest) 6256 ctx->ifc_cpuid_highest = cpuid; 6257 #endif 6258 return (0); 6259 } 6260 6261 int 6262 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6263 iflib_intr_type_t type, driver_filter_t *filter, 6264 void *filter_arg, int qid, const char *name) 6265 { 6266 device_t dev; 6267 struct grouptask *gtask; 6268 struct taskqgroup *tqg; 6269 iflib_filter_info_t info; 6270 gtask_fn_t *fn; 6271 int tqrid, err; 6272 driver_filter_t *intr_fast; 6273 void *q; 6274 6275 info = &ctx->ifc_filter_info; 6276 tqrid = rid; 6277 6278 switch (type) { 6279 /* XXX merge tx/rx for netmap? */ 6280 case IFLIB_INTR_TX: 6281 q = &ctx->ifc_txqs[qid]; 6282 info = &ctx->ifc_txqs[qid].ift_filter_info; 6283 gtask = &ctx->ifc_txqs[qid].ift_task; 6284 tqg = qgroup_if_io_tqg; 6285 fn = _task_fn_tx; 6286 intr_fast = iflib_fast_intr; 6287 GROUPTASK_INIT(gtask, 0, fn, q); 6288 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6289 break; 6290 case IFLIB_INTR_RX: 6291 q = &ctx->ifc_rxqs[qid]; 6292 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6293 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6294 tqg = qgroup_if_io_tqg; 6295 fn = _task_fn_rx; 6296 intr_fast = iflib_fast_intr; 6297 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6298 break; 6299 case IFLIB_INTR_RXTX: 6300 q = &ctx->ifc_rxqs[qid]; 6301 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6302 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6303 tqg = qgroup_if_io_tqg; 6304 fn = _task_fn_rx; 6305 intr_fast = iflib_fast_intr_rxtx; 6306 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6307 break; 6308 case IFLIB_INTR_ADMIN: 6309 q = ctx; 6310 tqrid = -1; 6311 info = &ctx->ifc_filter_info; 6312 gtask = &ctx->ifc_admin_task; 6313 tqg = qgroup_if_config_tqg; 6314 fn = _task_fn_admin; 6315 intr_fast = iflib_fast_intr_ctx; 6316 break; 6317 default: 6318 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6319 __func__); 6320 return (EINVAL); 6321 } 6322 6323 info->ifi_filter = filter; 6324 info->ifi_filter_arg = filter_arg; 6325 info->ifi_task = gtask; 6326 info->ifi_ctx = q; 6327 6328 dev = ctx->ifc_dev; 6329 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6330 if (err != 0) { 6331 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6332 return (err); 6333 } 6334 if (type == IFLIB_INTR_ADMIN) 6335 return (0); 6336 6337 if (tqrid != -1) { 6338 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6339 name); 6340 if (err) 6341 return (err); 6342 } else { 6343 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6344 } 6345 6346 return (0); 6347 } 6348 6349 void 6350 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6351 { 6352 device_t dev; 6353 struct grouptask *gtask; 6354 struct taskqgroup *tqg; 6355 gtask_fn_t *fn; 6356 void *q; 6357 int err; 6358 6359 switch (type) { 6360 case IFLIB_INTR_TX: 6361 q = &ctx->ifc_txqs[qid]; 6362 gtask = &ctx->ifc_txqs[qid].ift_task; 6363 tqg = qgroup_if_io_tqg; 6364 fn = _task_fn_tx; 6365 GROUPTASK_INIT(gtask, 0, fn, q); 6366 break; 6367 case IFLIB_INTR_RX: 6368 q = &ctx->ifc_rxqs[qid]; 6369 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6370 tqg = qgroup_if_io_tqg; 6371 fn = _task_fn_rx; 6372 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6373 break; 6374 case IFLIB_INTR_IOV: 6375 q = ctx; 6376 gtask = &ctx->ifc_vflr_task; 6377 tqg = qgroup_if_config_tqg; 6378 fn = _task_fn_iov; 6379 GROUPTASK_INIT(gtask, 0, fn, q); 6380 break; 6381 default: 6382 panic("unknown net intr type"); 6383 } 6384 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6385 if (err) { 6386 dev = ctx->ifc_dev; 6387 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6388 name); 6389 } 6390 } 6391 6392 void 6393 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6394 { 6395 6396 if (irq->ii_tag) 6397 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6398 6399 if (irq->ii_res) 6400 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6401 rman_get_rid(irq->ii_res), irq->ii_res); 6402 } 6403 6404 static int 6405 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6406 { 6407 iflib_txq_t txq = ctx->ifc_txqs; 6408 iflib_rxq_t rxq = ctx->ifc_rxqs; 6409 if_irq_t irq = &ctx->ifc_legacy_irq; 6410 iflib_filter_info_t info; 6411 device_t dev; 6412 struct grouptask *gtask; 6413 struct resource *res; 6414 struct taskqgroup *tqg; 6415 void *q; 6416 int err, tqrid; 6417 bool rx_only; 6418 6419 q = &ctx->ifc_rxqs[0]; 6420 info = &rxq[0].ifr_filter_info; 6421 gtask = &rxq[0].ifr_task; 6422 tqg = qgroup_if_io_tqg; 6423 tqrid = *rid; 6424 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6425 6426 ctx->ifc_flags |= IFC_LEGACY; 6427 info->ifi_filter = filter; 6428 info->ifi_filter_arg = filter_arg; 6429 info->ifi_task = gtask; 6430 info->ifi_ctx = rx_only ? ctx : q; 6431 6432 dev = ctx->ifc_dev; 6433 /* We allocate a single interrupt resource */ 6434 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6435 iflib_fast_intr_rxtx, NULL, info, name); 6436 if (err != 0) 6437 return (err); 6438 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6439 res = irq->ii_res; 6440 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6441 6442 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6443 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6444 "tx"); 6445 return (0); 6446 } 6447 6448 void 6449 iflib_led_create(if_ctx_t ctx) 6450 { 6451 6452 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6453 device_get_nameunit(ctx->ifc_dev)); 6454 } 6455 6456 void 6457 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6458 { 6459 6460 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6461 } 6462 6463 void 6464 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6465 { 6466 6467 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6468 } 6469 6470 void 6471 iflib_admin_intr_deferred(if_ctx_t ctx) 6472 { 6473 6474 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6475 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6476 } 6477 6478 void 6479 iflib_iov_intr_deferred(if_ctx_t ctx) 6480 { 6481 6482 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6483 } 6484 6485 void 6486 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6487 { 6488 6489 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6490 name); 6491 } 6492 6493 void 6494 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6495 const char *name) 6496 { 6497 6498 GROUPTASK_INIT(gtask, 0, fn, ctx); 6499 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6500 name); 6501 } 6502 6503 void 6504 iflib_config_gtask_deinit(struct grouptask *gtask) 6505 { 6506 6507 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6508 } 6509 6510 void 6511 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6512 { 6513 if_t ifp = ctx->ifc_ifp; 6514 iflib_txq_t txq = ctx->ifc_txqs; 6515 6516 if_setbaudrate(ifp, baudrate); 6517 if (baudrate >= IF_Gbps(10)) { 6518 STATE_LOCK(ctx); 6519 ctx->ifc_flags |= IFC_PREFETCH; 6520 STATE_UNLOCK(ctx); 6521 } 6522 /* If link down, disable watchdog */ 6523 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6524 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6525 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6526 } 6527 ctx->ifc_link_state = link_state; 6528 if_link_state_change(ifp, link_state); 6529 } 6530 6531 static int 6532 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6533 { 6534 int credits; 6535 #ifdef INVARIANTS 6536 int credits_pre = txq->ift_cidx_processed; 6537 #endif 6538 6539 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6540 BUS_DMASYNC_POSTREAD); 6541 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6542 return (0); 6543 6544 txq->ift_processed += credits; 6545 txq->ift_cidx_processed += credits; 6546 6547 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6548 if (txq->ift_cidx_processed >= txq->ift_size) 6549 txq->ift_cidx_processed -= txq->ift_size; 6550 return (credits); 6551 } 6552 6553 static int 6554 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6555 { 6556 iflib_fl_t fl; 6557 u_int i; 6558 6559 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6560 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6561 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6562 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6563 budget)); 6564 } 6565 6566 void 6567 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6568 const char *description, if_int_delay_info_t info, 6569 int offset, int value) 6570 { 6571 info->iidi_ctx = ctx; 6572 info->iidi_offset = offset; 6573 info->iidi_value = value; 6574 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6575 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6576 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6577 info, 0, iflib_sysctl_int_delay, "I", description); 6578 } 6579 6580 struct sx * 6581 iflib_ctx_lock_get(if_ctx_t ctx) 6582 { 6583 6584 return (&ctx->ifc_ctx_sx); 6585 } 6586 6587 static int 6588 iflib_msix_init(if_ctx_t ctx) 6589 { 6590 device_t dev = ctx->ifc_dev; 6591 if_shared_ctx_t sctx = ctx->ifc_sctx; 6592 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6593 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6594 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6595 6596 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6597 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6598 6599 if (bootverbose) 6600 device_printf(dev, "msix_init qsets capped at %d\n", 6601 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6602 6603 /* Override by tuneable */ 6604 if (scctx->isc_disable_msix) 6605 goto msi; 6606 6607 /* First try MSI-X */ 6608 if ((msgs = pci_msix_count(dev)) == 0) { 6609 if (bootverbose) 6610 device_printf(dev, "MSI-X not supported or disabled\n"); 6611 goto msi; 6612 } 6613 6614 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6615 /* 6616 * bar == -1 => "trust me I know what I'm doing" 6617 * Some drivers are for hardware that is so shoddily 6618 * documented that no one knows which bars are which 6619 * so the developer has to map all bars. This hack 6620 * allows shoddy garbage to use MSI-X in this framework. 6621 */ 6622 if (bar != -1) { 6623 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6624 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6625 if (ctx->ifc_msix_mem == NULL) { 6626 device_printf(dev, "Unable to map MSI-X table\n"); 6627 goto msi; 6628 } 6629 } 6630 6631 admincnt = sctx->isc_admin_intrcnt; 6632 #if IFLIB_DEBUG 6633 /* use only 1 qset in debug mode */ 6634 queuemsgs = min(msgs - admincnt, 1); 6635 #else 6636 queuemsgs = msgs - admincnt; 6637 #endif 6638 #ifdef RSS 6639 queues = imin(queuemsgs, rss_getnumbuckets()); 6640 #else 6641 queues = queuemsgs; 6642 #endif 6643 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6644 if (bootverbose) 6645 device_printf(dev, 6646 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6647 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6648 #ifdef RSS 6649 /* If we're doing RSS, clamp at the number of RSS buckets */ 6650 if (queues > rss_getnumbuckets()) 6651 queues = rss_getnumbuckets(); 6652 #endif 6653 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6654 rx_queues = iflib_num_rx_queues; 6655 else 6656 rx_queues = queues; 6657 6658 if (rx_queues > scctx->isc_nrxqsets) 6659 rx_queues = scctx->isc_nrxqsets; 6660 6661 /* 6662 * We want this to be all logical CPUs by default 6663 */ 6664 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6665 tx_queues = iflib_num_tx_queues; 6666 else 6667 tx_queues = mp_ncpus; 6668 6669 if (tx_queues > scctx->isc_ntxqsets) 6670 tx_queues = scctx->isc_ntxqsets; 6671 6672 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6673 #ifdef INVARIANTS 6674 if (tx_queues != rx_queues) 6675 device_printf(dev, 6676 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6677 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6678 #endif 6679 tx_queues = min(rx_queues, tx_queues); 6680 rx_queues = min(rx_queues, tx_queues); 6681 } 6682 6683 vectors = rx_queues + admincnt; 6684 if (msgs < vectors) { 6685 device_printf(dev, 6686 "insufficient number of MSI-X vectors " 6687 "(supported %d, need %d)\n", msgs, vectors); 6688 goto msi; 6689 } 6690 6691 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6692 tx_queues); 6693 msgs = vectors; 6694 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6695 if (vectors != msgs) { 6696 device_printf(dev, 6697 "Unable to allocate sufficient MSI-X vectors " 6698 "(got %d, need %d)\n", vectors, msgs); 6699 pci_release_msi(dev); 6700 if (bar != -1) { 6701 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6702 ctx->ifc_msix_mem); 6703 ctx->ifc_msix_mem = NULL; 6704 } 6705 goto msi; 6706 } 6707 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6708 vectors); 6709 scctx->isc_vectors = vectors; 6710 scctx->isc_nrxqsets = rx_queues; 6711 scctx->isc_ntxqsets = tx_queues; 6712 scctx->isc_intr = IFLIB_INTR_MSIX; 6713 6714 return (vectors); 6715 } else { 6716 device_printf(dev, 6717 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6718 err); 6719 if (bar != -1) { 6720 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6721 ctx->ifc_msix_mem); 6722 ctx->ifc_msix_mem = NULL; 6723 } 6724 } 6725 6726 msi: 6727 vectors = pci_msi_count(dev); 6728 scctx->isc_nrxqsets = 1; 6729 scctx->isc_ntxqsets = 1; 6730 scctx->isc_vectors = vectors; 6731 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6732 device_printf(dev,"Using an MSI interrupt\n"); 6733 scctx->isc_intr = IFLIB_INTR_MSI; 6734 } else { 6735 scctx->isc_vectors = 1; 6736 device_printf(dev,"Using a Legacy interrupt\n"); 6737 scctx->isc_intr = IFLIB_INTR_LEGACY; 6738 } 6739 6740 return (vectors); 6741 } 6742 6743 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6744 6745 static int 6746 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6747 { 6748 int rc; 6749 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6750 struct sbuf *sb; 6751 const char *ring_state = "UNKNOWN"; 6752 6753 /* XXX needed ? */ 6754 rc = sysctl_wire_old_buffer(req, 0); 6755 MPASS(rc == 0); 6756 if (rc != 0) 6757 return (rc); 6758 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6759 MPASS(sb != NULL); 6760 if (sb == NULL) 6761 return (ENOMEM); 6762 if (state[3] <= 3) 6763 ring_state = ring_states[state[3]]; 6764 6765 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6766 state[0], state[1], state[2], ring_state); 6767 rc = sbuf_finish(sb); 6768 sbuf_delete(sb); 6769 return(rc); 6770 } 6771 6772 enum iflib_ndesc_handler { 6773 IFLIB_NTXD_HANDLER, 6774 IFLIB_NRXD_HANDLER, 6775 }; 6776 6777 static int 6778 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6779 { 6780 if_ctx_t ctx = (void *)arg1; 6781 enum iflib_ndesc_handler type = arg2; 6782 char buf[256] = {0}; 6783 qidx_t *ndesc; 6784 char *p, *next; 6785 int nqs, rc, i; 6786 6787 nqs = 8; 6788 switch(type) { 6789 case IFLIB_NTXD_HANDLER: 6790 ndesc = ctx->ifc_sysctl_ntxds; 6791 if (ctx->ifc_sctx) 6792 nqs = ctx->ifc_sctx->isc_ntxqs; 6793 break; 6794 case IFLIB_NRXD_HANDLER: 6795 ndesc = ctx->ifc_sysctl_nrxds; 6796 if (ctx->ifc_sctx) 6797 nqs = ctx->ifc_sctx->isc_nrxqs; 6798 break; 6799 default: 6800 printf("%s: unhandled type\n", __func__); 6801 return (EINVAL); 6802 } 6803 if (nqs == 0) 6804 nqs = 8; 6805 6806 for (i=0; i<8; i++) { 6807 if (i >= nqs) 6808 break; 6809 if (i) 6810 strcat(buf, ","); 6811 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6812 } 6813 6814 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6815 if (rc || req->newptr == NULL) 6816 return rc; 6817 6818 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6819 i++, p = strsep(&next, " ,")) { 6820 ndesc[i] = strtoul(p, NULL, 10); 6821 } 6822 6823 return(rc); 6824 } 6825 6826 #define NAME_BUFLEN 32 6827 static void 6828 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6829 { 6830 device_t dev = iflib_get_dev(ctx); 6831 struct sysctl_oid_list *child, *oid_list; 6832 struct sysctl_ctx_list *ctx_list; 6833 struct sysctl_oid *node; 6834 6835 ctx_list = device_get_sysctl_ctx(dev); 6836 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6837 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6838 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6839 oid_list = SYSCTL_CHILDREN(node); 6840 6841 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6842 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6843 "driver version"); 6844 6845 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6846 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6847 "# of txqs to use, 0 => use default #"); 6848 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6849 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6850 "# of rxqs to use, 0 => use default #"); 6851 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6852 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6853 "permit #txq != #rxq"); 6854 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6855 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6856 "disable MSI-X (default 0)"); 6857 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6858 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6859 "set the RX budget"); 6860 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6861 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6862 "cause TX to abdicate instead of running to completion"); 6863 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6864 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6865 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6866 "offset to start using cores at"); 6867 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6868 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6869 "use separate cores for TX and RX"); 6870 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6871 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6872 "try to make use of logical cores for TX and RX"); 6873 6874 /* XXX change for per-queue sizes */ 6875 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6876 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6877 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6878 "list of # of TX descriptors to use, 0 = use default #"); 6879 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6880 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6881 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6882 "list of # of RX descriptors to use, 0 = use default #"); 6883 } 6884 6885 static void 6886 iflib_add_device_sysctl_post(if_ctx_t ctx) 6887 { 6888 if_shared_ctx_t sctx = ctx->ifc_sctx; 6889 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6890 device_t dev = iflib_get_dev(ctx); 6891 struct sysctl_oid_list *child; 6892 struct sysctl_ctx_list *ctx_list; 6893 iflib_fl_t fl; 6894 iflib_txq_t txq; 6895 iflib_rxq_t rxq; 6896 int i, j; 6897 char namebuf[NAME_BUFLEN]; 6898 char *qfmt; 6899 struct sysctl_oid *queue_node, *fl_node, *node; 6900 struct sysctl_oid_list *queue_list, *fl_list; 6901 ctx_list = device_get_sysctl_ctx(dev); 6902 6903 node = ctx->ifc_sysctl_node; 6904 child = SYSCTL_CHILDREN(node); 6905 6906 if (scctx->isc_ntxqsets > 100) 6907 qfmt = "txq%03d"; 6908 else if (scctx->isc_ntxqsets > 10) 6909 qfmt = "txq%02d"; 6910 else 6911 qfmt = "txq%d"; 6912 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6913 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6914 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6915 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6916 queue_list = SYSCTL_CHILDREN(queue_node); 6917 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6918 CTLFLAG_RD, 6919 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6920 #if MEMORY_LOGGING 6921 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6922 CTLFLAG_RD, 6923 &txq->ift_dequeued, "total mbufs freed"); 6924 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6925 CTLFLAG_RD, 6926 &txq->ift_enqueued, "total mbufs enqueued"); 6927 #endif 6928 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6929 CTLFLAG_RD, 6930 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6931 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6932 CTLFLAG_RD, 6933 &txq->ift_pullups, "# of times m_pullup was called"); 6934 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6935 CTLFLAG_RD, 6936 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6937 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6938 CTLFLAG_RD, 6939 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6940 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6941 CTLFLAG_RD, 6942 &txq->ift_map_failed, "# of times DMA map failed"); 6943 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6944 CTLFLAG_RD, 6945 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6946 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6947 CTLFLAG_RD, 6948 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6949 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6950 CTLFLAG_RD, 6951 &txq->ift_pidx, 1, "Producer Index"); 6952 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6953 CTLFLAG_RD, 6954 &txq->ift_cidx, 1, "Consumer Index"); 6955 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6956 CTLFLAG_RD, 6957 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6958 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6959 CTLFLAG_RD, 6960 &txq->ift_in_use, 1, "descriptors in use"); 6961 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6962 CTLFLAG_RD, 6963 &txq->ift_processed, "descriptors procesed for clean"); 6964 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6965 CTLFLAG_RD, 6966 &txq->ift_cleaned, "total cleaned"); 6967 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6968 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6969 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6970 mp_ring_state_handler, "A", "soft ring state"); 6971 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6972 CTLFLAG_RD, &txq->ift_br->enqueues, 6973 "# of enqueues to the mp_ring for this queue"); 6974 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6975 CTLFLAG_RD, &txq->ift_br->drops, 6976 "# of drops in the mp_ring for this queue"); 6977 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6978 CTLFLAG_RD, &txq->ift_br->starts, 6979 "# of normal consumer starts in the mp_ring for this queue"); 6980 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6981 CTLFLAG_RD, &txq->ift_br->stalls, 6982 "# of consumer stalls in the mp_ring for this queue"); 6983 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6984 CTLFLAG_RD, &txq->ift_br->restarts, 6985 "# of consumer restarts in the mp_ring for this queue"); 6986 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6987 CTLFLAG_RD, &txq->ift_br->abdications, 6988 "# of consumer abdications in the mp_ring for this queue"); 6989 } 6990 6991 if (scctx->isc_nrxqsets > 100) 6992 qfmt = "rxq%03d"; 6993 else if (scctx->isc_nrxqsets > 10) 6994 qfmt = "rxq%02d"; 6995 else 6996 qfmt = "rxq%d"; 6997 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6998 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6999 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7000 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7001 queue_list = SYSCTL_CHILDREN(queue_node); 7002 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7003 CTLFLAG_RD, 7004 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7005 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7006 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7007 CTLFLAG_RD, 7008 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7009 } 7010 7011 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7012 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7013 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7014 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7015 fl_list = SYSCTL_CHILDREN(fl_node); 7016 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7017 CTLFLAG_RD, 7018 &fl->ifl_pidx, 1, "Producer Index"); 7019 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7020 CTLFLAG_RD, 7021 &fl->ifl_cidx, 1, "Consumer Index"); 7022 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7023 CTLFLAG_RD, 7024 &fl->ifl_credits, 1, "credits available"); 7025 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7026 CTLFLAG_RD, 7027 &fl->ifl_buf_size, 1, "buffer size"); 7028 #if MEMORY_LOGGING 7029 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7030 CTLFLAG_RD, 7031 &fl->ifl_m_enqueued, "mbufs allocated"); 7032 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7033 CTLFLAG_RD, 7034 &fl->ifl_m_dequeued, "mbufs freed"); 7035 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7036 CTLFLAG_RD, 7037 &fl->ifl_cl_enqueued, "clusters allocated"); 7038 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7039 CTLFLAG_RD, 7040 &fl->ifl_cl_dequeued, "clusters freed"); 7041 #endif 7042 } 7043 } 7044 7045 } 7046 7047 void 7048 iflib_request_reset(if_ctx_t ctx) 7049 { 7050 7051 STATE_LOCK(ctx); 7052 ctx->ifc_flags |= IFC_DO_RESET; 7053 STATE_UNLOCK(ctx); 7054 } 7055 7056 #ifndef __NO_STRICT_ALIGNMENT 7057 static struct mbuf * 7058 iflib_fixup_rx(struct mbuf *m) 7059 { 7060 struct mbuf *n; 7061 7062 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7063 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7064 m->m_data += ETHER_HDR_LEN; 7065 n = m; 7066 } else { 7067 MGETHDR(n, M_NOWAIT, MT_DATA); 7068 if (n == NULL) { 7069 m_freem(m); 7070 return (NULL); 7071 } 7072 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7073 m->m_data += ETHER_HDR_LEN; 7074 m->m_len -= ETHER_HDR_LEN; 7075 n->m_len = ETHER_HDR_LEN; 7076 M_MOVE_PKTHDR(n, m); 7077 n->m_next = m; 7078 } 7079 return (n); 7080 } 7081 #endif 7082 7083 #ifdef DEBUGNET 7084 static void 7085 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7086 { 7087 if_ctx_t ctx; 7088 7089 ctx = if_getsoftc(ifp); 7090 CTX_LOCK(ctx); 7091 *nrxr = NRXQSETS(ctx); 7092 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7093 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7094 CTX_UNLOCK(ctx); 7095 } 7096 7097 static void 7098 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7099 { 7100 if_ctx_t ctx; 7101 if_softc_ctx_t scctx; 7102 iflib_fl_t fl; 7103 iflib_rxq_t rxq; 7104 int i, j; 7105 7106 ctx = if_getsoftc(ifp); 7107 scctx = &ctx->ifc_softc_ctx; 7108 7109 switch (event) { 7110 case DEBUGNET_START: 7111 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7112 rxq = &ctx->ifc_rxqs[i]; 7113 for (j = 0; j < rxq->ifr_nfl; j++) { 7114 fl = rxq->ifr_fl; 7115 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7116 } 7117 } 7118 iflib_no_tx_batch = 1; 7119 break; 7120 default: 7121 break; 7122 } 7123 } 7124 7125 static int 7126 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7127 { 7128 if_ctx_t ctx; 7129 iflib_txq_t txq; 7130 int error; 7131 7132 ctx = if_getsoftc(ifp); 7133 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7134 IFF_DRV_RUNNING) 7135 return (EBUSY); 7136 7137 txq = &ctx->ifc_txqs[0]; 7138 error = iflib_encap(txq, &m); 7139 if (error == 0) 7140 (void)iflib_txd_db_check(txq, true); 7141 return (error); 7142 } 7143 7144 static int 7145 iflib_debugnet_poll(if_t ifp, int count) 7146 { 7147 struct epoch_tracker et; 7148 if_ctx_t ctx; 7149 if_softc_ctx_t scctx; 7150 iflib_txq_t txq; 7151 int i; 7152 7153 ctx = if_getsoftc(ifp); 7154 scctx = &ctx->ifc_softc_ctx; 7155 7156 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7157 IFF_DRV_RUNNING) 7158 return (EBUSY); 7159 7160 txq = &ctx->ifc_txqs[0]; 7161 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7162 7163 NET_EPOCH_ENTER(et); 7164 for (i = 0; i < scctx->isc_nrxqsets; i++) 7165 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7166 NET_EPOCH_EXIT(et); 7167 return (0); 7168 } 7169 #endif /* DEBUGNET */ 7170