1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
5 * Bill Paul <[email protected]>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
40 * Used in the LinkSys USB200M and various other adapters.
41 *
42 * Manuals available from:
43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
45 * controller) to find the definitions for the RX control register.
46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
47 *
48 * Written by Bill Paul <[email protected]>
49 * Senior Engineer
50 * Wind River Systems
51 */
52
53 /*
54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
55 * It uses an external PHY (reference designs use a RealTek chip),
56 * and has a 64-bit multicast hash filter. There is some information
57 * missing from the manual which one needs to know in order to make
58 * the chip function:
59 *
60 * - You must set bit 7 in the RX control register, otherwise the
61 * chip won't receive any packets.
62 * - You must initialize all 3 IPG registers, or you won't be able
63 * to send any packets.
64 *
65 * Note that this device appears to only support loading the station
66 * address via autload from the EEPROM (i.e. there's no way to manually
67 * set it).
68 *
69 * (Adam Weinberger wanted me to name this driver if_gir.c.)
70 */
71
72 /*
73 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
74 * 2007/02/12, J.R. Oldroyd, [email protected]
75 *
76 * Manual here:
77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
79 */
80
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/bus.h>
84 #include <sys/condvar.h>
85 #include <sys/endian.h>
86 #include <sys/kernel.h>
87 #include <sys/lock.h>
88 #include <sys/malloc.h>
89 #include <sys/mbuf.h>
90 #include <sys/module.h>
91 #include <sys/mutex.h>
92 #include <sys/socket.h>
93 #include <sys/sockio.h>
94 #include <sys/sysctl.h>
95 #include <sys/sx.h>
96
97 #include <net/if.h>
98 #include <net/if_var.h>
99 #include <net/ethernet.h>
100 #include <net/if_types.h>
101 #include <net/if_media.h>
102 #include <net/if_vlan_var.h>
103
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106
107 #include <dev/usb/usb.h>
108 #include <dev/usb/usbdi.h>
109 #include <dev/usb/usbdi_util.h>
110 #include "usbdevs.h"
111
112 #define USB_DEBUG_VAR axe_debug
113 #include <dev/usb/usb_debug.h>
114 #include <dev/usb/usb_process.h>
115
116 #include <dev/usb/net/usb_ethernet.h>
117 #include <dev/usb/net/if_axereg.h>
118
119 #include "miibus_if.h"
120
121 /*
122 * AXE_178_MAX_FRAME_BURST
123 * max frame burst size for Ax88178 and Ax88772
124 * 0 2048 bytes
125 * 1 4096 bytes
126 * 2 8192 bytes
127 * 3 16384 bytes
128 * use the largest your system can handle without USB stalling.
129 *
130 * NB: 88772 parts appear to generate lots of input errors with
131 * a 2K rx buffer and 8K is only slightly faster than 4K on an
132 * EHCI port on a T42 so change at your own risk.
133 */
134 #define AXE_178_MAX_FRAME_BURST 1
135
136 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138 #ifdef USB_DEBUG
139 static int axe_debug = 0;
140
141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
142 "USB axe");
143 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0,
144 "Debug level");
145 #endif
146
147 /*
148 * Various supported device vendors/products.
149 */
150 static const STRUCT_USB_HOST_ID axe_devs[] = {
151 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
152 AXE_DEV(ABOCOM, UF200, 0),
153 AXE_DEV(ACERCM, EP1427X2, 0),
154 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
155 AXE_DEV(ASIX, AX88172, 0),
156 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
157 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
158 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
159 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
160 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
161 AXE_DEV(ATEN, UC210T, 0),
162 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
163 AXE_DEV(BILLIONTON, USB2AR, 0),
164 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
165 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
166 AXE_DEV(DLINK, DUBE100, 0),
167 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
168 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
169 AXE_DEV(GOODWAY, GWUSB2E, 0),
170 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
171 AXE_DEV(JVC, MP_PRX1, 0),
172 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
173 AXE_DEV(LINKSYS2, USB200M, 0),
174 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
175 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
176 AXE_DEV(MELCO, LUAU2KTX, 0),
177 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
178 AXE_DEV(NETGEAR, FA120, 0),
179 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
180 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
181 AXE_DEV(SITECOM, LN029, 0),
182 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
183 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178),
184 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
185 #undef AXE_DEV
186 };
187
188 static device_probe_t axe_probe;
189 static device_attach_t axe_attach;
190 static device_detach_t axe_detach;
191
192 static usb_callback_t axe_bulk_read_callback;
193 static usb_callback_t axe_bulk_write_callback;
194
195 static miibus_readreg_t axe_miibus_readreg;
196 static miibus_writereg_t axe_miibus_writereg;
197 static miibus_statchg_t axe_miibus_statchg;
198
199 static uether_fn_t axe_attach_post;
200 static uether_fn_t axe_init;
201 static uether_fn_t axe_stop;
202 static uether_fn_t axe_start;
203 static uether_fn_t axe_tick;
204 static uether_fn_t axe_setmulti;
205 static uether_fn_t axe_setpromisc;
206
207 static int axe_attach_post_sub(struct usb_ether *);
208 static int axe_ifmedia_upd(struct ifnet *);
209 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
210 static int axe_cmd(struct axe_softc *, int, int, int, void *);
211 static void axe_ax88178_init(struct axe_softc *);
212 static void axe_ax88772_init(struct axe_softc *);
213 static void axe_ax88772_phywake(struct axe_softc *);
214 static void axe_ax88772a_init(struct axe_softc *);
215 static void axe_ax88772b_init(struct axe_softc *);
216 static int axe_get_phyno(struct axe_softc *, int);
217 static int axe_ioctl(struct ifnet *, u_long, caddr_t);
218 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
219 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
220 unsigned int offset, unsigned int, struct axe_csum_hdr *);
221 static void axe_csum_cfg(struct usb_ether *);
222
223 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
224 [AXE_BULK_DT_WR] = {
225 .type = UE_BULK,
226 .endpoint = UE_ADDR_ANY,
227 .direction = UE_DIR_OUT,
228 .frames = 16,
229 .bufsize = 16 * MCLBYTES,
230 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
231 .callback = axe_bulk_write_callback,
232 .timeout = 10000, /* 10 seconds */
233 },
234
235 [AXE_BULK_DT_RD] = {
236 .type = UE_BULK,
237 .endpoint = UE_ADDR_ANY,
238 .direction = UE_DIR_IN,
239 .bufsize = 16384, /* bytes */
240 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
241 .callback = axe_bulk_read_callback,
242 .timeout = 0, /* no timeout */
243 },
244 };
245
246 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
247 { 0x8000, 0x8001, 2048 },
248 { 0x8100, 0x8147, 4096},
249 { 0x8200, 0x81EB, 6144},
250 { 0x8300, 0x83D7, 8192},
251 { 0x8400, 0x851E, 16384},
252 { 0x8500, 0x8666, 20480},
253 { 0x8600, 0x87AE, 24576},
254 { 0x8700, 0x8A3D, 32768}
255 };
256
257 static device_method_t axe_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, axe_probe),
260 DEVMETHOD(device_attach, axe_attach),
261 DEVMETHOD(device_detach, axe_detach),
262
263 /* MII interface */
264 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
265 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
266 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
267
268 DEVMETHOD_END
269 };
270
271 static driver_t axe_driver = {
272 .name = "axe",
273 .methods = axe_methods,
274 .size = sizeof(struct axe_softc),
275 };
276
277 static devclass_t axe_devclass;
278
279 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
280 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
281 MODULE_DEPEND(axe, uether, 1, 1, 1);
282 MODULE_DEPEND(axe, usb, 1, 1, 1);
283 MODULE_DEPEND(axe, ether, 1, 1, 1);
284 MODULE_DEPEND(axe, miibus, 1, 1, 1);
285 MODULE_VERSION(axe, 1);
286 USB_PNP_HOST_INFO(axe_devs);
287
288 static const struct usb_ether_methods axe_ue_methods = {
289 .ue_attach_post = axe_attach_post,
290 .ue_attach_post_sub = axe_attach_post_sub,
291 .ue_start = axe_start,
292 .ue_init = axe_init,
293 .ue_stop = axe_stop,
294 .ue_tick = axe_tick,
295 .ue_setmulti = axe_setmulti,
296 .ue_setpromisc = axe_setpromisc,
297 .ue_mii_upd = axe_ifmedia_upd,
298 .ue_mii_sts = axe_ifmedia_sts,
299 };
300
301 static int
axe_cmd(struct axe_softc * sc,int cmd,int index,int val,void * buf)302 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
303 {
304 struct usb_device_request req;
305 usb_error_t err;
306
307 AXE_LOCK_ASSERT(sc, MA_OWNED);
308
309 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
310 UT_WRITE_VENDOR_DEVICE :
311 UT_READ_VENDOR_DEVICE);
312 req.bRequest = AXE_CMD_CMD(cmd);
313 USETW(req.wValue, val);
314 USETW(req.wIndex, index);
315 USETW(req.wLength, AXE_CMD_LEN(cmd));
316
317 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
318
319 return (err);
320 }
321
322 static int
axe_miibus_readreg(device_t dev,int phy,int reg)323 axe_miibus_readreg(device_t dev, int phy, int reg)
324 {
325 struct axe_softc *sc = device_get_softc(dev);
326 uint16_t val;
327 int locked;
328
329 locked = mtx_owned(&sc->sc_mtx);
330 if (!locked)
331 AXE_LOCK(sc);
332
333 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
334 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
336
337 val = le16toh(val);
338 if (AXE_IS_772(sc) && reg == MII_BMSR) {
339 /*
340 * BMSR of AX88772 indicates that it supports extended
341 * capability but the extended status register is
342 * revered for embedded ethernet PHY. So clear the
343 * extended capability bit of BMSR.
344 */
345 val &= ~BMSR_EXTCAP;
346 }
347
348 if (!locked)
349 AXE_UNLOCK(sc);
350 return (val);
351 }
352
353 static int
axe_miibus_writereg(device_t dev,int phy,int reg,int val)354 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
355 {
356 struct axe_softc *sc = device_get_softc(dev);
357 int locked;
358
359 val = htole32(val);
360 locked = mtx_owned(&sc->sc_mtx);
361 if (!locked)
362 AXE_LOCK(sc);
363
364 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
365 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
366 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
367
368 if (!locked)
369 AXE_UNLOCK(sc);
370 return (0);
371 }
372
373 static void
axe_miibus_statchg(device_t dev)374 axe_miibus_statchg(device_t dev)
375 {
376 struct axe_softc *sc = device_get_softc(dev);
377 struct mii_data *mii = GET_MII(sc);
378 struct ifnet *ifp;
379 uint16_t val;
380 int err, locked;
381
382 locked = mtx_owned(&sc->sc_mtx);
383 if (!locked)
384 AXE_LOCK(sc);
385
386 ifp = uether_getifp(&sc->sc_ue);
387 if (mii == NULL || ifp == NULL ||
388 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
389 goto done;
390
391 sc->sc_flags &= ~AXE_FLAG_LINK;
392 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
393 (IFM_ACTIVE | IFM_AVALID)) {
394 switch (IFM_SUBTYPE(mii->mii_media_active)) {
395 case IFM_10_T:
396 case IFM_100_TX:
397 sc->sc_flags |= AXE_FLAG_LINK;
398 break;
399 case IFM_1000_T:
400 if ((sc->sc_flags & AXE_FLAG_178) == 0)
401 break;
402 sc->sc_flags |= AXE_FLAG_LINK;
403 break;
404 default:
405 break;
406 }
407 }
408
409 /* Lost link, do nothing. */
410 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
411 goto done;
412
413 val = 0;
414 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
415 val |= AXE_MEDIA_FULL_DUPLEX;
416 if (AXE_IS_178_FAMILY(sc)) {
417 if ((IFM_OPTIONS(mii->mii_media_active) &
418 IFM_ETH_TXPAUSE) != 0)
419 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
420 if ((IFM_OPTIONS(mii->mii_media_active) &
421 IFM_ETH_RXPAUSE) != 0)
422 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
423 }
424 }
425 if (AXE_IS_178_FAMILY(sc)) {
426 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
427 if ((sc->sc_flags & AXE_FLAG_178) != 0)
428 val |= AXE_178_MEDIA_ENCK;
429 switch (IFM_SUBTYPE(mii->mii_media_active)) {
430 case IFM_1000_T:
431 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
432 break;
433 case IFM_100_TX:
434 val |= AXE_178_MEDIA_100TX;
435 break;
436 case IFM_10_T:
437 /* doesn't need to be handled */
438 break;
439 }
440 }
441 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
442 if (err)
443 device_printf(dev, "media change failed, error %d\n", err);
444 done:
445 if (!locked)
446 AXE_UNLOCK(sc);
447 }
448
449 /*
450 * Set media options.
451 */
452 static int
axe_ifmedia_upd(struct ifnet * ifp)453 axe_ifmedia_upd(struct ifnet *ifp)
454 {
455 struct axe_softc *sc = ifp->if_softc;
456 struct mii_data *mii = GET_MII(sc);
457 struct mii_softc *miisc;
458 int error;
459
460 AXE_LOCK_ASSERT(sc, MA_OWNED);
461
462 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
463 PHY_RESET(miisc);
464 error = mii_mediachg(mii);
465 return (error);
466 }
467
468 /*
469 * Report current media status.
470 */
471 static void
axe_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)472 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
473 {
474 struct axe_softc *sc = ifp->if_softc;
475 struct mii_data *mii = GET_MII(sc);
476
477 AXE_LOCK(sc);
478 mii_pollstat(mii);
479 ifmr->ifm_active = mii->mii_media_active;
480 ifmr->ifm_status = mii->mii_media_status;
481 AXE_UNLOCK(sc);
482 }
483
484 static u_int
axe_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)485 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
486 {
487 uint8_t *hashtbl = arg;
488 uint32_t h;
489
490 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
491 hashtbl[h / 8] |= 1 << (h % 8);
492
493 return (1);
494 }
495
496 static void
axe_setmulti(struct usb_ether * ue)497 axe_setmulti(struct usb_ether *ue)
498 {
499 struct axe_softc *sc = uether_getsc(ue);
500 struct ifnet *ifp = uether_getifp(ue);
501 uint16_t rxmode;
502 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
503
504 AXE_LOCK_ASSERT(sc, MA_OWNED);
505
506 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
507 rxmode = le16toh(rxmode);
508
509 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
510 rxmode |= AXE_RXCMD_ALLMULTI;
511 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
512 return;
513 }
514 rxmode &= ~AXE_RXCMD_ALLMULTI;
515
516 if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl);
517
518 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
519 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
520 }
521
522 static int
axe_get_phyno(struct axe_softc * sc,int sel)523 axe_get_phyno(struct axe_softc *sc, int sel)
524 {
525 int phyno;
526
527 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
528 case PHY_TYPE_100_HOME:
529 case PHY_TYPE_GIG:
530 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
531 break;
532 case PHY_TYPE_SPECIAL:
533 /* FALLTHROUGH */
534 case PHY_TYPE_RSVD:
535 /* FALLTHROUGH */
536 case PHY_TYPE_NON_SUP:
537 /* FALLTHROUGH */
538 default:
539 phyno = -1;
540 break;
541 }
542
543 return (phyno);
544 }
545
546 #define AXE_GPIO_WRITE(x, y) do { \
547 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
548 uether_pause(ue, (y)); \
549 } while (0)
550
551 static void
axe_ax88178_init(struct axe_softc * sc)552 axe_ax88178_init(struct axe_softc *sc)
553 {
554 struct usb_ether *ue;
555 int gpio0, ledmode, phymode;
556 uint16_t eeprom, val;
557
558 ue = &sc->sc_ue;
559 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
560 /* XXX magic */
561 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
562 eeprom = le16toh(eeprom);
563 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
564
565 /* if EEPROM is invalid we have to use to GPIO0 */
566 if (eeprom == 0xffff) {
567 phymode = AXE_PHY_MODE_MARVELL;
568 gpio0 = 1;
569 ledmode = 0;
570 } else {
571 phymode = eeprom & 0x7f;
572 gpio0 = (eeprom & 0x80) ? 0 : 1;
573 ledmode = eeprom >> 8;
574 }
575
576 if (bootverbose)
577 device_printf(sc->sc_ue.ue_dev,
578 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
579 phymode);
580 /* Program GPIOs depending on PHY hardware. */
581 switch (phymode) {
582 case AXE_PHY_MODE_MARVELL:
583 if (gpio0 == 1) {
584 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
585 hz / 32);
586 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
587 hz / 32);
588 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
589 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
590 hz / 32);
591 } else {
592 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
593 AXE_GPIO1_EN, hz / 3);
594 if (ledmode == 1) {
595 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
597 hz / 3);
598 } else {
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
600 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
601 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
602 AXE_GPIO2_EN, hz / 4);
603 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
604 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
605 }
606 }
607 break;
608 case AXE_PHY_MODE_CICADA:
609 case AXE_PHY_MODE_CICADA_V2:
610 case AXE_PHY_MODE_CICADA_V2_ASIX:
611 if (gpio0 == 1)
612 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
613 AXE_GPIO0_EN, hz / 32);
614 else
615 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
616 AXE_GPIO1_EN, hz / 32);
617 break;
618 case AXE_PHY_MODE_AGERE:
619 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
620 AXE_GPIO1_EN, hz / 32);
621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
622 AXE_GPIO2_EN, hz / 32);
623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
624 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
625 AXE_GPIO2_EN, hz / 32);
626 break;
627 case AXE_PHY_MODE_REALTEK_8211CL:
628 case AXE_PHY_MODE_REALTEK_8211BN:
629 case AXE_PHY_MODE_REALTEK_8251CL:
630 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
631 AXE_GPIO1 | AXE_GPIO1_EN;
632 AXE_GPIO_WRITE(val, hz / 32);
633 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
635 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
636 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
638 0x1F, 0x0005);
639 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
640 0x0C, 0x0000);
641 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
642 0x0001);
643 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
644 0x01, val | 0x0080);
645 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
646 0x1F, 0x0000);
647 }
648 break;
649 default:
650 /* Unknown PHY model or no need to program GPIOs. */
651 break;
652 }
653
654 /* soft reset */
655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
656 uether_pause(ue, hz / 4);
657
658 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
659 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
660 uether_pause(ue, hz / 4);
661 /* Enable MII/GMII/RGMII interface to work with external PHY. */
662 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
663 uether_pause(ue, hz / 4);
664
665 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
666 }
667
668 static void
axe_ax88772_init(struct axe_softc * sc)669 axe_ax88772_init(struct axe_softc *sc)
670 {
671 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
672 uether_pause(&sc->sc_ue, hz / 16);
673
674 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
675 /* ask for the embedded PHY */
676 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
677 uether_pause(&sc->sc_ue, hz / 64);
678
679 /* power down and reset state, pin reset state */
680 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
681 AXE_SW_RESET_CLEAR, NULL);
682 uether_pause(&sc->sc_ue, hz / 16);
683
684 /* power down/reset state, pin operating state */
685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
686 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
687 uether_pause(&sc->sc_ue, hz / 4);
688
689 /* power up, reset */
690 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
691
692 /* power up, operating */
693 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
694 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
695 } else {
696 /* ask for external PHY */
697 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
698 uether_pause(&sc->sc_ue, hz / 64);
699
700 /* power down internal PHY */
701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
702 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
703 }
704
705 uether_pause(&sc->sc_ue, hz / 4);
706 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
707 }
708
709 static void
axe_ax88772_phywake(struct axe_softc * sc)710 axe_ax88772_phywake(struct axe_softc *sc)
711 {
712 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
713 /* Manually select internal(embedded) PHY - MAC mode. */
714 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
715 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
716 NULL);
717 uether_pause(&sc->sc_ue, hz / 32);
718 } else {
719 /*
720 * Manually select external PHY - MAC mode.
721 * Reverse MII/RMII is for AX88772A PHY mode.
722 */
723 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
724 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
725 uether_pause(&sc->sc_ue, hz / 32);
726 }
727 /* Take PHY out of power down. */
728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
729 AXE_SW_RESET_IPRL, NULL);
730 uether_pause(&sc->sc_ue, hz / 4);
731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
732 uether_pause(&sc->sc_ue, hz);
733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
734 uether_pause(&sc->sc_ue, hz / 32);
735 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
736 uether_pause(&sc->sc_ue, hz / 32);
737 }
738
739 static void
axe_ax88772a_init(struct axe_softc * sc)740 axe_ax88772a_init(struct axe_softc *sc)
741 {
742 struct usb_ether *ue;
743
744 ue = &sc->sc_ue;
745 /* Reload EEPROM. */
746 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
747 axe_ax88772_phywake(sc);
748 /* Stop MAC. */
749 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
750 }
751
752 static void
axe_ax88772b_init(struct axe_softc * sc)753 axe_ax88772b_init(struct axe_softc *sc)
754 {
755 struct usb_ether *ue;
756 uint16_t eeprom;
757 uint8_t *eaddr;
758 int i;
759
760 ue = &sc->sc_ue;
761 /* Reload EEPROM. */
762 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
763 /*
764 * Save PHY power saving configuration(high byte) and
765 * clear EEPROM checksum value(low byte).
766 */
767 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
768 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
769
770 /*
771 * Auto-loaded default station address from internal ROM is
772 * 00:00:00:00:00:00 such that an explicit access to EEPROM
773 * is required to get real station address.
774 */
775 eaddr = ue->ue_eaddr;
776 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
777 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
778 &eeprom);
779 eeprom = le16toh(eeprom);
780 *eaddr++ = (uint8_t)(eeprom & 0xFF);
781 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
782 }
783 /* Wakeup PHY. */
784 axe_ax88772_phywake(sc);
785 /* Stop MAC. */
786 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
787 }
788
789 #undef AXE_GPIO_WRITE
790
791 static void
axe_reset(struct axe_softc * sc)792 axe_reset(struct axe_softc *sc)
793 {
794 struct usb_config_descriptor *cd;
795 usb_error_t err;
796
797 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
798
799 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
800 cd->bConfigurationValue);
801 if (err)
802 DPRINTF("reset failed (ignored)\n");
803
804 /* Wait a little while for the chip to get its brains in order. */
805 uether_pause(&sc->sc_ue, hz / 100);
806
807 /* Reinitialize controller to achieve full reset. */
808 if (sc->sc_flags & AXE_FLAG_178)
809 axe_ax88178_init(sc);
810 else if (sc->sc_flags & AXE_FLAG_772)
811 axe_ax88772_init(sc);
812 else if (sc->sc_flags & AXE_FLAG_772A)
813 axe_ax88772a_init(sc);
814 else if (sc->sc_flags & AXE_FLAG_772B)
815 axe_ax88772b_init(sc);
816 }
817
818 static void
axe_attach_post(struct usb_ether * ue)819 axe_attach_post(struct usb_ether *ue)
820 {
821 struct axe_softc *sc = uether_getsc(ue);
822
823 /*
824 * Load PHY indexes first. Needed by axe_xxx_init().
825 */
826 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
827 if (bootverbose)
828 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
829 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
830 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
831 if (sc->sc_phyno == -1)
832 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
833 if (sc->sc_phyno == -1) {
834 device_printf(sc->sc_ue.ue_dev,
835 "no valid PHY address found, assuming PHY address 0\n");
836 sc->sc_phyno = 0;
837 }
838
839 /* Initialize controller and get station address. */
840 if (sc->sc_flags & AXE_FLAG_178) {
841 axe_ax88178_init(sc);
842 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
843 } else if (sc->sc_flags & AXE_FLAG_772) {
844 axe_ax88772_init(sc);
845 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
846 } else if (sc->sc_flags & AXE_FLAG_772A) {
847 axe_ax88772a_init(sc);
848 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
849 } else if (sc->sc_flags & AXE_FLAG_772B) {
850 axe_ax88772b_init(sc);
851 } else
852 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
853
854 /*
855 * Fetch IPG values.
856 */
857 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
858 /* Set IPG values. */
859 sc->sc_ipgs[0] = 0x15;
860 sc->sc_ipgs[1] = 0x16;
861 sc->sc_ipgs[2] = 0x1A;
862 } else
863 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
864 }
865
866 static int
axe_attach_post_sub(struct usb_ether * ue)867 axe_attach_post_sub(struct usb_ether *ue)
868 {
869 struct axe_softc *sc;
870 struct ifnet *ifp;
871 u_int adv_pause;
872 int error;
873
874 sc = uether_getsc(ue);
875 ifp = ue->ue_ifp;
876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
877 ifp->if_start = uether_start;
878 ifp->if_ioctl = axe_ioctl;
879 ifp->if_init = uether_init;
880 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
881 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
882 IFQ_SET_READY(&ifp->if_snd);
883
884 if (AXE_IS_178_FAMILY(sc))
885 ifp->if_capabilities |= IFCAP_VLAN_MTU;
886 if (sc->sc_flags & AXE_FLAG_772B) {
887 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
888 ifp->if_hwassist = AXE_CSUM_FEATURES;
889 /*
890 * Checksum offloading of AX88772B also works with VLAN
891 * tagged frames but there is no way to take advantage
892 * of the feature because vlan(4) assumes
893 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
894 * support checksum offloading with VLAN. VLAN hardware
895 * tagging support of AX88772B is very limited so it's
896 * not possible to announce IFCAP_VLAN_HWTAGGING.
897 */
898 }
899 ifp->if_capenable = ifp->if_capabilities;
900 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
901 adv_pause = MIIF_DOPAUSE;
902 else
903 adv_pause = 0;
904 mtx_lock(&Giant);
905 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
906 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
907 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
908 mtx_unlock(&Giant);
909
910 return (error);
911 }
912
913 /*
914 * Probe for a AX88172 chip.
915 */
916 static int
axe_probe(device_t dev)917 axe_probe(device_t dev)
918 {
919 struct usb_attach_arg *uaa = device_get_ivars(dev);
920
921 if (uaa->usb_mode != USB_MODE_HOST)
922 return (ENXIO);
923 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
924 return (ENXIO);
925 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
926 return (ENXIO);
927
928 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
929 }
930
931 /*
932 * Attach the interface. Allocate softc structures, do ifmedia
933 * setup and ethernet/BPF attach.
934 */
935 static int
axe_attach(device_t dev)936 axe_attach(device_t dev)
937 {
938 struct usb_attach_arg *uaa = device_get_ivars(dev);
939 struct axe_softc *sc = device_get_softc(dev);
940 struct usb_ether *ue = &sc->sc_ue;
941 uint8_t iface_index;
942 int error;
943
944 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
945
946 device_set_usb_desc(dev);
947
948 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
949
950 iface_index = AXE_IFACE_IDX;
951 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
952 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
953 if (error) {
954 device_printf(dev, "allocating USB transfers failed\n");
955 goto detach;
956 }
957
958 ue->ue_sc = sc;
959 ue->ue_dev = dev;
960 ue->ue_udev = uaa->device;
961 ue->ue_mtx = &sc->sc_mtx;
962 ue->ue_methods = &axe_ue_methods;
963
964 error = uether_ifattach(ue);
965 if (error) {
966 device_printf(dev, "could not attach interface\n");
967 goto detach;
968 }
969 return (0); /* success */
970
971 detach:
972 axe_detach(dev);
973 return (ENXIO); /* failure */
974 }
975
976 static int
axe_detach(device_t dev)977 axe_detach(device_t dev)
978 {
979 struct axe_softc *sc = device_get_softc(dev);
980 struct usb_ether *ue = &sc->sc_ue;
981
982 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
983 uether_ifdetach(ue);
984 mtx_destroy(&sc->sc_mtx);
985
986 return (0);
987 }
988
989 #if (AXE_BULK_BUF_SIZE >= 0x10000)
990 #error "Please update axe_bulk_read_callback()!"
991 #endif
992
993 static void
axe_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)994 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
995 {
996 struct axe_softc *sc = usbd_xfer_softc(xfer);
997 struct usb_ether *ue = &sc->sc_ue;
998 struct usb_page_cache *pc;
999 int actlen;
1000
1001 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1002
1003 switch (USB_GET_STATE(xfer)) {
1004 case USB_ST_TRANSFERRED:
1005 pc = usbd_xfer_get_frame(xfer, 0);
1006 axe_rx_frame(ue, pc, actlen);
1007
1008 /* FALLTHROUGH */
1009 case USB_ST_SETUP:
1010 tr_setup:
1011 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1012 usbd_transfer_submit(xfer);
1013 uether_rxflush(ue);
1014 return;
1015
1016 default: /* Error */
1017 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1018
1019 if (error != USB_ERR_CANCELLED) {
1020 /* try to clear stall first */
1021 usbd_xfer_set_stall(xfer);
1022 goto tr_setup;
1023 }
1024 return;
1025 }
1026 }
1027
1028 static int
axe_rx_frame(struct usb_ether * ue,struct usb_page_cache * pc,int actlen)1029 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1030 {
1031 struct axe_softc *sc;
1032 struct axe_sframe_hdr hdr;
1033 struct axe_csum_hdr csum_hdr;
1034 int error, len, pos;
1035
1036 sc = uether_getsc(ue);
1037 pos = 0;
1038 len = 0;
1039 error = 0;
1040 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1041 while (pos < actlen) {
1042 if ((int)(pos + sizeof(hdr)) > actlen) {
1043 /* too little data */
1044 error = EINVAL;
1045 break;
1046 }
1047 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1048
1049 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1050 /* we lost sync */
1051 error = EINVAL;
1052 break;
1053 }
1054 pos += sizeof(hdr);
1055 len = le16toh(hdr.len);
1056 if (pos + len > actlen) {
1057 /* invalid length */
1058 error = EINVAL;
1059 break;
1060 }
1061 axe_rxeof(ue, pc, pos, len, NULL);
1062 pos += len + (len % 2);
1063 }
1064 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1065 while (pos < actlen) {
1066 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1067 /* too little data */
1068 error = EINVAL;
1069 break;
1070 }
1071 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1072
1073 csum_hdr.len = le16toh(csum_hdr.len);
1074 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1075 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1076 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1077 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1078 sc->sc_lenmask) {
1079 /* we lost sync */
1080 error = EINVAL;
1081 break;
1082 }
1083 /*
1084 * Get total transferred frame length including
1085 * checksum header. The length should be multiple
1086 * of 4.
1087 */
1088 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1089 len = (len + 3) & ~3;
1090 if (pos + len > actlen) {
1091 /* invalid length */
1092 error = EINVAL;
1093 break;
1094 }
1095 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1096 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1097 pos += len;
1098 }
1099 } else
1100 axe_rxeof(ue, pc, 0, actlen, NULL);
1101
1102 if (error != 0)
1103 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
1104 return (error);
1105 }
1106
1107 static int
axe_rxeof(struct usb_ether * ue,struct usb_page_cache * pc,unsigned int offset,unsigned int len,struct axe_csum_hdr * csum_hdr)1108 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1109 unsigned int len, struct axe_csum_hdr *csum_hdr)
1110 {
1111 struct ifnet *ifp = ue->ue_ifp;
1112 struct mbuf *m;
1113
1114 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1115 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1116 return (EINVAL);
1117 }
1118
1119 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1120 if (m == NULL) {
1121 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1122 return (ENOMEM);
1123 }
1124 m->m_len = m->m_pkthdr.len = MCLBYTES;
1125 m_adj(m, ETHER_ALIGN);
1126
1127 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1128
1129 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1130 m->m_pkthdr.rcvif = ifp;
1131 m->m_pkthdr.len = m->m_len = len;
1132
1133 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1134 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1135 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1136 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1137 CSUM_IP_VALID;
1138 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1139 AXE_CSUM_HDR_L4_TYPE_TCP ||
1140 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1141 AXE_CSUM_HDR_L4_TYPE_UDP) {
1142 m->m_pkthdr.csum_flags |=
1143 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1144 m->m_pkthdr.csum_data = 0xffff;
1145 }
1146 }
1147 }
1148
1149 (void)mbufq_enqueue(&ue->ue_rxq, m);
1150 return (0);
1151 }
1152
1153 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1154 #error "Please update axe_bulk_write_callback()!"
1155 #endif
1156
1157 static void
axe_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)1158 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1159 {
1160 struct axe_softc *sc = usbd_xfer_softc(xfer);
1161 struct axe_sframe_hdr hdr;
1162 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1163 struct usb_page_cache *pc;
1164 struct mbuf *m;
1165 int nframes, pos;
1166
1167 switch (USB_GET_STATE(xfer)) {
1168 case USB_ST_TRANSFERRED:
1169 DPRINTFN(11, "transfer complete\n");
1170 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1171 /* FALLTHROUGH */
1172 case USB_ST_SETUP:
1173 tr_setup:
1174 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1175 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1176 /*
1177 * Don't send anything if there is no link or
1178 * controller is busy.
1179 */
1180 return;
1181 }
1182
1183 for (nframes = 0; nframes < 16 &&
1184 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1185 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1186 if (m == NULL)
1187 break;
1188 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1189 nframes);
1190 pos = 0;
1191 pc = usbd_xfer_get_frame(xfer, nframes);
1192 if (AXE_IS_178_FAMILY(sc)) {
1193 hdr.len = htole16(m->m_pkthdr.len);
1194 hdr.ilen = ~hdr.len;
1195 /*
1196 * If upper stack computed checksum, driver
1197 * should tell controller not to insert
1198 * computed checksum for checksum offloading
1199 * enabled controller.
1200 */
1201 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1202 if ((m->m_pkthdr.csum_flags &
1203 AXE_CSUM_FEATURES) != 0)
1204 hdr.len |= htole16(
1205 AXE_TX_CSUM_PSEUDO_HDR);
1206 else
1207 hdr.len |= htole16(
1208 AXE_TX_CSUM_DIS);
1209 }
1210 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1211 pos += sizeof(hdr);
1212 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1213 pos += m->m_pkthdr.len;
1214 if ((pos % 512) == 0) {
1215 hdr.len = 0;
1216 hdr.ilen = 0xffff;
1217 usbd_copy_in(pc, pos, &hdr,
1218 sizeof(hdr));
1219 pos += sizeof(hdr);
1220 }
1221 } else {
1222 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1223 pos += m->m_pkthdr.len;
1224 }
1225
1226 /*
1227 * XXX
1228 * Update TX packet counter here. This is not
1229 * correct way but it seems that there is no way
1230 * to know how many packets are sent at the end
1231 * of transfer because controller combines
1232 * multiple writes into single one if there is
1233 * room in TX buffer of controller.
1234 */
1235 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1236
1237 /*
1238 * if there's a BPF listener, bounce a copy
1239 * of this frame to him:
1240 */
1241 BPF_MTAP(ifp, m);
1242
1243 m_freem(m);
1244
1245 /* Set frame length. */
1246 usbd_xfer_set_frame_len(xfer, nframes, pos);
1247 }
1248 if (nframes != 0) {
1249 usbd_xfer_set_frames(xfer, nframes);
1250 usbd_transfer_submit(xfer);
1251 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1252 }
1253 return;
1254 /* NOTREACHED */
1255 default: /* Error */
1256 DPRINTFN(11, "transfer error, %s\n",
1257 usbd_errstr(error));
1258
1259 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1260 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1261
1262 if (error != USB_ERR_CANCELLED) {
1263 /* try to clear stall first */
1264 usbd_xfer_set_stall(xfer);
1265 goto tr_setup;
1266 }
1267 return;
1268 }
1269 }
1270
1271 static void
axe_tick(struct usb_ether * ue)1272 axe_tick(struct usb_ether *ue)
1273 {
1274 struct axe_softc *sc = uether_getsc(ue);
1275 struct mii_data *mii = GET_MII(sc);
1276
1277 AXE_LOCK_ASSERT(sc, MA_OWNED);
1278
1279 mii_tick(mii);
1280 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1281 axe_miibus_statchg(ue->ue_dev);
1282 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1283 axe_start(ue);
1284 }
1285 }
1286
1287 static void
axe_start(struct usb_ether * ue)1288 axe_start(struct usb_ether *ue)
1289 {
1290 struct axe_softc *sc = uether_getsc(ue);
1291
1292 /*
1293 * start the USB transfers, if not already started:
1294 */
1295 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1296 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1297 }
1298
1299 static void
axe_csum_cfg(struct usb_ether * ue)1300 axe_csum_cfg(struct usb_ether *ue)
1301 {
1302 struct axe_softc *sc;
1303 struct ifnet *ifp;
1304 uint16_t csum1, csum2;
1305
1306 sc = uether_getsc(ue);
1307 AXE_LOCK_ASSERT(sc, MA_OWNED);
1308
1309 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1310 ifp = uether_getifp(ue);
1311 csum1 = 0;
1312 csum2 = 0;
1313 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1314 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1315 AXE_TXCSUM_UDP;
1316 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1317 csum1 = 0;
1318 csum2 = 0;
1319 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1320 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1321 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1322 AXE_RXCSUM_IGMP;
1323 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1324 }
1325 }
1326
1327 static void
axe_init(struct usb_ether * ue)1328 axe_init(struct usb_ether *ue)
1329 {
1330 struct axe_softc *sc = uether_getsc(ue);
1331 struct ifnet *ifp = uether_getifp(ue);
1332 uint16_t rxmode;
1333
1334 AXE_LOCK_ASSERT(sc, MA_OWNED);
1335
1336 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1337 return;
1338
1339 /* Cancel pending I/O */
1340 axe_stop(ue);
1341
1342 axe_reset(sc);
1343
1344 /* Set MAC address and transmitter IPG values. */
1345 if (AXE_IS_178_FAMILY(sc)) {
1346 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1347 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1348 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1349 } else {
1350 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1351 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1352 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1353 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1354 }
1355
1356 if (AXE_IS_178_FAMILY(sc)) {
1357 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1358 if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1359 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1360 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1361 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1362 } else {
1363 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1364 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1365 }
1366 }
1367
1368 /* Configure TX/RX checksum offloading. */
1369 axe_csum_cfg(ue);
1370
1371 if (sc->sc_flags & AXE_FLAG_772B) {
1372 /* AX88772B uses different maximum frame burst configuration. */
1373 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1374 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1375 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1376 }
1377
1378 /* Enable receiver, set RX mode. */
1379 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1380 if (AXE_IS_178_FAMILY(sc)) {
1381 if (sc->sc_flags & AXE_FLAG_772B) {
1382 /*
1383 * Select RX header format type 1. Aligning IP
1384 * header on 4 byte boundary is not needed when
1385 * checksum offloading feature is not used
1386 * because we always copy the received frame in
1387 * RX handler. When RX checksum offloading is
1388 * active, aligning IP header is required to
1389 * reflect actual frame length including RX
1390 * header size.
1391 */
1392 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1393 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1394 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1395 } else {
1396 /*
1397 * Default Rx buffer size is too small to get
1398 * maximum performance.
1399 */
1400 rxmode |= AXE_178_RXCMD_MFB_16384;
1401 }
1402 } else {
1403 rxmode |= AXE_172_RXCMD_UNICAST;
1404 }
1405
1406 /* If we want promiscuous mode, set the allframes bit. */
1407 if (ifp->if_flags & IFF_PROMISC)
1408 rxmode |= AXE_RXCMD_PROMISC;
1409
1410 if (ifp->if_flags & IFF_BROADCAST)
1411 rxmode |= AXE_RXCMD_BROADCAST;
1412
1413 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1414
1415 /* Load the multicast filter. */
1416 axe_setmulti(ue);
1417
1418 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1419
1420 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1421 /* Switch to selected media. */
1422 axe_ifmedia_upd(ifp);
1423 }
1424
1425 static void
axe_setpromisc(struct usb_ether * ue)1426 axe_setpromisc(struct usb_ether *ue)
1427 {
1428 struct axe_softc *sc = uether_getsc(ue);
1429 struct ifnet *ifp = uether_getifp(ue);
1430 uint16_t rxmode;
1431
1432 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1433
1434 rxmode = le16toh(rxmode);
1435
1436 if (ifp->if_flags & IFF_PROMISC) {
1437 rxmode |= AXE_RXCMD_PROMISC;
1438 } else {
1439 rxmode &= ~AXE_RXCMD_PROMISC;
1440 }
1441
1442 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1443
1444 axe_setmulti(ue);
1445 }
1446
1447 static void
axe_stop(struct usb_ether * ue)1448 axe_stop(struct usb_ether *ue)
1449 {
1450 struct axe_softc *sc = uether_getsc(ue);
1451 struct ifnet *ifp = uether_getifp(ue);
1452
1453 AXE_LOCK_ASSERT(sc, MA_OWNED);
1454
1455 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1456 sc->sc_flags &= ~AXE_FLAG_LINK;
1457
1458 /*
1459 * stop all the transfers, if not already stopped:
1460 */
1461 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1462 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1463 }
1464
1465 static int
axe_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1466 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1467 {
1468 struct usb_ether *ue = ifp->if_softc;
1469 struct axe_softc *sc;
1470 struct ifreq *ifr;
1471 int error, mask, reinit;
1472
1473 sc = uether_getsc(ue);
1474 ifr = (struct ifreq *)data;
1475 error = 0;
1476 reinit = 0;
1477 if (cmd == SIOCSIFCAP) {
1478 AXE_LOCK(sc);
1479 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1480 if ((mask & IFCAP_TXCSUM) != 0 &&
1481 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1482 ifp->if_capenable ^= IFCAP_TXCSUM;
1483 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1484 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1485 else
1486 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1487 reinit++;
1488 }
1489 if ((mask & IFCAP_RXCSUM) != 0 &&
1490 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1491 ifp->if_capenable ^= IFCAP_RXCSUM;
1492 reinit++;
1493 }
1494 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1496 else
1497 reinit = 0;
1498 AXE_UNLOCK(sc);
1499 if (reinit > 0)
1500 uether_init(ue);
1501 } else
1502 error = uether_ioctl(ifp, cmd, data);
1503
1504 return (error);
1505 }
1506