1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR atmegadci_debug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/atmegadci.h> 80 81 #define ATMEGA_BUS2SC(bus) \ 82 __containerof(bus, struct atmegadci_softc, sc_bus) 83 84 #define ATMEGA_PC2SC(pc) \ 85 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 86 87 #ifdef USB_DEBUG 88 static int atmegadci_debug = 0; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 91 "USB ATMEGA DCI"); 92 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 93 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 94 #endif 95 96 #define ATMEGA_INTR_ENDPT 1 97 98 /* prototypes */ 99 100 static const struct usb_bus_methods atmegadci_bus_methods; 101 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 102 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 103 104 static atmegadci_cmd_t atmegadci_setup_rx; 105 static atmegadci_cmd_t atmegadci_data_rx; 106 static atmegadci_cmd_t atmegadci_data_tx; 107 static atmegadci_cmd_t atmegadci_data_tx_sync; 108 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 109 static void atmegadci_do_poll(struct usb_bus *); 110 static void atmegadci_standard_done(struct usb_xfer *); 111 static void atmegadci_root_intr(struct atmegadci_softc *sc); 112 113 /* 114 * Here is a list of what the chip supports: 115 */ 116 static const struct usb_hw_ep_profile 117 atmegadci_ep_profile[2] = { 118 [0] = { 119 .max_in_frame_size = 64, 120 .max_out_frame_size = 64, 121 .is_simplex = 1, 122 .support_control = 1, 123 }, 124 [1] = { 125 .max_in_frame_size = 64, 126 .max_out_frame_size = 64, 127 .is_simplex = 1, 128 .support_bulk = 1, 129 .support_interrupt = 1, 130 .support_isochronous = 1, 131 .support_in = 1, 132 .support_out = 1, 133 }, 134 }; 135 136 static void 137 atmegadci_get_hw_ep_profile(struct usb_device *udev, 138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 139 { 140 if (ep_addr == 0) 141 *ppf = atmegadci_ep_profile; 142 else if (ep_addr < ATMEGA_EP_MAX) 143 *ppf = atmegadci_ep_profile + 1; 144 else 145 *ppf = NULL; 146 } 147 148 static void 149 atmegadci_clocks_on(struct atmegadci_softc *sc) 150 { 151 if (sc->sc_flags.clocks_off && 152 sc->sc_flags.port_powered) { 153 DPRINTFN(5, "\n"); 154 155 /* turn on clocks */ 156 (sc->sc_clocks_on) (&sc->sc_bus); 157 158 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 159 ATMEGA_USBCON_USBE | 160 ATMEGA_USBCON_OTGPADE | 161 ATMEGA_USBCON_VBUSTE); 162 163 sc->sc_flags.clocks_off = 0; 164 165 /* enable transceiver ? */ 166 } 167 } 168 169 static void 170 atmegadci_clocks_off(struct atmegadci_softc *sc) 171 { 172 if (!sc->sc_flags.clocks_off) { 173 DPRINTFN(5, "\n"); 174 175 /* disable Transceiver ? */ 176 177 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 178 ATMEGA_USBCON_USBE | 179 ATMEGA_USBCON_OTGPADE | 180 ATMEGA_USBCON_FRZCLK | 181 ATMEGA_USBCON_VBUSTE); 182 183 /* turn clocks off */ 184 (sc->sc_clocks_off) (&sc->sc_bus); 185 186 sc->sc_flags.clocks_off = 1; 187 } 188 } 189 190 static void 191 atmegadci_pull_up(struct atmegadci_softc *sc) 192 { 193 /* pullup D+, if possible */ 194 195 if (!sc->sc_flags.d_pulled_up && 196 sc->sc_flags.port_powered) { 197 sc->sc_flags.d_pulled_up = 1; 198 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 199 } 200 } 201 202 static void 203 atmegadci_pull_down(struct atmegadci_softc *sc) 204 { 205 /* pulldown D+, if possible */ 206 207 if (sc->sc_flags.d_pulled_up) { 208 sc->sc_flags.d_pulled_up = 0; 209 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 210 } 211 } 212 213 static void 214 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 215 { 216 uint8_t temp; 217 218 if (!sc->sc_flags.status_suspend) { 219 return; 220 } 221 222 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 223 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 224 225 /* wait 8 milliseconds */ 226 /* Wait for reset to complete. */ 227 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 228 229 /* hardware should have cleared RMWKUP bit */ 230 } 231 232 static void 233 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 234 { 235 DPRINTFN(5, "addr=%d\n", addr); 236 237 addr |= ATMEGA_UDADDR_ADDEN; 238 239 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 240 } 241 242 static uint8_t 243 atmegadci_setup_rx(struct atmegadci_td *td) 244 { 245 struct atmegadci_softc *sc; 246 struct usb_device_request req; 247 uint16_t count; 248 uint8_t temp; 249 250 /* get pointer to softc */ 251 sc = ATMEGA_PC2SC(td->pc); 252 253 /* select endpoint number */ 254 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 255 256 /* check endpoint status */ 257 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 258 259 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 260 261 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 262 goto not_complete; 263 } 264 /* clear did stall */ 265 td->did_stall = 0; 266 /* get the packet byte count */ 267 count = 268 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 269 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 270 271 /* mask away undefined bits */ 272 count &= 0x7FF; 273 274 /* verify data length */ 275 if (count != td->remainder) { 276 DPRINTFN(0, "Invalid SETUP packet " 277 "length, %d bytes\n", count); 278 goto not_complete; 279 } 280 if (count != sizeof(req)) { 281 DPRINTFN(0, "Unsupported SETUP packet " 282 "length, %d bytes\n", count); 283 goto not_complete; 284 } 285 /* receive data */ 286 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 287 (void *)&req, sizeof(req)); 288 289 /* copy data into real buffer */ 290 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 291 292 td->offset = sizeof(req); 293 td->remainder = 0; 294 295 /* sneak peek the set address */ 296 if ((req.bmRequestType == UT_WRITE_DEVICE) && 297 (req.bRequest == UR_SET_ADDRESS)) { 298 sc->sc_dv_addr = req.wValue[0] & 0x7F; 299 /* must write address before ZLP */ 300 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 301 } else { 302 sc->sc_dv_addr = 0xFF; 303 } 304 305 /* Clear SETUP packet interrupt and all other previous interrupts */ 306 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 307 return (0); /* complete */ 308 309 not_complete: 310 /* abort any ongoing transfer */ 311 if (!td->did_stall) { 312 DPRINTFN(5, "stalling\n"); 313 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 314 ATMEGA_UECONX_EPEN | 315 ATMEGA_UECONX_STALLRQ); 316 td->did_stall = 1; 317 } 318 if (temp & ATMEGA_UEINTX_RXSTPI) { 319 /* clear SETUP packet interrupt */ 320 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 321 } 322 /* we only want to know if there is a SETUP packet */ 323 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 324 return (1); /* not complete */ 325 } 326 327 static uint8_t 328 atmegadci_data_rx(struct atmegadci_td *td) 329 { 330 struct atmegadci_softc *sc; 331 struct usb_page_search buf_res; 332 uint16_t count; 333 uint8_t temp; 334 uint8_t to; 335 uint8_t got_short; 336 337 to = 3; /* don't loop forever! */ 338 got_short = 0; 339 340 /* get pointer to softc */ 341 sc = ATMEGA_PC2SC(td->pc); 342 343 /* select endpoint number */ 344 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 345 346 repeat: 347 /* check if any of the FIFO banks have data */ 348 /* check endpoint status */ 349 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 350 351 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 352 353 if (temp & ATMEGA_UEINTX_RXSTPI) { 354 if (td->remainder == 0) { 355 /* 356 * We are actually complete and have 357 * received the next SETUP 358 */ 359 DPRINTFN(5, "faking complete\n"); 360 return (0); /* complete */ 361 } 362 /* 363 * USB Host Aborted the transfer. 364 */ 365 td->error = 1; 366 return (0); /* complete */ 367 } 368 /* check status */ 369 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 370 ATMEGA_UEINTX_RXOUTI))) { 371 /* no data */ 372 goto not_complete; 373 } 374 /* get the packet byte count */ 375 count = 376 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 377 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 378 379 /* mask away undefined bits */ 380 count &= 0x7FF; 381 382 /* verify the packet byte count */ 383 if (count != td->max_packet_size) { 384 if (count < td->max_packet_size) { 385 /* we have a short packet */ 386 td->short_pkt = 1; 387 got_short = 1; 388 } else { 389 /* invalid USB packet */ 390 td->error = 1; 391 return (0); /* we are complete */ 392 } 393 } 394 /* verify the packet byte count */ 395 if (count > td->remainder) { 396 /* invalid USB packet */ 397 td->error = 1; 398 return (0); /* we are complete */ 399 } 400 while (count > 0) { 401 usbd_get_page(td->pc, td->offset, &buf_res); 402 403 /* get correct length */ 404 if (buf_res.length > count) { 405 buf_res.length = count; 406 } 407 /* receive data */ 408 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 409 buf_res.buffer, buf_res.length); 410 411 /* update counters */ 412 count -= buf_res.length; 413 td->offset += buf_res.length; 414 td->remainder -= buf_res.length; 415 } 416 417 /* clear OUT packet interrupt */ 418 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 419 420 /* release FIFO bank */ 421 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 422 423 /* check if we are complete */ 424 if ((td->remainder == 0) || got_short) { 425 if (td->short_pkt) { 426 /* we are complete */ 427 return (0); 428 } 429 /* else need to receive a zero length packet */ 430 } 431 if (--to) { 432 goto repeat; 433 } 434 not_complete: 435 /* we only want to know if there is a SETUP packet or OUT packet */ 436 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 437 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 438 return (1); /* not complete */ 439 } 440 441 static uint8_t 442 atmegadci_data_tx(struct atmegadci_td *td) 443 { 444 struct atmegadci_softc *sc; 445 struct usb_page_search buf_res; 446 uint16_t count; 447 uint8_t to; 448 uint8_t temp; 449 450 to = 3; /* don't loop forever! */ 451 452 /* get pointer to softc */ 453 sc = ATMEGA_PC2SC(td->pc); 454 455 /* select endpoint number */ 456 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 457 458 repeat: 459 460 /* check endpoint status */ 461 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 462 463 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 464 465 if (temp & ATMEGA_UEINTX_RXSTPI) { 466 /* 467 * The current transfer was aborted 468 * by the USB Host 469 */ 470 td->error = 1; 471 return (0); /* complete */ 472 } 473 474 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 475 if (temp & 3) { 476 /* cannot write any data - a bank is busy */ 477 goto not_complete; 478 } 479 480 count = td->max_packet_size; 481 if (td->remainder < count) { 482 /* we have a short packet */ 483 td->short_pkt = 1; 484 count = td->remainder; 485 } 486 while (count > 0) { 487 usbd_get_page(td->pc, td->offset, &buf_res); 488 489 /* get correct length */ 490 if (buf_res.length > count) { 491 buf_res.length = count; 492 } 493 /* transmit data */ 494 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 495 buf_res.buffer, buf_res.length); 496 497 /* update counters */ 498 count -= buf_res.length; 499 td->offset += buf_res.length; 500 td->remainder -= buf_res.length; 501 } 502 503 /* clear IN packet interrupt */ 504 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 505 506 /* allocate FIFO bank */ 507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 508 509 /* check remainder */ 510 if (td->remainder == 0) { 511 if (td->short_pkt) { 512 return (0); /* complete */ 513 } 514 /* else we need to transmit a short packet */ 515 } 516 if (--to) { 517 goto repeat; 518 } 519 not_complete: 520 /* we only want to know if there is a SETUP packet or free IN packet */ 521 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 522 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 523 return (1); /* not complete */ 524 } 525 526 static uint8_t 527 atmegadci_data_tx_sync(struct atmegadci_td *td) 528 { 529 struct atmegadci_softc *sc; 530 uint8_t temp; 531 532 /* get pointer to softc */ 533 sc = ATMEGA_PC2SC(td->pc); 534 535 /* select endpoint number */ 536 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 537 538 /* check endpoint status */ 539 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 540 541 DPRINTFN(5, "temp=0x%02x\n", temp); 542 543 if (temp & ATMEGA_UEINTX_RXSTPI) { 544 DPRINTFN(5, "faking complete\n"); 545 /* Race condition */ 546 return (0); /* complete */ 547 } 548 /* 549 * The control endpoint has only got one bank, so if that bank 550 * is free the packet has been transferred! 551 */ 552 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 553 if (temp & 3) { 554 /* cannot write any data - a bank is busy */ 555 goto not_complete; 556 } 557 if (sc->sc_dv_addr != 0xFF) { 558 /* set new address */ 559 atmegadci_set_address(sc, sc->sc_dv_addr); 560 } 561 return (0); /* complete */ 562 563 not_complete: 564 /* we only want to know if there is a SETUP packet or free IN packet */ 565 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 566 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 567 return (1); /* not complete */ 568 } 569 570 static uint8_t 571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 572 { 573 struct atmegadci_td *td; 574 575 DPRINTFN(9, "\n"); 576 577 td = xfer->td_transfer_cache; 578 while (1) { 579 if ((td->func) (td)) { 580 /* operation in progress */ 581 break; 582 } 583 if (((void *)td) == xfer->td_transfer_last) { 584 goto done; 585 } 586 if (td->error) { 587 goto done; 588 } else if (td->remainder > 0) { 589 /* 590 * We had a short transfer. If there is no alternate 591 * next, stop processing ! 592 */ 593 if (!td->alt_next) { 594 goto done; 595 } 596 } 597 /* 598 * Fetch the next transfer descriptor and transfer 599 * some flags to the next transfer descriptor 600 */ 601 td = td->obj_next; 602 xfer->td_transfer_cache = td; 603 } 604 return (1); /* not complete */ 605 606 done: 607 /* compute all actual lengths */ 608 609 atmegadci_standard_done(xfer); 610 return (0); /* complete */ 611 } 612 613 static void 614 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 615 { 616 struct usb_xfer *xfer; 617 618 repeat: 619 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 620 if (!atmegadci_xfer_do_fifo(xfer)) { 621 /* queue has been modified */ 622 goto repeat; 623 } 624 } 625 } 626 627 static void 628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 629 { 630 DPRINTFN(5, "vbus = %u\n", is_on); 631 632 if (is_on) { 633 if (!sc->sc_flags.status_vbus) { 634 sc->sc_flags.status_vbus = 1; 635 636 /* complete root HUB interrupt endpoint */ 637 638 atmegadci_root_intr(sc); 639 } 640 } else { 641 if (sc->sc_flags.status_vbus) { 642 sc->sc_flags.status_vbus = 0; 643 sc->sc_flags.status_bus_reset = 0; 644 sc->sc_flags.status_suspend = 0; 645 sc->sc_flags.change_suspend = 0; 646 sc->sc_flags.change_connect = 1; 647 648 /* complete root HUB interrupt endpoint */ 649 650 atmegadci_root_intr(sc); 651 } 652 } 653 } 654 655 void 656 atmegadci_interrupt(struct atmegadci_softc *sc) 657 { 658 uint8_t status; 659 660 USB_BUS_LOCK(&sc->sc_bus); 661 662 /* read interrupt status */ 663 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 664 665 /* clear all set interrupts */ 666 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 667 668 DPRINTFN(14, "UDINT=0x%02x\n", status); 669 670 /* check for any bus state change interrupts */ 671 if (status & ATMEGA_UDINT_EORSTI) { 672 DPRINTFN(5, "end of reset\n"); 673 674 /* set correct state */ 675 sc->sc_flags.status_bus_reset = 1; 676 sc->sc_flags.status_suspend = 0; 677 sc->sc_flags.change_suspend = 0; 678 sc->sc_flags.change_connect = 1; 679 680 /* disable resume interrupt */ 681 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 682 ATMEGA_UDINT_SUSPE | 683 ATMEGA_UDINT_EORSTE); 684 685 /* complete root HUB interrupt endpoint */ 686 atmegadci_root_intr(sc); 687 } 688 /* 689 * If resume and suspend is set at the same time we interpret 690 * that like RESUME. Resume is set when there is at least 3 691 * milliseconds of inactivity on the USB BUS. 692 */ 693 if (status & ATMEGA_UDINT_WAKEUPI) { 694 DPRINTFN(5, "resume interrupt\n"); 695 696 if (sc->sc_flags.status_suspend) { 697 /* update status bits */ 698 sc->sc_flags.status_suspend = 0; 699 sc->sc_flags.change_suspend = 1; 700 701 /* disable resume interrupt */ 702 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 703 ATMEGA_UDINT_SUSPE | 704 ATMEGA_UDINT_EORSTE); 705 706 /* complete root HUB interrupt endpoint */ 707 atmegadci_root_intr(sc); 708 } 709 } else if (status & ATMEGA_UDINT_SUSPI) { 710 DPRINTFN(5, "suspend interrupt\n"); 711 712 if (!sc->sc_flags.status_suspend) { 713 /* update status bits */ 714 sc->sc_flags.status_suspend = 1; 715 sc->sc_flags.change_suspend = 1; 716 717 /* disable suspend interrupt */ 718 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 719 ATMEGA_UDINT_WAKEUPE | 720 ATMEGA_UDINT_EORSTE); 721 722 /* complete root HUB interrupt endpoint */ 723 atmegadci_root_intr(sc); 724 } 725 } 726 /* check VBUS */ 727 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 728 729 /* clear all set interrupts */ 730 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 731 732 if (status & ATMEGA_USBINT_VBUSTI) { 733 uint8_t temp; 734 735 DPRINTFN(5, "USBINT=0x%02x\n", status); 736 737 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 738 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 739 } 740 /* check for any endpoint interrupts */ 741 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 742 /* the hardware will clear the UEINT bits automatically */ 743 if (status) { 744 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 745 746 atmegadci_interrupt_poll(sc); 747 } 748 USB_BUS_UNLOCK(&sc->sc_bus); 749 } 750 751 static void 752 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 753 { 754 struct atmegadci_td *td; 755 756 /* get current Transfer Descriptor */ 757 td = temp->td_next; 758 temp->td = td; 759 760 /* prepare for next TD */ 761 temp->td_next = td->obj_next; 762 763 /* fill out the Transfer Descriptor */ 764 td->func = temp->func; 765 td->pc = temp->pc; 766 td->offset = temp->offset; 767 td->remainder = temp->len; 768 td->error = 0; 769 td->did_stall = temp->did_stall; 770 td->short_pkt = temp->short_pkt; 771 td->alt_next = temp->setup_alt_next; 772 } 773 774 static void 775 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 776 { 777 struct atmegadci_std_temp temp; 778 struct atmegadci_softc *sc; 779 struct atmegadci_td *td; 780 uint32_t x; 781 uint8_t ep_no; 782 uint8_t need_sync; 783 784 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 785 xfer->address, UE_GET_ADDR(xfer->endpointno), 786 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 787 788 temp.max_frame_size = xfer->max_frame_size; 789 790 td = xfer->td_start[0]; 791 xfer->td_transfer_first = td; 792 xfer->td_transfer_cache = td; 793 794 /* setup temp */ 795 796 temp.pc = NULL; 797 temp.td = NULL; 798 temp.td_next = xfer->td_start[0]; 799 temp.offset = 0; 800 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 801 xfer->flags_int.isochronous_xfr; 802 temp.did_stall = !xfer->flags_int.control_stall; 803 804 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 805 ep_no = (xfer->endpointno & UE_ADDR); 806 807 /* check if we should prepend a setup message */ 808 809 if (xfer->flags_int.control_xfr) { 810 if (xfer->flags_int.control_hdr) { 811 temp.func = &atmegadci_setup_rx; 812 temp.len = xfer->frlengths[0]; 813 temp.pc = xfer->frbuffers + 0; 814 temp.short_pkt = temp.len ? 1 : 0; 815 /* check for last frame */ 816 if (xfer->nframes == 1) { 817 /* no STATUS stage yet, SETUP is last */ 818 if (xfer->flags_int.control_act) 819 temp.setup_alt_next = 0; 820 } 821 822 atmegadci_setup_standard_chain_sub(&temp); 823 } 824 x = 1; 825 } else { 826 x = 0; 827 } 828 829 if (x != xfer->nframes) { 830 if (xfer->endpointno & UE_DIR_IN) { 831 temp.func = &atmegadci_data_tx; 832 need_sync = 1; 833 } else { 834 temp.func = &atmegadci_data_rx; 835 need_sync = 0; 836 } 837 838 /* setup "pc" pointer */ 839 temp.pc = xfer->frbuffers + x; 840 } else { 841 need_sync = 0; 842 } 843 while (x != xfer->nframes) { 844 /* DATA0 / DATA1 message */ 845 846 temp.len = xfer->frlengths[x]; 847 848 x++; 849 850 if (x == xfer->nframes) { 851 if (xfer->flags_int.control_xfr) { 852 if (xfer->flags_int.control_act) { 853 temp.setup_alt_next = 0; 854 } 855 } else { 856 temp.setup_alt_next = 0; 857 } 858 } 859 if (temp.len == 0) { 860 /* make sure that we send an USB packet */ 861 862 temp.short_pkt = 0; 863 864 } else { 865 /* regular data transfer */ 866 867 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 868 } 869 870 atmegadci_setup_standard_chain_sub(&temp); 871 872 if (xfer->flags_int.isochronous_xfr) { 873 temp.offset += temp.len; 874 } else { 875 /* get next Page Cache pointer */ 876 temp.pc = xfer->frbuffers + x; 877 } 878 } 879 880 if (xfer->flags_int.control_xfr) { 881 /* always setup a valid "pc" pointer for status and sync */ 882 temp.pc = xfer->frbuffers + 0; 883 temp.len = 0; 884 temp.short_pkt = 0; 885 temp.setup_alt_next = 0; 886 887 /* check if we need to sync */ 888 if (need_sync) { 889 /* we need a SYNC point after TX */ 890 temp.func = &atmegadci_data_tx_sync; 891 atmegadci_setup_standard_chain_sub(&temp); 892 } 893 894 /* check if we should append a status stage */ 895 if (!xfer->flags_int.control_act) { 896 /* 897 * Send a DATA1 message and invert the current 898 * endpoint direction. 899 */ 900 if (xfer->endpointno & UE_DIR_IN) { 901 temp.func = &atmegadci_data_rx; 902 need_sync = 0; 903 } else { 904 temp.func = &atmegadci_data_tx; 905 need_sync = 1; 906 } 907 908 atmegadci_setup_standard_chain_sub(&temp); 909 if (need_sync) { 910 /* we need a SYNC point after TX */ 911 temp.func = &atmegadci_data_tx_sync; 912 atmegadci_setup_standard_chain_sub(&temp); 913 } 914 } 915 } 916 /* must have at least one frame! */ 917 td = temp.td; 918 xfer->td_transfer_last = td; 919 } 920 921 static void 922 atmegadci_timeout(void *arg) 923 { 924 struct usb_xfer *xfer = arg; 925 926 DPRINTF("xfer=%p\n", xfer); 927 928 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 929 930 /* transfer is transferred */ 931 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 932 } 933 934 static void 935 atmegadci_start_standard_chain(struct usb_xfer *xfer) 936 { 937 DPRINTFN(9, "\n"); 938 939 /* poll one time - will turn on interrupts */ 940 if (atmegadci_xfer_do_fifo(xfer)) { 941 /* put transfer on interrupt queue */ 942 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 943 944 /* start timeout, if any */ 945 if (xfer->timeout != 0) { 946 usbd_transfer_timeout_ms(xfer, 947 &atmegadci_timeout, xfer->timeout); 948 } 949 } 950 } 951 952 static void 953 atmegadci_root_intr(struct atmegadci_softc *sc) 954 { 955 DPRINTFN(9, "\n"); 956 957 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 958 959 /* set port bit */ 960 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 961 962 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 963 sizeof(sc->sc_hub_idata)); 964 } 965 966 static usb_error_t 967 atmegadci_standard_done_sub(struct usb_xfer *xfer) 968 { 969 struct atmegadci_td *td; 970 uint32_t len; 971 uint8_t error; 972 973 DPRINTFN(9, "\n"); 974 975 td = xfer->td_transfer_cache; 976 977 do { 978 len = td->remainder; 979 980 if (xfer->aframes != xfer->nframes) { 981 /* 982 * Verify the length and subtract 983 * the remainder from "frlengths[]": 984 */ 985 if (len > xfer->frlengths[xfer->aframes]) { 986 td->error = 1; 987 } else { 988 xfer->frlengths[xfer->aframes] -= len; 989 } 990 } 991 /* Check for transfer error */ 992 if (td->error) { 993 /* the transfer is finished */ 994 error = 1; 995 td = NULL; 996 break; 997 } 998 /* Check for short transfer */ 999 if (len > 0) { 1000 if (xfer->flags_int.short_frames_ok || 1001 xfer->flags_int.isochronous_xfr) { 1002 /* follow alt next */ 1003 if (td->alt_next) { 1004 td = td->obj_next; 1005 } else { 1006 td = NULL; 1007 } 1008 } else { 1009 /* the transfer is finished */ 1010 td = NULL; 1011 } 1012 error = 0; 1013 break; 1014 } 1015 td = td->obj_next; 1016 1017 /* this USB frame is complete */ 1018 error = 0; 1019 break; 1020 1021 } while (0); 1022 1023 /* update transfer cache */ 1024 1025 xfer->td_transfer_cache = td; 1026 1027 return (error ? 1028 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1029 } 1030 1031 static void 1032 atmegadci_standard_done(struct usb_xfer *xfer) 1033 { 1034 usb_error_t err = 0; 1035 1036 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1037 xfer, xfer->endpoint); 1038 1039 /* reset scanner */ 1040 1041 xfer->td_transfer_cache = xfer->td_transfer_first; 1042 1043 if (xfer->flags_int.control_xfr) { 1044 if (xfer->flags_int.control_hdr) { 1045 err = atmegadci_standard_done_sub(xfer); 1046 } 1047 xfer->aframes = 1; 1048 1049 if (xfer->td_transfer_cache == NULL) { 1050 goto done; 1051 } 1052 } 1053 while (xfer->aframes != xfer->nframes) { 1054 err = atmegadci_standard_done_sub(xfer); 1055 xfer->aframes++; 1056 1057 if (xfer->td_transfer_cache == NULL) { 1058 goto done; 1059 } 1060 } 1061 1062 if (xfer->flags_int.control_xfr && 1063 !xfer->flags_int.control_act) { 1064 err = atmegadci_standard_done_sub(xfer); 1065 } 1066 done: 1067 atmegadci_device_done(xfer, err); 1068 } 1069 1070 /*------------------------------------------------------------------------* 1071 * atmegadci_device_done 1072 * 1073 * NOTE: this function can be called more than one time on the 1074 * same USB transfer! 1075 *------------------------------------------------------------------------*/ 1076 static void 1077 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1078 { 1079 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1080 uint8_t ep_no; 1081 1082 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1083 1084 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1085 xfer, xfer->endpoint, error); 1086 1087 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1088 ep_no = (xfer->endpointno & UE_ADDR); 1089 1090 /* select endpoint number */ 1091 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1092 1093 /* disable endpoint interrupt */ 1094 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1095 1096 DPRINTFN(15, "disabled interrupts!\n"); 1097 } 1098 /* dequeue transfer and start next transfer */ 1099 usbd_transfer_done(xfer, error); 1100 } 1101 1102 static void 1103 atmegadci_xfer_stall(struct usb_xfer *xfer) 1104 { 1105 atmegadci_device_done(xfer, USB_ERR_STALLED); 1106 } 1107 1108 static void 1109 atmegadci_set_stall(struct usb_device *udev, 1110 struct usb_endpoint *ep, uint8_t *did_stall) 1111 { 1112 struct atmegadci_softc *sc; 1113 uint8_t ep_no; 1114 1115 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1116 1117 DPRINTFN(5, "endpoint=%p\n", ep); 1118 1119 sc = ATMEGA_BUS2SC(udev->bus); 1120 /* get endpoint number */ 1121 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1122 /* select endpoint number */ 1123 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1124 /* set stall */ 1125 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1126 ATMEGA_UECONX_EPEN | 1127 ATMEGA_UECONX_STALLRQ); 1128 } 1129 1130 static void 1131 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1132 uint8_t ep_type, uint8_t ep_dir) 1133 { 1134 uint8_t temp; 1135 1136 if (ep_type == UE_CONTROL) { 1137 /* clearing stall is not needed */ 1138 return; 1139 } 1140 /* select endpoint number */ 1141 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1142 1143 /* set endpoint reset */ 1144 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1145 1146 /* clear endpoint reset */ 1147 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1148 1149 /* set stall */ 1150 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1151 ATMEGA_UECONX_EPEN | 1152 ATMEGA_UECONX_STALLRQ); 1153 1154 /* reset data toggle */ 1155 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1156 ATMEGA_UECONX_EPEN | 1157 ATMEGA_UECONX_RSTDT); 1158 1159 /* clear stall */ 1160 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1161 ATMEGA_UECONX_EPEN | 1162 ATMEGA_UECONX_STALLRQC); 1163 1164 do { 1165 if (ep_type == UE_BULK) { 1166 temp = ATMEGA_UECFG0X_EPTYPE2; 1167 } else if (ep_type == UE_INTERRUPT) { 1168 temp = ATMEGA_UECFG0X_EPTYPE3; 1169 } else { 1170 temp = ATMEGA_UECFG0X_EPTYPE1; 1171 } 1172 if (ep_dir & UE_DIR_IN) { 1173 temp |= ATMEGA_UECFG0X_EPDIR; 1174 } 1175 /* two banks, 64-bytes wMaxPacket */ 1176 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1177 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1178 ATMEGA_UECFG1X_ALLOC | 1179 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1180 ATMEGA_UECFG1X_EPSIZE(3)); 1181 1182 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1183 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1184 device_printf(sc->sc_bus.bdev, 1185 "Chip rejected configuration\n"); 1186 } 1187 } while (0); 1188 } 1189 1190 static void 1191 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1192 { 1193 struct atmegadci_softc *sc; 1194 struct usb_endpoint_descriptor *ed; 1195 1196 DPRINTFN(5, "endpoint=%p\n", ep); 1197 1198 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1199 1200 /* check mode */ 1201 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1202 /* not supported */ 1203 return; 1204 } 1205 /* get softc */ 1206 sc = ATMEGA_BUS2SC(udev->bus); 1207 1208 /* get endpoint descriptor */ 1209 ed = ep->edesc; 1210 1211 /* reset endpoint */ 1212 atmegadci_clear_stall_sub(sc, 1213 (ed->bEndpointAddress & UE_ADDR), 1214 (ed->bmAttributes & UE_XFERTYPE), 1215 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1216 } 1217 1218 usb_error_t 1219 atmegadci_init(struct atmegadci_softc *sc) 1220 { 1221 uint8_t n; 1222 1223 DPRINTF("start\n"); 1224 1225 /* set up the bus structure */ 1226 sc->sc_bus.usbrev = USB_REV_1_1; 1227 sc->sc_bus.methods = &atmegadci_bus_methods; 1228 1229 USB_BUS_LOCK(&sc->sc_bus); 1230 1231 /* make sure USB is enabled */ 1232 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1233 ATMEGA_USBCON_USBE | 1234 ATMEGA_USBCON_FRZCLK); 1235 1236 /* enable USB PAD regulator */ 1237 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1238 ATMEGA_UHWCON_UVREGE | 1239 ATMEGA_UHWCON_UIMOD); 1240 1241 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1242 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1243 1244 /* wait for PLL to lock */ 1245 for (n = 0; n != 20; n++) { 1246 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1247 break; 1248 /* wait a little bit for PLL to start */ 1249 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1250 } 1251 1252 /* make sure USB is enabled */ 1253 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1254 ATMEGA_USBCON_USBE | 1255 ATMEGA_USBCON_OTGPADE | 1256 ATMEGA_USBCON_VBUSTE); 1257 1258 /* turn on clocks */ 1259 (sc->sc_clocks_on) (&sc->sc_bus); 1260 1261 /* make sure device is re-enumerated */ 1262 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1263 1264 /* wait a little for things to stabilise */ 1265 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1266 1267 /* enable interrupts */ 1268 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1269 ATMEGA_UDINT_SUSPE | 1270 ATMEGA_UDINT_EORSTE); 1271 1272 /* reset all endpoints */ 1273 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1274 (1 << ATMEGA_EP_MAX) - 1); 1275 1276 /* disable reset */ 1277 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1278 1279 /* disable all endpoints */ 1280 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1281 /* select endpoint */ 1282 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1283 1284 /* disable endpoint interrupt */ 1285 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1286 1287 /* disable endpoint */ 1288 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1289 } 1290 1291 /* turn off clocks */ 1292 1293 atmegadci_clocks_off(sc); 1294 1295 /* read initial VBUS state */ 1296 1297 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1298 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1299 1300 USB_BUS_UNLOCK(&sc->sc_bus); 1301 1302 /* catch any lost interrupts */ 1303 1304 atmegadci_do_poll(&sc->sc_bus); 1305 1306 return (0); /* success */ 1307 } 1308 1309 void 1310 atmegadci_uninit(struct atmegadci_softc *sc) 1311 { 1312 USB_BUS_LOCK(&sc->sc_bus); 1313 1314 /* turn on clocks */ 1315 (sc->sc_clocks_on) (&sc->sc_bus); 1316 1317 /* disable interrupts */ 1318 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1319 1320 /* reset all endpoints */ 1321 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1322 (1 << ATMEGA_EP_MAX) - 1); 1323 1324 /* disable reset */ 1325 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1326 1327 sc->sc_flags.port_powered = 0; 1328 sc->sc_flags.status_vbus = 0; 1329 sc->sc_flags.status_bus_reset = 0; 1330 sc->sc_flags.status_suspend = 0; 1331 sc->sc_flags.change_suspend = 0; 1332 sc->sc_flags.change_connect = 1; 1333 1334 atmegadci_pull_down(sc); 1335 atmegadci_clocks_off(sc); 1336 1337 /* disable USB PAD regulator */ 1338 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1339 1340 USB_BUS_UNLOCK(&sc->sc_bus); 1341 } 1342 1343 static void 1344 atmegadci_suspend(struct atmegadci_softc *sc) 1345 { 1346 /* TODO */ 1347 } 1348 1349 static void 1350 atmegadci_resume(struct atmegadci_softc *sc) 1351 { 1352 /* TODO */ 1353 } 1354 1355 static void 1356 atmegadci_do_poll(struct usb_bus *bus) 1357 { 1358 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1359 1360 USB_BUS_LOCK(&sc->sc_bus); 1361 atmegadci_interrupt_poll(sc); 1362 USB_BUS_UNLOCK(&sc->sc_bus); 1363 } 1364 1365 /*------------------------------------------------------------------------* 1366 * atmegadci bulk support 1367 * atmegadci control support 1368 * atmegadci interrupt support 1369 *------------------------------------------------------------------------*/ 1370 static void 1371 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1372 { 1373 return; 1374 } 1375 1376 static void 1377 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1378 { 1379 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1380 } 1381 1382 static void 1383 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1384 { 1385 return; 1386 } 1387 1388 static void 1389 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1390 { 1391 /* setup TDs */ 1392 atmegadci_setup_standard_chain(xfer); 1393 atmegadci_start_standard_chain(xfer); 1394 } 1395 1396 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1397 { 1398 .open = atmegadci_device_non_isoc_open, 1399 .close = atmegadci_device_non_isoc_close, 1400 .enter = atmegadci_device_non_isoc_enter, 1401 .start = atmegadci_device_non_isoc_start, 1402 }; 1403 1404 /*------------------------------------------------------------------------* 1405 * atmegadci full speed isochronous support 1406 *------------------------------------------------------------------------*/ 1407 static void 1408 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1409 { 1410 return; 1411 } 1412 1413 static void 1414 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1415 { 1416 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1417 } 1418 1419 static void 1420 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1421 { 1422 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1423 uint32_t temp; 1424 uint32_t nframes; 1425 1426 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1427 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1428 1429 /* get the current frame index */ 1430 1431 nframes = 1432 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1433 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1434 1435 nframes &= ATMEGA_FRAME_MASK; 1436 1437 /* 1438 * check if the frame index is within the window where the frames 1439 * will be inserted 1440 */ 1441 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK; 1442 1443 if ((xfer->endpoint->is_synced == 0) || 1444 (temp < xfer->nframes)) { 1445 /* 1446 * If there is data underflow or the pipe queue is 1447 * empty we schedule the transfer a few frames ahead 1448 * of the current frame position. Else two isochronous 1449 * transfers might overlap. 1450 */ 1451 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1452 xfer->endpoint->is_synced = 1; 1453 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1454 } 1455 /* 1456 * compute how many milliseconds the insertion is ahead of the 1457 * current frame position: 1458 */ 1459 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1460 1461 /* 1462 * pre-compute when the isochronous transfer will be finished: 1463 */ 1464 xfer->isoc_time_complete = 1465 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1466 xfer->nframes; 1467 1468 /* compute frame number for next insertion */ 1469 xfer->endpoint->isoc_next += xfer->nframes; 1470 1471 /* setup TDs */ 1472 atmegadci_setup_standard_chain(xfer); 1473 } 1474 1475 static void 1476 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1477 { 1478 /* start TD chain */ 1479 atmegadci_start_standard_chain(xfer); 1480 } 1481 1482 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1483 { 1484 .open = atmegadci_device_isoc_fs_open, 1485 .close = atmegadci_device_isoc_fs_close, 1486 .enter = atmegadci_device_isoc_fs_enter, 1487 .start = atmegadci_device_isoc_fs_start, 1488 }; 1489 1490 /*------------------------------------------------------------------------* 1491 * atmegadci root control support 1492 *------------------------------------------------------------------------* 1493 * Simulate a hardware HUB by handling all the necessary requests. 1494 *------------------------------------------------------------------------*/ 1495 1496 static const struct usb_device_descriptor atmegadci_devd = { 1497 .bLength = sizeof(struct usb_device_descriptor), 1498 .bDescriptorType = UDESC_DEVICE, 1499 .bcdUSB = {0x00, 0x02}, 1500 .bDeviceClass = UDCLASS_HUB, 1501 .bDeviceSubClass = UDSUBCLASS_HUB, 1502 .bDeviceProtocol = UDPROTO_FSHUB, 1503 .bMaxPacketSize = 64, 1504 .bcdDevice = {0x00, 0x01}, 1505 .iManufacturer = 1, 1506 .iProduct = 2, 1507 .bNumConfigurations = 1, 1508 }; 1509 1510 static const struct atmegadci_config_desc atmegadci_confd = { 1511 .confd = { 1512 .bLength = sizeof(struct usb_config_descriptor), 1513 .bDescriptorType = UDESC_CONFIG, 1514 .wTotalLength[0] = sizeof(atmegadci_confd), 1515 .bNumInterface = 1, 1516 .bConfigurationValue = 1, 1517 .iConfiguration = 0, 1518 .bmAttributes = UC_SELF_POWERED, 1519 .bMaxPower = 0, 1520 }, 1521 .ifcd = { 1522 .bLength = sizeof(struct usb_interface_descriptor), 1523 .bDescriptorType = UDESC_INTERFACE, 1524 .bNumEndpoints = 1, 1525 .bInterfaceClass = UICLASS_HUB, 1526 .bInterfaceSubClass = UISUBCLASS_HUB, 1527 .bInterfaceProtocol = 0, 1528 }, 1529 .endpd = { 1530 .bLength = sizeof(struct usb_endpoint_descriptor), 1531 .bDescriptorType = UDESC_ENDPOINT, 1532 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1533 .bmAttributes = UE_INTERRUPT, 1534 .wMaxPacketSize[0] = 8, 1535 .bInterval = 255, 1536 }, 1537 }; 1538 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1539 1540 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1541 .bDescLength = sizeof(atmegadci_hubd), 1542 .bDescriptorType = UDESC_HUB, 1543 .bNbrPorts = 1, 1544 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1545 .bPwrOn2PwrGood = 50, 1546 .bHubContrCurrent = 0, 1547 .DeviceRemovable = {0}, /* port is removable */ 1548 }; 1549 1550 #define STRING_VENDOR \ 1551 "A\0T\0M\0E\0G\0A" 1552 1553 #define STRING_PRODUCT \ 1554 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1555 1556 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1557 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1558 1559 static usb_error_t 1560 atmegadci_roothub_exec(struct usb_device *udev, 1561 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1562 { 1563 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1564 const void *ptr; 1565 uint16_t len; 1566 uint16_t value; 1567 uint16_t index; 1568 uint8_t temp; 1569 usb_error_t err; 1570 1571 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1572 1573 /* buffer reset */ 1574 ptr = (const void *)&sc->sc_hub_temp; 1575 len = 0; 1576 err = 0; 1577 1578 value = UGETW(req->wValue); 1579 index = UGETW(req->wIndex); 1580 1581 /* demultiplex the control request */ 1582 1583 switch (req->bmRequestType) { 1584 case UT_READ_DEVICE: 1585 switch (req->bRequest) { 1586 case UR_GET_DESCRIPTOR: 1587 goto tr_handle_get_descriptor; 1588 case UR_GET_CONFIG: 1589 goto tr_handle_get_config; 1590 case UR_GET_STATUS: 1591 goto tr_handle_get_status; 1592 default: 1593 goto tr_stalled; 1594 } 1595 break; 1596 1597 case UT_WRITE_DEVICE: 1598 switch (req->bRequest) { 1599 case UR_SET_ADDRESS: 1600 goto tr_handle_set_address; 1601 case UR_SET_CONFIG: 1602 goto tr_handle_set_config; 1603 case UR_CLEAR_FEATURE: 1604 goto tr_valid; /* nop */ 1605 case UR_SET_DESCRIPTOR: 1606 goto tr_valid; /* nop */ 1607 case UR_SET_FEATURE: 1608 default: 1609 goto tr_stalled; 1610 } 1611 break; 1612 1613 case UT_WRITE_ENDPOINT: 1614 switch (req->bRequest) { 1615 case UR_CLEAR_FEATURE: 1616 switch (UGETW(req->wValue)) { 1617 case UF_ENDPOINT_HALT: 1618 goto tr_handle_clear_halt; 1619 case UF_DEVICE_REMOTE_WAKEUP: 1620 goto tr_handle_clear_wakeup; 1621 default: 1622 goto tr_stalled; 1623 } 1624 break; 1625 case UR_SET_FEATURE: 1626 switch (UGETW(req->wValue)) { 1627 case UF_ENDPOINT_HALT: 1628 goto tr_handle_set_halt; 1629 case UF_DEVICE_REMOTE_WAKEUP: 1630 goto tr_handle_set_wakeup; 1631 default: 1632 goto tr_stalled; 1633 } 1634 break; 1635 case UR_SYNCH_FRAME: 1636 goto tr_valid; /* nop */ 1637 default: 1638 goto tr_stalled; 1639 } 1640 break; 1641 1642 case UT_READ_ENDPOINT: 1643 switch (req->bRequest) { 1644 case UR_GET_STATUS: 1645 goto tr_handle_get_ep_status; 1646 default: 1647 goto tr_stalled; 1648 } 1649 break; 1650 1651 case UT_WRITE_INTERFACE: 1652 switch (req->bRequest) { 1653 case UR_SET_INTERFACE: 1654 goto tr_handle_set_interface; 1655 case UR_CLEAR_FEATURE: 1656 goto tr_valid; /* nop */ 1657 case UR_SET_FEATURE: 1658 default: 1659 goto tr_stalled; 1660 } 1661 break; 1662 1663 case UT_READ_INTERFACE: 1664 switch (req->bRequest) { 1665 case UR_GET_INTERFACE: 1666 goto tr_handle_get_interface; 1667 case UR_GET_STATUS: 1668 goto tr_handle_get_iface_status; 1669 default: 1670 goto tr_stalled; 1671 } 1672 break; 1673 1674 case UT_WRITE_CLASS_INTERFACE: 1675 case UT_WRITE_VENDOR_INTERFACE: 1676 /* XXX forward */ 1677 break; 1678 1679 case UT_READ_CLASS_INTERFACE: 1680 case UT_READ_VENDOR_INTERFACE: 1681 /* XXX forward */ 1682 break; 1683 1684 case UT_WRITE_CLASS_DEVICE: 1685 switch (req->bRequest) { 1686 case UR_CLEAR_FEATURE: 1687 goto tr_valid; 1688 case UR_SET_DESCRIPTOR: 1689 case UR_SET_FEATURE: 1690 break; 1691 default: 1692 goto tr_stalled; 1693 } 1694 break; 1695 1696 case UT_WRITE_CLASS_OTHER: 1697 switch (req->bRequest) { 1698 case UR_CLEAR_FEATURE: 1699 goto tr_handle_clear_port_feature; 1700 case UR_SET_FEATURE: 1701 goto tr_handle_set_port_feature; 1702 case UR_CLEAR_TT_BUFFER: 1703 case UR_RESET_TT: 1704 case UR_STOP_TT: 1705 goto tr_valid; 1706 1707 default: 1708 goto tr_stalled; 1709 } 1710 break; 1711 1712 case UT_READ_CLASS_OTHER: 1713 switch (req->bRequest) { 1714 case UR_GET_TT_STATE: 1715 goto tr_handle_get_tt_state; 1716 case UR_GET_STATUS: 1717 goto tr_handle_get_port_status; 1718 default: 1719 goto tr_stalled; 1720 } 1721 break; 1722 1723 case UT_READ_CLASS_DEVICE: 1724 switch (req->bRequest) { 1725 case UR_GET_DESCRIPTOR: 1726 goto tr_handle_get_class_descriptor; 1727 case UR_GET_STATUS: 1728 goto tr_handle_get_class_status; 1729 1730 default: 1731 goto tr_stalled; 1732 } 1733 break; 1734 default: 1735 goto tr_stalled; 1736 } 1737 goto tr_valid; 1738 1739 tr_handle_get_descriptor: 1740 switch (value >> 8) { 1741 case UDESC_DEVICE: 1742 if (value & 0xff) { 1743 goto tr_stalled; 1744 } 1745 len = sizeof(atmegadci_devd); 1746 ptr = (const void *)&atmegadci_devd; 1747 goto tr_valid; 1748 case UDESC_CONFIG: 1749 if (value & 0xff) { 1750 goto tr_stalled; 1751 } 1752 len = sizeof(atmegadci_confd); 1753 ptr = (const void *)&atmegadci_confd; 1754 goto tr_valid; 1755 case UDESC_STRING: 1756 switch (value & 0xff) { 1757 case 0: /* Language table */ 1758 len = sizeof(usb_string_lang_en); 1759 ptr = (const void *)&usb_string_lang_en; 1760 goto tr_valid; 1761 1762 case 1: /* Vendor */ 1763 len = sizeof(atmegadci_vendor); 1764 ptr = (const void *)&atmegadci_vendor; 1765 goto tr_valid; 1766 1767 case 2: /* Product */ 1768 len = sizeof(atmegadci_product); 1769 ptr = (const void *)&atmegadci_product; 1770 goto tr_valid; 1771 default: 1772 break; 1773 } 1774 break; 1775 default: 1776 goto tr_stalled; 1777 } 1778 goto tr_stalled; 1779 1780 tr_handle_get_config: 1781 len = 1; 1782 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1783 goto tr_valid; 1784 1785 tr_handle_get_status: 1786 len = 2; 1787 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1788 goto tr_valid; 1789 1790 tr_handle_set_address: 1791 if (value & 0xFF00) { 1792 goto tr_stalled; 1793 } 1794 sc->sc_rt_addr = value; 1795 goto tr_valid; 1796 1797 tr_handle_set_config: 1798 if (value >= 2) { 1799 goto tr_stalled; 1800 } 1801 sc->sc_conf = value; 1802 goto tr_valid; 1803 1804 tr_handle_get_interface: 1805 len = 1; 1806 sc->sc_hub_temp.wValue[0] = 0; 1807 goto tr_valid; 1808 1809 tr_handle_get_tt_state: 1810 tr_handle_get_class_status: 1811 tr_handle_get_iface_status: 1812 tr_handle_get_ep_status: 1813 len = 2; 1814 USETW(sc->sc_hub_temp.wValue, 0); 1815 goto tr_valid; 1816 1817 tr_handle_set_halt: 1818 tr_handle_set_interface: 1819 tr_handle_set_wakeup: 1820 tr_handle_clear_wakeup: 1821 tr_handle_clear_halt: 1822 goto tr_valid; 1823 1824 tr_handle_clear_port_feature: 1825 if (index != 1) { 1826 goto tr_stalled; 1827 } 1828 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1829 1830 switch (value) { 1831 case UHF_PORT_SUSPEND: 1832 atmegadci_wakeup_peer(sc); 1833 break; 1834 1835 case UHF_PORT_ENABLE: 1836 sc->sc_flags.port_enabled = 0; 1837 break; 1838 1839 case UHF_PORT_TEST: 1840 case UHF_PORT_INDICATOR: 1841 case UHF_C_PORT_ENABLE: 1842 case UHF_C_PORT_OVER_CURRENT: 1843 case UHF_C_PORT_RESET: 1844 /* nops */ 1845 break; 1846 case UHF_PORT_POWER: 1847 sc->sc_flags.port_powered = 0; 1848 atmegadci_pull_down(sc); 1849 atmegadci_clocks_off(sc); 1850 break; 1851 case UHF_C_PORT_CONNECTION: 1852 /* clear connect change flag */ 1853 sc->sc_flags.change_connect = 0; 1854 1855 if (!sc->sc_flags.status_bus_reset) { 1856 /* we are not connected */ 1857 break; 1858 } 1859 1860 /* configure the control endpoint */ 1861 1862 /* select endpoint number */ 1863 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1864 1865 /* set endpoint reset */ 1866 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1867 1868 /* clear endpoint reset */ 1869 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1870 1871 /* enable and stall endpoint */ 1872 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1873 ATMEGA_UECONX_EPEN | 1874 ATMEGA_UECONX_STALLRQ); 1875 1876 /* one bank, 64-bytes wMaxPacket */ 1877 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1878 ATMEGA_UECFG0X_EPTYPE0); 1879 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1880 ATMEGA_UECFG1X_ALLOC | 1881 ATMEGA_UECFG1X_EPBK0 | 1882 ATMEGA_UECFG1X_EPSIZE(3)); 1883 1884 /* check valid config */ 1885 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1886 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1887 device_printf(sc->sc_bus.bdev, 1888 "Chip rejected EP0 configuration\n"); 1889 } 1890 break; 1891 case UHF_C_PORT_SUSPEND: 1892 sc->sc_flags.change_suspend = 0; 1893 break; 1894 default: 1895 err = USB_ERR_IOERROR; 1896 goto done; 1897 } 1898 goto tr_valid; 1899 1900 tr_handle_set_port_feature: 1901 if (index != 1) { 1902 goto tr_stalled; 1903 } 1904 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1905 1906 switch (value) { 1907 case UHF_PORT_ENABLE: 1908 sc->sc_flags.port_enabled = 1; 1909 break; 1910 case UHF_PORT_SUSPEND: 1911 case UHF_PORT_RESET: 1912 case UHF_PORT_TEST: 1913 case UHF_PORT_INDICATOR: 1914 /* nops */ 1915 break; 1916 case UHF_PORT_POWER: 1917 sc->sc_flags.port_powered = 1; 1918 break; 1919 default: 1920 err = USB_ERR_IOERROR; 1921 goto done; 1922 } 1923 goto tr_valid; 1924 1925 tr_handle_get_port_status: 1926 1927 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1928 1929 if (index != 1) { 1930 goto tr_stalled; 1931 } 1932 if (sc->sc_flags.status_vbus) { 1933 atmegadci_clocks_on(sc); 1934 atmegadci_pull_up(sc); 1935 } else { 1936 atmegadci_pull_down(sc); 1937 atmegadci_clocks_off(sc); 1938 } 1939 1940 /* Select FULL-speed and Device Side Mode */ 1941 1942 value = UPS_PORT_MODE_DEVICE; 1943 1944 if (sc->sc_flags.port_powered) { 1945 value |= UPS_PORT_POWER; 1946 } 1947 if (sc->sc_flags.port_enabled) { 1948 value |= UPS_PORT_ENABLED; 1949 } 1950 if (sc->sc_flags.status_vbus && 1951 sc->sc_flags.status_bus_reset) { 1952 value |= UPS_CURRENT_CONNECT_STATUS; 1953 } 1954 if (sc->sc_flags.status_suspend) { 1955 value |= UPS_SUSPEND; 1956 } 1957 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1958 1959 value = 0; 1960 1961 if (sc->sc_flags.change_connect) { 1962 value |= UPS_C_CONNECT_STATUS; 1963 } 1964 if (sc->sc_flags.change_suspend) { 1965 value |= UPS_C_SUSPEND; 1966 } 1967 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1968 len = sizeof(sc->sc_hub_temp.ps); 1969 goto tr_valid; 1970 1971 tr_handle_get_class_descriptor: 1972 if (value & 0xFF) { 1973 goto tr_stalled; 1974 } 1975 ptr = (const void *)&atmegadci_hubd; 1976 len = sizeof(atmegadci_hubd); 1977 goto tr_valid; 1978 1979 tr_stalled: 1980 err = USB_ERR_STALLED; 1981 tr_valid: 1982 done: 1983 *plength = len; 1984 *pptr = ptr; 1985 return (err); 1986 } 1987 1988 static void 1989 atmegadci_xfer_setup(struct usb_setup_params *parm) 1990 { 1991 const struct usb_hw_ep_profile *pf; 1992 struct atmegadci_softc *sc; 1993 struct usb_xfer *xfer; 1994 void *last_obj; 1995 uint32_t ntd; 1996 uint32_t n; 1997 uint8_t ep_no; 1998 1999 sc = ATMEGA_BUS2SC(parm->udev->bus); 2000 xfer = parm->curr_xfer; 2001 2002 /* 2003 * NOTE: This driver does not use any of the parameters that 2004 * are computed from the following values. Just set some 2005 * reasonable dummies: 2006 */ 2007 parm->hc_max_packet_size = 0x500; 2008 parm->hc_max_packet_count = 1; 2009 parm->hc_max_frame_size = 0x500; 2010 2011 usbd_transfer_setup_sub(parm); 2012 2013 /* 2014 * compute maximum number of TDs 2015 */ 2016 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2017 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2018 + 1 /* SYNC 2 */ ; 2019 } else { 2020 ntd = xfer->nframes + 1 /* SYNC */ ; 2021 } 2022 2023 /* 2024 * check if "usbd_transfer_setup_sub" set an error 2025 */ 2026 if (parm->err) 2027 return; 2028 2029 /* 2030 * allocate transfer descriptors 2031 */ 2032 last_obj = NULL; 2033 2034 /* 2035 * get profile stuff 2036 */ 2037 ep_no = xfer->endpointno & UE_ADDR; 2038 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2039 2040 if (pf == NULL) { 2041 /* should not happen */ 2042 parm->err = USB_ERR_INVAL; 2043 return; 2044 } 2045 2046 /* align data */ 2047 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2048 2049 for (n = 0; n != ntd; n++) { 2050 struct atmegadci_td *td; 2051 2052 if (parm->buf) { 2053 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2054 2055 /* init TD */ 2056 td->max_packet_size = xfer->max_packet_size; 2057 td->ep_no = ep_no; 2058 if (pf->support_multi_buffer) { 2059 td->support_multi_buffer = 1; 2060 } 2061 td->obj_next = last_obj; 2062 2063 last_obj = td; 2064 } 2065 parm->size[0] += sizeof(*td); 2066 } 2067 2068 xfer->td_start[0] = last_obj; 2069 } 2070 2071 static void 2072 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2073 { 2074 return; 2075 } 2076 2077 static void 2078 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2079 struct usb_endpoint *ep) 2080 { 2081 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2082 2083 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2084 ep, udev->address, 2085 edesc->bEndpointAddress, udev->flags.usb_mode, 2086 sc->sc_rt_addr, udev->device_index); 2087 2088 if (udev->device_index != sc->sc_rt_addr) { 2089 if (udev->speed != USB_SPEED_FULL) { 2090 /* not supported */ 2091 return; 2092 } 2093 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2094 ep->methods = &atmegadci_device_isoc_fs_methods; 2095 else 2096 ep->methods = &atmegadci_device_non_isoc_methods; 2097 } 2098 } 2099 2100 static void 2101 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2102 { 2103 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2104 2105 switch (state) { 2106 case USB_HW_POWER_SUSPEND: 2107 atmegadci_suspend(sc); 2108 break; 2109 case USB_HW_POWER_SHUTDOWN: 2110 atmegadci_uninit(sc); 2111 break; 2112 case USB_HW_POWER_RESUME: 2113 atmegadci_resume(sc); 2114 break; 2115 default: 2116 break; 2117 } 2118 } 2119 2120 static const struct usb_bus_methods atmegadci_bus_methods = 2121 { 2122 .endpoint_init = &atmegadci_ep_init, 2123 .xfer_setup = &atmegadci_xfer_setup, 2124 .xfer_unsetup = &atmegadci_xfer_unsetup, 2125 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2126 .xfer_stall = &atmegadci_xfer_stall, 2127 .set_stall = &atmegadci_set_stall, 2128 .clear_stall = &atmegadci_clear_stall, 2129 .roothub_exec = &atmegadci_roothub_exec, 2130 .xfer_poll = &atmegadci_do_poll, 2131 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2132 }; 2133