1 /* $FreeBSD$ */
2 /*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * This file contains the driver for the ATMEGA series USB OTG Controller. This
31 * driver currently only supports the DCI mode of the USB hardware.
32 */
33
34 /*
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
37 */
38
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
41 #else
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/module.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
55 #include <sys/sx.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
59 #include <sys/priv.h>
60
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63
64 #define USB_DEBUG_VAR atmegadci_debug
65
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
74
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
78
79 #include <dev/usb/controller/atmegadci.h>
80
81 #define ATMEGA_BUS2SC(bus) \
82 __containerof(bus, struct atmegadci_softc, sc_bus)
83
84 #define ATMEGA_PC2SC(pc) \
85 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
86
87 #ifdef USB_DEBUG
88 static int atmegadci_debug = 0;
89
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
91 "USB ATMEGA DCI");
92 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN,
93 &atmegadci_debug, 0, "ATMEGA DCI debug level");
94 #endif
95
96 #define ATMEGA_INTR_ENDPT 1
97
98 /* prototypes */
99
100 static const struct usb_bus_methods atmegadci_bus_methods;
101 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods;
102 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
103
104 static atmegadci_cmd_t atmegadci_setup_rx;
105 static atmegadci_cmd_t atmegadci_data_rx;
106 static atmegadci_cmd_t atmegadci_data_tx;
107 static atmegadci_cmd_t atmegadci_data_tx_sync;
108 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
109 static void atmegadci_do_poll(struct usb_bus *);
110 static void atmegadci_standard_done(struct usb_xfer *);
111 static void atmegadci_root_intr(struct atmegadci_softc *sc);
112
113 /*
114 * Here is a list of what the chip supports:
115 */
116 static const struct usb_hw_ep_profile
117 atmegadci_ep_profile[2] = {
118 [0] = {
119 .max_in_frame_size = 64,
120 .max_out_frame_size = 64,
121 .is_simplex = 1,
122 .support_control = 1,
123 },
124 [1] = {
125 .max_in_frame_size = 64,
126 .max_out_frame_size = 64,
127 .is_simplex = 1,
128 .support_bulk = 1,
129 .support_interrupt = 1,
130 .support_isochronous = 1,
131 .support_in = 1,
132 .support_out = 1,
133 },
134 };
135
136 static void
atmegadci_get_hw_ep_profile(struct usb_device * udev,const struct usb_hw_ep_profile ** ppf,uint8_t ep_addr)137 atmegadci_get_hw_ep_profile(struct usb_device *udev,
138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
139 {
140 if (ep_addr == 0)
141 *ppf = atmegadci_ep_profile;
142 else if (ep_addr < ATMEGA_EP_MAX)
143 *ppf = atmegadci_ep_profile + 1;
144 else
145 *ppf = NULL;
146 }
147
148 static void
atmegadci_clocks_on(struct atmegadci_softc * sc)149 atmegadci_clocks_on(struct atmegadci_softc *sc)
150 {
151 if (sc->sc_flags.clocks_off &&
152 sc->sc_flags.port_powered) {
153 DPRINTFN(5, "\n");
154
155 /* turn on clocks */
156 (sc->sc_clocks_on) (&sc->sc_bus);
157
158 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
159 ATMEGA_USBCON_USBE |
160 ATMEGA_USBCON_OTGPADE |
161 ATMEGA_USBCON_VBUSTE);
162
163 sc->sc_flags.clocks_off = 0;
164
165 /* enable transceiver ? */
166 }
167 }
168
169 static void
atmegadci_clocks_off(struct atmegadci_softc * sc)170 atmegadci_clocks_off(struct atmegadci_softc *sc)
171 {
172 if (!sc->sc_flags.clocks_off) {
173 DPRINTFN(5, "\n");
174
175 /* disable Transceiver ? */
176
177 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
178 ATMEGA_USBCON_USBE |
179 ATMEGA_USBCON_OTGPADE |
180 ATMEGA_USBCON_FRZCLK |
181 ATMEGA_USBCON_VBUSTE);
182
183 /* turn clocks off */
184 (sc->sc_clocks_off) (&sc->sc_bus);
185
186 sc->sc_flags.clocks_off = 1;
187 }
188 }
189
190 static void
atmegadci_pull_up(struct atmegadci_softc * sc)191 atmegadci_pull_up(struct atmegadci_softc *sc)
192 {
193 /* pullup D+, if possible */
194
195 if (!sc->sc_flags.d_pulled_up &&
196 sc->sc_flags.port_powered) {
197 sc->sc_flags.d_pulled_up = 1;
198 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
199 }
200 }
201
202 static void
atmegadci_pull_down(struct atmegadci_softc * sc)203 atmegadci_pull_down(struct atmegadci_softc *sc)
204 {
205 /* pulldown D+, if possible */
206
207 if (sc->sc_flags.d_pulled_up) {
208 sc->sc_flags.d_pulled_up = 0;
209 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
210 }
211 }
212
213 static void
atmegadci_wakeup_peer(struct atmegadci_softc * sc)214 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
215 {
216 uint8_t temp;
217
218 if (!sc->sc_flags.status_suspend) {
219 return;
220 }
221
222 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
223 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
224
225 /* wait 8 milliseconds */
226 /* Wait for reset to complete. */
227 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
228
229 /* hardware should have cleared RMWKUP bit */
230 }
231
232 static void
atmegadci_set_address(struct atmegadci_softc * sc,uint8_t addr)233 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
234 {
235 DPRINTFN(5, "addr=%d\n", addr);
236
237 addr |= ATMEGA_UDADDR_ADDEN;
238
239 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
240 }
241
242 static uint8_t
atmegadci_setup_rx(struct atmegadci_td * td)243 atmegadci_setup_rx(struct atmegadci_td *td)
244 {
245 struct atmegadci_softc *sc;
246 struct usb_device_request req;
247 uint16_t count;
248 uint8_t temp;
249
250 /* get pointer to softc */
251 sc = ATMEGA_PC2SC(td->pc);
252
253 /* select endpoint number */
254 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
255
256 /* check endpoint status */
257 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
258
259 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
260
261 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
262 goto not_complete;
263 }
264 /* clear did stall */
265 td->did_stall = 0;
266 /* get the packet byte count */
267 count =
268 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
269 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
270
271 /* mask away undefined bits */
272 count &= 0x7FF;
273
274 /* verify data length */
275 if (count != td->remainder) {
276 DPRINTFN(0, "Invalid SETUP packet "
277 "length, %d bytes\n", count);
278 goto not_complete;
279 }
280 if (count != sizeof(req)) {
281 DPRINTFN(0, "Unsupported SETUP packet "
282 "length, %d bytes\n", count);
283 goto not_complete;
284 }
285 /* receive data */
286 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
287 (void *)&req, sizeof(req));
288
289 /* copy data into real buffer */
290 usbd_copy_in(td->pc, 0, &req, sizeof(req));
291
292 td->offset = sizeof(req);
293 td->remainder = 0;
294
295 /* sneak peek the set address */
296 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
297 (req.bRequest == UR_SET_ADDRESS)) {
298 sc->sc_dv_addr = req.wValue[0] & 0x7F;
299 /* must write address before ZLP */
300 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
301 } else {
302 sc->sc_dv_addr = 0xFF;
303 }
304
305 /* Clear SETUP packet interrupt and all other previous interrupts */
306 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
307 return (0); /* complete */
308
309 not_complete:
310 /* abort any ongoing transfer */
311 if (!td->did_stall) {
312 DPRINTFN(5, "stalling\n");
313 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
314 ATMEGA_UECONX_EPEN |
315 ATMEGA_UECONX_STALLRQ);
316 td->did_stall = 1;
317 }
318 if (temp & ATMEGA_UEINTX_RXSTPI) {
319 /* clear SETUP packet interrupt */
320 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
321 }
322 /* we only want to know if there is a SETUP packet */
323 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
324 return (1); /* not complete */
325 }
326
327 static uint8_t
atmegadci_data_rx(struct atmegadci_td * td)328 atmegadci_data_rx(struct atmegadci_td *td)
329 {
330 struct atmegadci_softc *sc;
331 struct usb_page_search buf_res;
332 uint16_t count;
333 uint8_t temp;
334 uint8_t to;
335 uint8_t got_short;
336
337 to = 3; /* don't loop forever! */
338 got_short = 0;
339
340 /* get pointer to softc */
341 sc = ATMEGA_PC2SC(td->pc);
342
343 /* select endpoint number */
344 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
345
346 repeat:
347 /* check if any of the FIFO banks have data */
348 /* check endpoint status */
349 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
350
351 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
352
353 if (temp & ATMEGA_UEINTX_RXSTPI) {
354 if (td->remainder == 0) {
355 /*
356 * We are actually complete and have
357 * received the next SETUP
358 */
359 DPRINTFN(5, "faking complete\n");
360 return (0); /* complete */
361 }
362 /*
363 * USB Host Aborted the transfer.
364 */
365 td->error = 1;
366 return (0); /* complete */
367 }
368 /* check status */
369 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
370 ATMEGA_UEINTX_RXOUTI))) {
371 /* no data */
372 goto not_complete;
373 }
374 /* get the packet byte count */
375 count =
376 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
377 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
378
379 /* mask away undefined bits */
380 count &= 0x7FF;
381
382 /* verify the packet byte count */
383 if (count != td->max_packet_size) {
384 if (count < td->max_packet_size) {
385 /* we have a short packet */
386 td->short_pkt = 1;
387 got_short = 1;
388 } else {
389 /* invalid USB packet */
390 td->error = 1;
391 return (0); /* we are complete */
392 }
393 }
394 /* verify the packet byte count */
395 if (count > td->remainder) {
396 /* invalid USB packet */
397 td->error = 1;
398 return (0); /* we are complete */
399 }
400 while (count > 0) {
401 usbd_get_page(td->pc, td->offset, &buf_res);
402
403 /* get correct length */
404 if (buf_res.length > count) {
405 buf_res.length = count;
406 }
407 /* receive data */
408 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
409 buf_res.buffer, buf_res.length);
410
411 /* update counters */
412 count -= buf_res.length;
413 td->offset += buf_res.length;
414 td->remainder -= buf_res.length;
415 }
416
417 /* clear OUT packet interrupt */
418 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
419
420 /* release FIFO bank */
421 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
422
423 /* check if we are complete */
424 if ((td->remainder == 0) || got_short) {
425 if (td->short_pkt) {
426 /* we are complete */
427 return (0);
428 }
429 /* else need to receive a zero length packet */
430 }
431 if (--to) {
432 goto repeat;
433 }
434 not_complete:
435 /* we only want to know if there is a SETUP packet or OUT packet */
436 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
437 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
438 return (1); /* not complete */
439 }
440
441 static uint8_t
atmegadci_data_tx(struct atmegadci_td * td)442 atmegadci_data_tx(struct atmegadci_td *td)
443 {
444 struct atmegadci_softc *sc;
445 struct usb_page_search buf_res;
446 uint16_t count;
447 uint8_t to;
448 uint8_t temp;
449
450 to = 3; /* don't loop forever! */
451
452 /* get pointer to softc */
453 sc = ATMEGA_PC2SC(td->pc);
454
455 /* select endpoint number */
456 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
457
458 repeat:
459
460 /* check endpoint status */
461 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
462
463 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
464
465 if (temp & ATMEGA_UEINTX_RXSTPI) {
466 /*
467 * The current transfer was aborted
468 * by the USB Host
469 */
470 td->error = 1;
471 return (0); /* complete */
472 }
473
474 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
475 if (temp & 3) {
476 /* cannot write any data - a bank is busy */
477 goto not_complete;
478 }
479
480 count = td->max_packet_size;
481 if (td->remainder < count) {
482 /* we have a short packet */
483 td->short_pkt = 1;
484 count = td->remainder;
485 }
486 while (count > 0) {
487 usbd_get_page(td->pc, td->offset, &buf_res);
488
489 /* get correct length */
490 if (buf_res.length > count) {
491 buf_res.length = count;
492 }
493 /* transmit data */
494 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
495 buf_res.buffer, buf_res.length);
496
497 /* update counters */
498 count -= buf_res.length;
499 td->offset += buf_res.length;
500 td->remainder -= buf_res.length;
501 }
502
503 /* clear IN packet interrupt */
504 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
505
506 /* allocate FIFO bank */
507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
508
509 /* check remainder */
510 if (td->remainder == 0) {
511 if (td->short_pkt) {
512 return (0); /* complete */
513 }
514 /* else we need to transmit a short packet */
515 }
516 if (--to) {
517 goto repeat;
518 }
519 not_complete:
520 /* we only want to know if there is a SETUP packet or free IN packet */
521 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
522 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
523 return (1); /* not complete */
524 }
525
526 static uint8_t
atmegadci_data_tx_sync(struct atmegadci_td * td)527 atmegadci_data_tx_sync(struct atmegadci_td *td)
528 {
529 struct atmegadci_softc *sc;
530 uint8_t temp;
531
532 /* get pointer to softc */
533 sc = ATMEGA_PC2SC(td->pc);
534
535 /* select endpoint number */
536 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
537
538 /* check endpoint status */
539 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
540
541 DPRINTFN(5, "temp=0x%02x\n", temp);
542
543 if (temp & ATMEGA_UEINTX_RXSTPI) {
544 DPRINTFN(5, "faking complete\n");
545 /* Race condition */
546 return (0); /* complete */
547 }
548 /*
549 * The control endpoint has only got one bank, so if that bank
550 * is free the packet has been transferred!
551 */
552 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
553 if (temp & 3) {
554 /* cannot write any data - a bank is busy */
555 goto not_complete;
556 }
557 if (sc->sc_dv_addr != 0xFF) {
558 /* set new address */
559 atmegadci_set_address(sc, sc->sc_dv_addr);
560 }
561 return (0); /* complete */
562
563 not_complete:
564 /* we only want to know if there is a SETUP packet or free IN packet */
565 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
566 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
567 return (1); /* not complete */
568 }
569
570 static uint8_t
atmegadci_xfer_do_fifo(struct usb_xfer * xfer)571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
572 {
573 struct atmegadci_td *td;
574
575 DPRINTFN(9, "\n");
576
577 td = xfer->td_transfer_cache;
578 while (1) {
579 if ((td->func) (td)) {
580 /* operation in progress */
581 break;
582 }
583 if (((void *)td) == xfer->td_transfer_last) {
584 goto done;
585 }
586 if (td->error) {
587 goto done;
588 } else if (td->remainder > 0) {
589 /*
590 * We had a short transfer. If there is no alternate
591 * next, stop processing !
592 */
593 if (!td->alt_next) {
594 goto done;
595 }
596 }
597 /*
598 * Fetch the next transfer descriptor and transfer
599 * some flags to the next transfer descriptor
600 */
601 td = td->obj_next;
602 xfer->td_transfer_cache = td;
603 }
604 return (1); /* not complete */
605
606 done:
607 /* compute all actual lengths */
608
609 atmegadci_standard_done(xfer);
610 return (0); /* complete */
611 }
612
613 static void
atmegadci_interrupt_poll(struct atmegadci_softc * sc)614 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
615 {
616 struct usb_xfer *xfer;
617
618 repeat:
619 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
620 if (!atmegadci_xfer_do_fifo(xfer)) {
621 /* queue has been modified */
622 goto repeat;
623 }
624 }
625 }
626
627 static void
atmegadci_vbus_interrupt(struct atmegadci_softc * sc,uint8_t is_on)628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
629 {
630 DPRINTFN(5, "vbus = %u\n", is_on);
631
632 if (is_on) {
633 if (!sc->sc_flags.status_vbus) {
634 sc->sc_flags.status_vbus = 1;
635
636 /* complete root HUB interrupt endpoint */
637
638 atmegadci_root_intr(sc);
639 }
640 } else {
641 if (sc->sc_flags.status_vbus) {
642 sc->sc_flags.status_vbus = 0;
643 sc->sc_flags.status_bus_reset = 0;
644 sc->sc_flags.status_suspend = 0;
645 sc->sc_flags.change_suspend = 0;
646 sc->sc_flags.change_connect = 1;
647
648 /* complete root HUB interrupt endpoint */
649
650 atmegadci_root_intr(sc);
651 }
652 }
653 }
654
655 void
atmegadci_interrupt(struct atmegadci_softc * sc)656 atmegadci_interrupt(struct atmegadci_softc *sc)
657 {
658 uint8_t status;
659
660 USB_BUS_LOCK(&sc->sc_bus);
661
662 /* read interrupt status */
663 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
664
665 /* clear all set interrupts */
666 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
667
668 DPRINTFN(14, "UDINT=0x%02x\n", status);
669
670 /* check for any bus state change interrupts */
671 if (status & ATMEGA_UDINT_EORSTI) {
672 DPRINTFN(5, "end of reset\n");
673
674 /* set correct state */
675 sc->sc_flags.status_bus_reset = 1;
676 sc->sc_flags.status_suspend = 0;
677 sc->sc_flags.change_suspend = 0;
678 sc->sc_flags.change_connect = 1;
679
680 /* disable resume interrupt */
681 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
682 ATMEGA_UDINT_SUSPE |
683 ATMEGA_UDINT_EORSTE);
684
685 /* complete root HUB interrupt endpoint */
686 atmegadci_root_intr(sc);
687 }
688 /*
689 * If resume and suspend is set at the same time we interpret
690 * that like RESUME. Resume is set when there is at least 3
691 * milliseconds of inactivity on the USB BUS.
692 */
693 if (status & ATMEGA_UDINT_WAKEUPI) {
694 DPRINTFN(5, "resume interrupt\n");
695
696 if (sc->sc_flags.status_suspend) {
697 /* update status bits */
698 sc->sc_flags.status_suspend = 0;
699 sc->sc_flags.change_suspend = 1;
700
701 /* disable resume interrupt */
702 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
703 ATMEGA_UDINT_SUSPE |
704 ATMEGA_UDINT_EORSTE);
705
706 /* complete root HUB interrupt endpoint */
707 atmegadci_root_intr(sc);
708 }
709 } else if (status & ATMEGA_UDINT_SUSPI) {
710 DPRINTFN(5, "suspend interrupt\n");
711
712 if (!sc->sc_flags.status_suspend) {
713 /* update status bits */
714 sc->sc_flags.status_suspend = 1;
715 sc->sc_flags.change_suspend = 1;
716
717 /* disable suspend interrupt */
718 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
719 ATMEGA_UDINT_WAKEUPE |
720 ATMEGA_UDINT_EORSTE);
721
722 /* complete root HUB interrupt endpoint */
723 atmegadci_root_intr(sc);
724 }
725 }
726 /* check VBUS */
727 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
728
729 /* clear all set interrupts */
730 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
731
732 if (status & ATMEGA_USBINT_VBUSTI) {
733 uint8_t temp;
734
735 DPRINTFN(5, "USBINT=0x%02x\n", status);
736
737 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
738 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
739 }
740 /* check for any endpoint interrupts */
741 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
742 /* the hardware will clear the UEINT bits automatically */
743 if (status) {
744 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
745
746 atmegadci_interrupt_poll(sc);
747 }
748 USB_BUS_UNLOCK(&sc->sc_bus);
749 }
750
751 static void
atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp * temp)752 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
753 {
754 struct atmegadci_td *td;
755
756 /* get current Transfer Descriptor */
757 td = temp->td_next;
758 temp->td = td;
759
760 /* prepare for next TD */
761 temp->td_next = td->obj_next;
762
763 /* fill out the Transfer Descriptor */
764 td->func = temp->func;
765 td->pc = temp->pc;
766 td->offset = temp->offset;
767 td->remainder = temp->len;
768 td->error = 0;
769 td->did_stall = temp->did_stall;
770 td->short_pkt = temp->short_pkt;
771 td->alt_next = temp->setup_alt_next;
772 }
773
774 static void
atmegadci_setup_standard_chain(struct usb_xfer * xfer)775 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
776 {
777 struct atmegadci_std_temp temp;
778 struct atmegadci_softc *sc;
779 struct atmegadci_td *td;
780 uint32_t x;
781 uint8_t ep_no;
782 uint8_t need_sync;
783
784 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
785 xfer->address, UE_GET_ADDR(xfer->endpointno),
786 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
787
788 temp.max_frame_size = xfer->max_frame_size;
789
790 td = xfer->td_start[0];
791 xfer->td_transfer_first = td;
792 xfer->td_transfer_cache = td;
793
794 /* setup temp */
795
796 temp.pc = NULL;
797 temp.td = NULL;
798 temp.td_next = xfer->td_start[0];
799 temp.offset = 0;
800 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
801 xfer->flags_int.isochronous_xfr;
802 temp.did_stall = !xfer->flags_int.control_stall;
803
804 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
805 ep_no = (xfer->endpointno & UE_ADDR);
806
807 /* check if we should prepend a setup message */
808
809 if (xfer->flags_int.control_xfr) {
810 if (xfer->flags_int.control_hdr) {
811 temp.func = &atmegadci_setup_rx;
812 temp.len = xfer->frlengths[0];
813 temp.pc = xfer->frbuffers + 0;
814 temp.short_pkt = temp.len ? 1 : 0;
815 /* check for last frame */
816 if (xfer->nframes == 1) {
817 /* no STATUS stage yet, SETUP is last */
818 if (xfer->flags_int.control_act)
819 temp.setup_alt_next = 0;
820 }
821
822 atmegadci_setup_standard_chain_sub(&temp);
823 }
824 x = 1;
825 } else {
826 x = 0;
827 }
828
829 if (x != xfer->nframes) {
830 if (xfer->endpointno & UE_DIR_IN) {
831 temp.func = &atmegadci_data_tx;
832 need_sync = 1;
833 } else {
834 temp.func = &atmegadci_data_rx;
835 need_sync = 0;
836 }
837
838 /* setup "pc" pointer */
839 temp.pc = xfer->frbuffers + x;
840 } else {
841 need_sync = 0;
842 }
843 while (x != xfer->nframes) {
844 /* DATA0 / DATA1 message */
845
846 temp.len = xfer->frlengths[x];
847
848 x++;
849
850 if (x == xfer->nframes) {
851 if (xfer->flags_int.control_xfr) {
852 if (xfer->flags_int.control_act) {
853 temp.setup_alt_next = 0;
854 }
855 } else {
856 temp.setup_alt_next = 0;
857 }
858 }
859 if (temp.len == 0) {
860 /* make sure that we send an USB packet */
861
862 temp.short_pkt = 0;
863
864 } else {
865 /* regular data transfer */
866
867 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
868 }
869
870 atmegadci_setup_standard_chain_sub(&temp);
871
872 if (xfer->flags_int.isochronous_xfr) {
873 temp.offset += temp.len;
874 } else {
875 /* get next Page Cache pointer */
876 temp.pc = xfer->frbuffers + x;
877 }
878 }
879
880 if (xfer->flags_int.control_xfr) {
881 /* always setup a valid "pc" pointer for status and sync */
882 temp.pc = xfer->frbuffers + 0;
883 temp.len = 0;
884 temp.short_pkt = 0;
885 temp.setup_alt_next = 0;
886
887 /* check if we need to sync */
888 if (need_sync) {
889 /* we need a SYNC point after TX */
890 temp.func = &atmegadci_data_tx_sync;
891 atmegadci_setup_standard_chain_sub(&temp);
892 }
893
894 /* check if we should append a status stage */
895 if (!xfer->flags_int.control_act) {
896 /*
897 * Send a DATA1 message and invert the current
898 * endpoint direction.
899 */
900 if (xfer->endpointno & UE_DIR_IN) {
901 temp.func = &atmegadci_data_rx;
902 need_sync = 0;
903 } else {
904 temp.func = &atmegadci_data_tx;
905 need_sync = 1;
906 }
907
908 atmegadci_setup_standard_chain_sub(&temp);
909 if (need_sync) {
910 /* we need a SYNC point after TX */
911 temp.func = &atmegadci_data_tx_sync;
912 atmegadci_setup_standard_chain_sub(&temp);
913 }
914 }
915 }
916 /* must have at least one frame! */
917 td = temp.td;
918 xfer->td_transfer_last = td;
919 }
920
921 static void
atmegadci_timeout(void * arg)922 atmegadci_timeout(void *arg)
923 {
924 struct usb_xfer *xfer = arg;
925
926 DPRINTF("xfer=%p\n", xfer);
927
928 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
929
930 /* transfer is transferred */
931 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
932 }
933
934 static void
atmegadci_start_standard_chain(struct usb_xfer * xfer)935 atmegadci_start_standard_chain(struct usb_xfer *xfer)
936 {
937 DPRINTFN(9, "\n");
938
939 /* poll one time - will turn on interrupts */
940 if (atmegadci_xfer_do_fifo(xfer)) {
941 /* put transfer on interrupt queue */
942 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
943
944 /* start timeout, if any */
945 if (xfer->timeout != 0) {
946 usbd_transfer_timeout_ms(xfer,
947 &atmegadci_timeout, xfer->timeout);
948 }
949 }
950 }
951
952 static void
atmegadci_root_intr(struct atmegadci_softc * sc)953 atmegadci_root_intr(struct atmegadci_softc *sc)
954 {
955 DPRINTFN(9, "\n");
956
957 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
958
959 /* set port bit */
960 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
961
962 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
963 sizeof(sc->sc_hub_idata));
964 }
965
966 static usb_error_t
atmegadci_standard_done_sub(struct usb_xfer * xfer)967 atmegadci_standard_done_sub(struct usb_xfer *xfer)
968 {
969 struct atmegadci_td *td;
970 uint32_t len;
971 uint8_t error;
972
973 DPRINTFN(9, "\n");
974
975 td = xfer->td_transfer_cache;
976
977 do {
978 len = td->remainder;
979
980 if (xfer->aframes != xfer->nframes) {
981 /*
982 * Verify the length and subtract
983 * the remainder from "frlengths[]":
984 */
985 if (len > xfer->frlengths[xfer->aframes]) {
986 td->error = 1;
987 } else {
988 xfer->frlengths[xfer->aframes] -= len;
989 }
990 }
991 /* Check for transfer error */
992 if (td->error) {
993 /* the transfer is finished */
994 error = 1;
995 td = NULL;
996 break;
997 }
998 /* Check for short transfer */
999 if (len > 0) {
1000 if (xfer->flags_int.short_frames_ok ||
1001 xfer->flags_int.isochronous_xfr) {
1002 /* follow alt next */
1003 if (td->alt_next) {
1004 td = td->obj_next;
1005 } else {
1006 td = NULL;
1007 }
1008 } else {
1009 /* the transfer is finished */
1010 td = NULL;
1011 }
1012 error = 0;
1013 break;
1014 }
1015 td = td->obj_next;
1016
1017 /* this USB frame is complete */
1018 error = 0;
1019 break;
1020
1021 } while (0);
1022
1023 /* update transfer cache */
1024
1025 xfer->td_transfer_cache = td;
1026
1027 return (error ?
1028 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1029 }
1030
1031 static void
atmegadci_standard_done(struct usb_xfer * xfer)1032 atmegadci_standard_done(struct usb_xfer *xfer)
1033 {
1034 usb_error_t err = 0;
1035
1036 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1037 xfer, xfer->endpoint);
1038
1039 /* reset scanner */
1040
1041 xfer->td_transfer_cache = xfer->td_transfer_first;
1042
1043 if (xfer->flags_int.control_xfr) {
1044 if (xfer->flags_int.control_hdr) {
1045 err = atmegadci_standard_done_sub(xfer);
1046 }
1047 xfer->aframes = 1;
1048
1049 if (xfer->td_transfer_cache == NULL) {
1050 goto done;
1051 }
1052 }
1053 while (xfer->aframes != xfer->nframes) {
1054 err = atmegadci_standard_done_sub(xfer);
1055 xfer->aframes++;
1056
1057 if (xfer->td_transfer_cache == NULL) {
1058 goto done;
1059 }
1060 }
1061
1062 if (xfer->flags_int.control_xfr &&
1063 !xfer->flags_int.control_act) {
1064 err = atmegadci_standard_done_sub(xfer);
1065 }
1066 done:
1067 atmegadci_device_done(xfer, err);
1068 }
1069
1070 /*------------------------------------------------------------------------*
1071 * atmegadci_device_done
1072 *
1073 * NOTE: this function can be called more than one time on the
1074 * same USB transfer!
1075 *------------------------------------------------------------------------*/
1076 static void
atmegadci_device_done(struct usb_xfer * xfer,usb_error_t error)1077 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1078 {
1079 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1080 uint8_t ep_no;
1081
1082 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1083
1084 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1085 xfer, xfer->endpoint, error);
1086
1087 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1088 ep_no = (xfer->endpointno & UE_ADDR);
1089
1090 /* select endpoint number */
1091 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1092
1093 /* disable endpoint interrupt */
1094 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1095
1096 DPRINTFN(15, "disabled interrupts!\n");
1097 }
1098 /* dequeue transfer and start next transfer */
1099 usbd_transfer_done(xfer, error);
1100 }
1101
1102 static void
atmegadci_xfer_stall(struct usb_xfer * xfer)1103 atmegadci_xfer_stall(struct usb_xfer *xfer)
1104 {
1105 atmegadci_device_done(xfer, USB_ERR_STALLED);
1106 }
1107
1108 static void
atmegadci_set_stall(struct usb_device * udev,struct usb_endpoint * ep,uint8_t * did_stall)1109 atmegadci_set_stall(struct usb_device *udev,
1110 struct usb_endpoint *ep, uint8_t *did_stall)
1111 {
1112 struct atmegadci_softc *sc;
1113 uint8_t ep_no;
1114
1115 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1116
1117 DPRINTFN(5, "endpoint=%p\n", ep);
1118
1119 sc = ATMEGA_BUS2SC(udev->bus);
1120 /* get endpoint number */
1121 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1122 /* select endpoint number */
1123 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1124 /* set stall */
1125 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1126 ATMEGA_UECONX_EPEN |
1127 ATMEGA_UECONX_STALLRQ);
1128 }
1129
1130 static void
atmegadci_clear_stall_sub(struct atmegadci_softc * sc,uint8_t ep_no,uint8_t ep_type,uint8_t ep_dir)1131 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1132 uint8_t ep_type, uint8_t ep_dir)
1133 {
1134 uint8_t temp;
1135
1136 if (ep_type == UE_CONTROL) {
1137 /* clearing stall is not needed */
1138 return;
1139 }
1140 /* select endpoint number */
1141 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1142
1143 /* set endpoint reset */
1144 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1145
1146 /* clear endpoint reset */
1147 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1148
1149 /* set stall */
1150 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1151 ATMEGA_UECONX_EPEN |
1152 ATMEGA_UECONX_STALLRQ);
1153
1154 /* reset data toggle */
1155 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1156 ATMEGA_UECONX_EPEN |
1157 ATMEGA_UECONX_RSTDT);
1158
1159 /* clear stall */
1160 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1161 ATMEGA_UECONX_EPEN |
1162 ATMEGA_UECONX_STALLRQC);
1163
1164 do {
1165 if (ep_type == UE_BULK) {
1166 temp = ATMEGA_UECFG0X_EPTYPE2;
1167 } else if (ep_type == UE_INTERRUPT) {
1168 temp = ATMEGA_UECFG0X_EPTYPE3;
1169 } else {
1170 temp = ATMEGA_UECFG0X_EPTYPE1;
1171 }
1172 if (ep_dir & UE_DIR_IN) {
1173 temp |= ATMEGA_UECFG0X_EPDIR;
1174 }
1175 /* two banks, 64-bytes wMaxPacket */
1176 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1177 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1178 ATMEGA_UECFG1X_ALLOC |
1179 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1180 ATMEGA_UECFG1X_EPSIZE(3));
1181
1182 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1183 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1184 device_printf(sc->sc_bus.bdev,
1185 "Chip rejected configuration\n");
1186 }
1187 } while (0);
1188 }
1189
1190 static void
atmegadci_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)1191 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1192 {
1193 struct atmegadci_softc *sc;
1194 struct usb_endpoint_descriptor *ed;
1195
1196 DPRINTFN(5, "endpoint=%p\n", ep);
1197
1198 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1199
1200 /* check mode */
1201 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1202 /* not supported */
1203 return;
1204 }
1205 /* get softc */
1206 sc = ATMEGA_BUS2SC(udev->bus);
1207
1208 /* get endpoint descriptor */
1209 ed = ep->edesc;
1210
1211 /* reset endpoint */
1212 atmegadci_clear_stall_sub(sc,
1213 (ed->bEndpointAddress & UE_ADDR),
1214 (ed->bmAttributes & UE_XFERTYPE),
1215 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1216 }
1217
1218 usb_error_t
atmegadci_init(struct atmegadci_softc * sc)1219 atmegadci_init(struct atmegadci_softc *sc)
1220 {
1221 uint8_t n;
1222
1223 DPRINTF("start\n");
1224
1225 /* set up the bus structure */
1226 sc->sc_bus.usbrev = USB_REV_1_1;
1227 sc->sc_bus.methods = &atmegadci_bus_methods;
1228
1229 USB_BUS_LOCK(&sc->sc_bus);
1230
1231 /* make sure USB is enabled */
1232 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1233 ATMEGA_USBCON_USBE |
1234 ATMEGA_USBCON_FRZCLK);
1235
1236 /* enable USB PAD regulator */
1237 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1238 ATMEGA_UHWCON_UVREGE |
1239 ATMEGA_UHWCON_UIMOD);
1240
1241 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1242 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1243
1244 /* wait for PLL to lock */
1245 for (n = 0; n != 20; n++) {
1246 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1247 break;
1248 /* wait a little bit for PLL to start */
1249 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1250 }
1251
1252 /* make sure USB is enabled */
1253 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1254 ATMEGA_USBCON_USBE |
1255 ATMEGA_USBCON_OTGPADE |
1256 ATMEGA_USBCON_VBUSTE);
1257
1258 /* turn on clocks */
1259 (sc->sc_clocks_on) (&sc->sc_bus);
1260
1261 /* make sure device is re-enumerated */
1262 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1263
1264 /* wait a little for things to stabilise */
1265 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1266
1267 /* enable interrupts */
1268 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1269 ATMEGA_UDINT_SUSPE |
1270 ATMEGA_UDINT_EORSTE);
1271
1272 /* reset all endpoints */
1273 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1274 (1 << ATMEGA_EP_MAX) - 1);
1275
1276 /* disable reset */
1277 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1278
1279 /* disable all endpoints */
1280 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1281 /* select endpoint */
1282 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1283
1284 /* disable endpoint interrupt */
1285 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1286
1287 /* disable endpoint */
1288 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1289 }
1290
1291 /* turn off clocks */
1292
1293 atmegadci_clocks_off(sc);
1294
1295 /* read initial VBUS state */
1296
1297 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1298 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1299
1300 USB_BUS_UNLOCK(&sc->sc_bus);
1301
1302 /* catch any lost interrupts */
1303
1304 atmegadci_do_poll(&sc->sc_bus);
1305
1306 return (0); /* success */
1307 }
1308
1309 void
atmegadci_uninit(struct atmegadci_softc * sc)1310 atmegadci_uninit(struct atmegadci_softc *sc)
1311 {
1312 USB_BUS_LOCK(&sc->sc_bus);
1313
1314 /* turn on clocks */
1315 (sc->sc_clocks_on) (&sc->sc_bus);
1316
1317 /* disable interrupts */
1318 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1319
1320 /* reset all endpoints */
1321 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1322 (1 << ATMEGA_EP_MAX) - 1);
1323
1324 /* disable reset */
1325 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1326
1327 sc->sc_flags.port_powered = 0;
1328 sc->sc_flags.status_vbus = 0;
1329 sc->sc_flags.status_bus_reset = 0;
1330 sc->sc_flags.status_suspend = 0;
1331 sc->sc_flags.change_suspend = 0;
1332 sc->sc_flags.change_connect = 1;
1333
1334 atmegadci_pull_down(sc);
1335 atmegadci_clocks_off(sc);
1336
1337 /* disable USB PAD regulator */
1338 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1339
1340 USB_BUS_UNLOCK(&sc->sc_bus);
1341 }
1342
1343 static void
atmegadci_suspend(struct atmegadci_softc * sc)1344 atmegadci_suspend(struct atmegadci_softc *sc)
1345 {
1346 /* TODO */
1347 }
1348
1349 static void
atmegadci_resume(struct atmegadci_softc * sc)1350 atmegadci_resume(struct atmegadci_softc *sc)
1351 {
1352 /* TODO */
1353 }
1354
1355 static void
atmegadci_do_poll(struct usb_bus * bus)1356 atmegadci_do_poll(struct usb_bus *bus)
1357 {
1358 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1359
1360 USB_BUS_LOCK(&sc->sc_bus);
1361 atmegadci_interrupt_poll(sc);
1362 USB_BUS_UNLOCK(&sc->sc_bus);
1363 }
1364
1365 /*------------------------------------------------------------------------*
1366 * atmegadci bulk support
1367 * atmegadci control support
1368 * atmegadci interrupt support
1369 *------------------------------------------------------------------------*/
1370 static void
atmegadci_device_non_isoc_open(struct usb_xfer * xfer)1371 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1372 {
1373 return;
1374 }
1375
1376 static void
atmegadci_device_non_isoc_close(struct usb_xfer * xfer)1377 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1378 {
1379 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1380 }
1381
1382 static void
atmegadci_device_non_isoc_enter(struct usb_xfer * xfer)1383 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1384 {
1385 return;
1386 }
1387
1388 static void
atmegadci_device_non_isoc_start(struct usb_xfer * xfer)1389 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1390 {
1391 /* setup TDs */
1392 atmegadci_setup_standard_chain(xfer);
1393 atmegadci_start_standard_chain(xfer);
1394 }
1395
1396 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1397 {
1398 .open = atmegadci_device_non_isoc_open,
1399 .close = atmegadci_device_non_isoc_close,
1400 .enter = atmegadci_device_non_isoc_enter,
1401 .start = atmegadci_device_non_isoc_start,
1402 };
1403
1404 /*------------------------------------------------------------------------*
1405 * atmegadci full speed isochronous support
1406 *------------------------------------------------------------------------*/
1407 static void
atmegadci_device_isoc_fs_open(struct usb_xfer * xfer)1408 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1409 {
1410 return;
1411 }
1412
1413 static void
atmegadci_device_isoc_fs_close(struct usb_xfer * xfer)1414 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1415 {
1416 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1417 }
1418
1419 static void
atmegadci_device_isoc_fs_enter(struct usb_xfer * xfer)1420 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1421 {
1422 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1423 uint32_t nframes;
1424
1425 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1426 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1427
1428 /* get the current frame index */
1429
1430 nframes =
1431 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1432 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1433
1434 if (usbd_xfer_get_isochronous_start_frame(
1435 xfer, nframes, 0, 1, ATMEGA_FRAME_MASK, NULL))
1436 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1437
1438 /* setup TDs */
1439 atmegadci_setup_standard_chain(xfer);
1440 }
1441
1442 static void
atmegadci_device_isoc_fs_start(struct usb_xfer * xfer)1443 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1444 {
1445 /* start TD chain */
1446 atmegadci_start_standard_chain(xfer);
1447 }
1448
1449 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1450 {
1451 .open = atmegadci_device_isoc_fs_open,
1452 .close = atmegadci_device_isoc_fs_close,
1453 .enter = atmegadci_device_isoc_fs_enter,
1454 .start = atmegadci_device_isoc_fs_start,
1455 };
1456
1457 /*------------------------------------------------------------------------*
1458 * atmegadci root control support
1459 *------------------------------------------------------------------------*
1460 * Simulate a hardware HUB by handling all the necessary requests.
1461 *------------------------------------------------------------------------*/
1462
1463 static const struct usb_device_descriptor atmegadci_devd = {
1464 .bLength = sizeof(struct usb_device_descriptor),
1465 .bDescriptorType = UDESC_DEVICE,
1466 .bcdUSB = {0x00, 0x02},
1467 .bDeviceClass = UDCLASS_HUB,
1468 .bDeviceSubClass = UDSUBCLASS_HUB,
1469 .bDeviceProtocol = UDPROTO_FSHUB,
1470 .bMaxPacketSize = 64,
1471 .bcdDevice = {0x00, 0x01},
1472 .iManufacturer = 1,
1473 .iProduct = 2,
1474 .bNumConfigurations = 1,
1475 };
1476
1477 static const struct atmegadci_config_desc atmegadci_confd = {
1478 .confd = {
1479 .bLength = sizeof(struct usb_config_descriptor),
1480 .bDescriptorType = UDESC_CONFIG,
1481 .wTotalLength[0] = sizeof(atmegadci_confd),
1482 .bNumInterface = 1,
1483 .bConfigurationValue = 1,
1484 .iConfiguration = 0,
1485 .bmAttributes = UC_SELF_POWERED,
1486 .bMaxPower = 0,
1487 },
1488 .ifcd = {
1489 .bLength = sizeof(struct usb_interface_descriptor),
1490 .bDescriptorType = UDESC_INTERFACE,
1491 .bNumEndpoints = 1,
1492 .bInterfaceClass = UICLASS_HUB,
1493 .bInterfaceSubClass = UISUBCLASS_HUB,
1494 .bInterfaceProtocol = 0,
1495 },
1496 .endpd = {
1497 .bLength = sizeof(struct usb_endpoint_descriptor),
1498 .bDescriptorType = UDESC_ENDPOINT,
1499 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1500 .bmAttributes = UE_INTERRUPT,
1501 .wMaxPacketSize[0] = 8,
1502 .bInterval = 255,
1503 },
1504 };
1505 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1506
1507 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1508 .bDescLength = sizeof(atmegadci_hubd),
1509 .bDescriptorType = UDESC_HUB,
1510 .bNbrPorts = 1,
1511 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1512 .bPwrOn2PwrGood = 50,
1513 .bHubContrCurrent = 0,
1514 .DeviceRemovable = {0}, /* port is removable */
1515 };
1516
1517 #define STRING_VENDOR \
1518 "A\0T\0M\0E\0G\0A"
1519
1520 #define STRING_PRODUCT \
1521 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1522
1523 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1524 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1525
1526 static usb_error_t
atmegadci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)1527 atmegadci_roothub_exec(struct usb_device *udev,
1528 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1529 {
1530 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1531 const void *ptr;
1532 uint16_t len;
1533 uint16_t value;
1534 uint16_t index;
1535 uint8_t temp;
1536 usb_error_t err;
1537
1538 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1539
1540 /* buffer reset */
1541 ptr = (const void *)&sc->sc_hub_temp;
1542 len = 0;
1543 err = 0;
1544
1545 value = UGETW(req->wValue);
1546 index = UGETW(req->wIndex);
1547
1548 /* demultiplex the control request */
1549
1550 switch (req->bmRequestType) {
1551 case UT_READ_DEVICE:
1552 switch (req->bRequest) {
1553 case UR_GET_DESCRIPTOR:
1554 goto tr_handle_get_descriptor;
1555 case UR_GET_CONFIG:
1556 goto tr_handle_get_config;
1557 case UR_GET_STATUS:
1558 goto tr_handle_get_status;
1559 default:
1560 goto tr_stalled;
1561 }
1562 break;
1563
1564 case UT_WRITE_DEVICE:
1565 switch (req->bRequest) {
1566 case UR_SET_ADDRESS:
1567 goto tr_handle_set_address;
1568 case UR_SET_CONFIG:
1569 goto tr_handle_set_config;
1570 case UR_CLEAR_FEATURE:
1571 goto tr_valid; /* nop */
1572 case UR_SET_DESCRIPTOR:
1573 goto tr_valid; /* nop */
1574 case UR_SET_FEATURE:
1575 default:
1576 goto tr_stalled;
1577 }
1578 break;
1579
1580 case UT_WRITE_ENDPOINT:
1581 switch (req->bRequest) {
1582 case UR_CLEAR_FEATURE:
1583 switch (UGETW(req->wValue)) {
1584 case UF_ENDPOINT_HALT:
1585 goto tr_handle_clear_halt;
1586 case UF_DEVICE_REMOTE_WAKEUP:
1587 goto tr_handle_clear_wakeup;
1588 default:
1589 goto tr_stalled;
1590 }
1591 break;
1592 case UR_SET_FEATURE:
1593 switch (UGETW(req->wValue)) {
1594 case UF_ENDPOINT_HALT:
1595 goto tr_handle_set_halt;
1596 case UF_DEVICE_REMOTE_WAKEUP:
1597 goto tr_handle_set_wakeup;
1598 default:
1599 goto tr_stalled;
1600 }
1601 break;
1602 case UR_SYNCH_FRAME:
1603 goto tr_valid; /* nop */
1604 default:
1605 goto tr_stalled;
1606 }
1607 break;
1608
1609 case UT_READ_ENDPOINT:
1610 switch (req->bRequest) {
1611 case UR_GET_STATUS:
1612 goto tr_handle_get_ep_status;
1613 default:
1614 goto tr_stalled;
1615 }
1616 break;
1617
1618 case UT_WRITE_INTERFACE:
1619 switch (req->bRequest) {
1620 case UR_SET_INTERFACE:
1621 goto tr_handle_set_interface;
1622 case UR_CLEAR_FEATURE:
1623 goto tr_valid; /* nop */
1624 case UR_SET_FEATURE:
1625 default:
1626 goto tr_stalled;
1627 }
1628 break;
1629
1630 case UT_READ_INTERFACE:
1631 switch (req->bRequest) {
1632 case UR_GET_INTERFACE:
1633 goto tr_handle_get_interface;
1634 case UR_GET_STATUS:
1635 goto tr_handle_get_iface_status;
1636 default:
1637 goto tr_stalled;
1638 }
1639 break;
1640
1641 case UT_WRITE_CLASS_INTERFACE:
1642 case UT_WRITE_VENDOR_INTERFACE:
1643 /* XXX forward */
1644 break;
1645
1646 case UT_READ_CLASS_INTERFACE:
1647 case UT_READ_VENDOR_INTERFACE:
1648 /* XXX forward */
1649 break;
1650
1651 case UT_WRITE_CLASS_DEVICE:
1652 switch (req->bRequest) {
1653 case UR_CLEAR_FEATURE:
1654 goto tr_valid;
1655 case UR_SET_DESCRIPTOR:
1656 case UR_SET_FEATURE:
1657 break;
1658 default:
1659 goto tr_stalled;
1660 }
1661 break;
1662
1663 case UT_WRITE_CLASS_OTHER:
1664 switch (req->bRequest) {
1665 case UR_CLEAR_FEATURE:
1666 goto tr_handle_clear_port_feature;
1667 case UR_SET_FEATURE:
1668 goto tr_handle_set_port_feature;
1669 case UR_CLEAR_TT_BUFFER:
1670 case UR_RESET_TT:
1671 case UR_STOP_TT:
1672 goto tr_valid;
1673
1674 default:
1675 goto tr_stalled;
1676 }
1677 break;
1678
1679 case UT_READ_CLASS_OTHER:
1680 switch (req->bRequest) {
1681 case UR_GET_TT_STATE:
1682 goto tr_handle_get_tt_state;
1683 case UR_GET_STATUS:
1684 goto tr_handle_get_port_status;
1685 default:
1686 goto tr_stalled;
1687 }
1688 break;
1689
1690 case UT_READ_CLASS_DEVICE:
1691 switch (req->bRequest) {
1692 case UR_GET_DESCRIPTOR:
1693 goto tr_handle_get_class_descriptor;
1694 case UR_GET_STATUS:
1695 goto tr_handle_get_class_status;
1696
1697 default:
1698 goto tr_stalled;
1699 }
1700 break;
1701 default:
1702 goto tr_stalled;
1703 }
1704 goto tr_valid;
1705
1706 tr_handle_get_descriptor:
1707 switch (value >> 8) {
1708 case UDESC_DEVICE:
1709 if (value & 0xff) {
1710 goto tr_stalled;
1711 }
1712 len = sizeof(atmegadci_devd);
1713 ptr = (const void *)&atmegadci_devd;
1714 goto tr_valid;
1715 case UDESC_CONFIG:
1716 if (value & 0xff) {
1717 goto tr_stalled;
1718 }
1719 len = sizeof(atmegadci_confd);
1720 ptr = (const void *)&atmegadci_confd;
1721 goto tr_valid;
1722 case UDESC_STRING:
1723 switch (value & 0xff) {
1724 case 0: /* Language table */
1725 len = sizeof(usb_string_lang_en);
1726 ptr = (const void *)&usb_string_lang_en;
1727 goto tr_valid;
1728
1729 case 1: /* Vendor */
1730 len = sizeof(atmegadci_vendor);
1731 ptr = (const void *)&atmegadci_vendor;
1732 goto tr_valid;
1733
1734 case 2: /* Product */
1735 len = sizeof(atmegadci_product);
1736 ptr = (const void *)&atmegadci_product;
1737 goto tr_valid;
1738 default:
1739 break;
1740 }
1741 break;
1742 default:
1743 goto tr_stalled;
1744 }
1745 goto tr_stalled;
1746
1747 tr_handle_get_config:
1748 len = 1;
1749 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1750 goto tr_valid;
1751
1752 tr_handle_get_status:
1753 len = 2;
1754 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1755 goto tr_valid;
1756
1757 tr_handle_set_address:
1758 if (value & 0xFF00) {
1759 goto tr_stalled;
1760 }
1761 sc->sc_rt_addr = value;
1762 goto tr_valid;
1763
1764 tr_handle_set_config:
1765 if (value >= 2) {
1766 goto tr_stalled;
1767 }
1768 sc->sc_conf = value;
1769 goto tr_valid;
1770
1771 tr_handle_get_interface:
1772 len = 1;
1773 sc->sc_hub_temp.wValue[0] = 0;
1774 goto tr_valid;
1775
1776 tr_handle_get_tt_state:
1777 tr_handle_get_class_status:
1778 tr_handle_get_iface_status:
1779 tr_handle_get_ep_status:
1780 len = 2;
1781 USETW(sc->sc_hub_temp.wValue, 0);
1782 goto tr_valid;
1783
1784 tr_handle_set_halt:
1785 tr_handle_set_interface:
1786 tr_handle_set_wakeup:
1787 tr_handle_clear_wakeup:
1788 tr_handle_clear_halt:
1789 goto tr_valid;
1790
1791 tr_handle_clear_port_feature:
1792 if (index != 1) {
1793 goto tr_stalled;
1794 }
1795 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1796
1797 switch (value) {
1798 case UHF_PORT_SUSPEND:
1799 atmegadci_wakeup_peer(sc);
1800 break;
1801
1802 case UHF_PORT_ENABLE:
1803 sc->sc_flags.port_enabled = 0;
1804 break;
1805
1806 case UHF_PORT_TEST:
1807 case UHF_PORT_INDICATOR:
1808 case UHF_C_PORT_ENABLE:
1809 case UHF_C_PORT_OVER_CURRENT:
1810 case UHF_C_PORT_RESET:
1811 /* nops */
1812 break;
1813 case UHF_PORT_POWER:
1814 sc->sc_flags.port_powered = 0;
1815 atmegadci_pull_down(sc);
1816 atmegadci_clocks_off(sc);
1817 break;
1818 case UHF_C_PORT_CONNECTION:
1819 /* clear connect change flag */
1820 sc->sc_flags.change_connect = 0;
1821
1822 if (!sc->sc_flags.status_bus_reset) {
1823 /* we are not connected */
1824 break;
1825 }
1826
1827 /* configure the control endpoint */
1828
1829 /* select endpoint number */
1830 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1831
1832 /* set endpoint reset */
1833 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1834
1835 /* clear endpoint reset */
1836 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1837
1838 /* enable and stall endpoint */
1839 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1840 ATMEGA_UECONX_EPEN |
1841 ATMEGA_UECONX_STALLRQ);
1842
1843 /* one bank, 64-bytes wMaxPacket */
1844 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1845 ATMEGA_UECFG0X_EPTYPE0);
1846 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1847 ATMEGA_UECFG1X_ALLOC |
1848 ATMEGA_UECFG1X_EPBK0 |
1849 ATMEGA_UECFG1X_EPSIZE(3));
1850
1851 /* check valid config */
1852 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1853 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1854 device_printf(sc->sc_bus.bdev,
1855 "Chip rejected EP0 configuration\n");
1856 }
1857 break;
1858 case UHF_C_PORT_SUSPEND:
1859 sc->sc_flags.change_suspend = 0;
1860 break;
1861 default:
1862 err = USB_ERR_IOERROR;
1863 goto done;
1864 }
1865 goto tr_valid;
1866
1867 tr_handle_set_port_feature:
1868 if (index != 1) {
1869 goto tr_stalled;
1870 }
1871 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1872
1873 switch (value) {
1874 case UHF_PORT_ENABLE:
1875 sc->sc_flags.port_enabled = 1;
1876 break;
1877 case UHF_PORT_SUSPEND:
1878 case UHF_PORT_RESET:
1879 case UHF_PORT_TEST:
1880 case UHF_PORT_INDICATOR:
1881 /* nops */
1882 break;
1883 case UHF_PORT_POWER:
1884 sc->sc_flags.port_powered = 1;
1885 break;
1886 default:
1887 err = USB_ERR_IOERROR;
1888 goto done;
1889 }
1890 goto tr_valid;
1891
1892 tr_handle_get_port_status:
1893
1894 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1895
1896 if (index != 1) {
1897 goto tr_stalled;
1898 }
1899 if (sc->sc_flags.status_vbus) {
1900 atmegadci_clocks_on(sc);
1901 atmegadci_pull_up(sc);
1902 } else {
1903 atmegadci_pull_down(sc);
1904 atmegadci_clocks_off(sc);
1905 }
1906
1907 /* Select FULL-speed and Device Side Mode */
1908
1909 value = UPS_PORT_MODE_DEVICE;
1910
1911 if (sc->sc_flags.port_powered) {
1912 value |= UPS_PORT_POWER;
1913 }
1914 if (sc->sc_flags.port_enabled) {
1915 value |= UPS_PORT_ENABLED;
1916 }
1917 if (sc->sc_flags.status_vbus &&
1918 sc->sc_flags.status_bus_reset) {
1919 value |= UPS_CURRENT_CONNECT_STATUS;
1920 }
1921 if (sc->sc_flags.status_suspend) {
1922 value |= UPS_SUSPEND;
1923 }
1924 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1925
1926 value = 0;
1927
1928 if (sc->sc_flags.change_connect) {
1929 value |= UPS_C_CONNECT_STATUS;
1930 }
1931 if (sc->sc_flags.change_suspend) {
1932 value |= UPS_C_SUSPEND;
1933 }
1934 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1935 len = sizeof(sc->sc_hub_temp.ps);
1936 goto tr_valid;
1937
1938 tr_handle_get_class_descriptor:
1939 if (value & 0xFF) {
1940 goto tr_stalled;
1941 }
1942 ptr = (const void *)&atmegadci_hubd;
1943 len = sizeof(atmegadci_hubd);
1944 goto tr_valid;
1945
1946 tr_stalled:
1947 err = USB_ERR_STALLED;
1948 tr_valid:
1949 done:
1950 *plength = len;
1951 *pptr = ptr;
1952 return (err);
1953 }
1954
1955 static void
atmegadci_xfer_setup(struct usb_setup_params * parm)1956 atmegadci_xfer_setup(struct usb_setup_params *parm)
1957 {
1958 const struct usb_hw_ep_profile *pf;
1959 struct atmegadci_softc *sc;
1960 struct usb_xfer *xfer;
1961 void *last_obj;
1962 uint32_t ntd;
1963 uint32_t n;
1964 uint8_t ep_no;
1965
1966 sc = ATMEGA_BUS2SC(parm->udev->bus);
1967 xfer = parm->curr_xfer;
1968
1969 /*
1970 * NOTE: This driver does not use any of the parameters that
1971 * are computed from the following values. Just set some
1972 * reasonable dummies:
1973 */
1974 parm->hc_max_packet_size = 0x500;
1975 parm->hc_max_packet_count = 1;
1976 parm->hc_max_frame_size = 0x500;
1977
1978 usbd_transfer_setup_sub(parm);
1979
1980 /*
1981 * compute maximum number of TDs
1982 */
1983 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1984 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
1985 + 1 /* SYNC 2 */ ;
1986 } else {
1987 ntd = xfer->nframes + 1 /* SYNC */ ;
1988 }
1989
1990 /*
1991 * check if "usbd_transfer_setup_sub" set an error
1992 */
1993 if (parm->err)
1994 return;
1995
1996 /*
1997 * allocate transfer descriptors
1998 */
1999 last_obj = NULL;
2000
2001 /*
2002 * get profile stuff
2003 */
2004 ep_no = xfer->endpointno & UE_ADDR;
2005 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2006
2007 if (pf == NULL) {
2008 /* should not happen */
2009 parm->err = USB_ERR_INVAL;
2010 return;
2011 }
2012
2013 /* align data */
2014 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2015
2016 for (n = 0; n != ntd; n++) {
2017 struct atmegadci_td *td;
2018
2019 if (parm->buf) {
2020 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2021
2022 /* init TD */
2023 td->max_packet_size = xfer->max_packet_size;
2024 td->ep_no = ep_no;
2025 if (pf->support_multi_buffer) {
2026 td->support_multi_buffer = 1;
2027 }
2028 td->obj_next = last_obj;
2029
2030 last_obj = td;
2031 }
2032 parm->size[0] += sizeof(*td);
2033 }
2034
2035 xfer->td_start[0] = last_obj;
2036 }
2037
2038 static void
atmegadci_xfer_unsetup(struct usb_xfer * xfer)2039 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2040 {
2041 return;
2042 }
2043
2044 static void
atmegadci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)2045 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2046 struct usb_endpoint *ep)
2047 {
2048 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2049
2050 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2051 ep, udev->address,
2052 edesc->bEndpointAddress, udev->flags.usb_mode,
2053 sc->sc_rt_addr, udev->device_index);
2054
2055 if (udev->device_index != sc->sc_rt_addr) {
2056 if (udev->speed != USB_SPEED_FULL) {
2057 /* not supported */
2058 return;
2059 }
2060 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2061 ep->methods = &atmegadci_device_isoc_fs_methods;
2062 else
2063 ep->methods = &atmegadci_device_non_isoc_methods;
2064 }
2065 }
2066
2067 static void
atmegadci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)2068 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2069 {
2070 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2071
2072 switch (state) {
2073 case USB_HW_POWER_SUSPEND:
2074 atmegadci_suspend(sc);
2075 break;
2076 case USB_HW_POWER_SHUTDOWN:
2077 atmegadci_uninit(sc);
2078 break;
2079 case USB_HW_POWER_RESUME:
2080 atmegadci_resume(sc);
2081 break;
2082 default:
2083 break;
2084 }
2085 }
2086
2087 static const struct usb_bus_methods atmegadci_bus_methods =
2088 {
2089 .endpoint_init = &atmegadci_ep_init,
2090 .xfer_setup = &atmegadci_xfer_setup,
2091 .xfer_unsetup = &atmegadci_xfer_unsetup,
2092 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2093 .xfer_stall = &atmegadci_xfer_stall,
2094 .set_stall = &atmegadci_set_stall,
2095 .clear_stall = &atmegadci_clear_stall,
2096 .roothub_exec = &atmegadci_roothub_exec,
2097 .xfer_poll = &atmegadci_do_poll,
2098 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,
2099 };
2100