1 /*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ppc.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/interrupt.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/proc.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <sys/rman.h> 45 46 #ifdef __i386__ 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <machine/vmparam.h> 50 #endif 51 52 #include <dev/ppbus/ppbconf.h> 53 #include <dev/ppbus/ppb_msq.h> 54 55 #include <dev/ppc/ppcvar.h> 56 #include <dev/ppc/ppcreg.h> 57 58 #include "ppbus_if.h" 59 60 static void ppcintr(void *arg); 61 62 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 63 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 64 65 #define LOG_PPC(function, ppc, string) \ 66 if (bootverbose) printf("%s: %s\n", function, string) 67 68 #if defined(__i386__) && defined(PC98) 69 #define PC98_IEEE_1284_DISABLE 0x100 70 #define PC98_IEEE_1284_PORT 0x140 71 #endif 72 73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 74 75 devclass_t ppc_devclass; 76 const char ppc_driver_name[] = "ppc"; 77 78 static char *ppc_models[] = { 79 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 80 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 81 "SMC FDC37C935", "PC87303", 0 82 }; 83 84 /* list of available modes */ 85 static char *ppc_avms[] = { 86 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 87 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 88 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 89 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 90 }; 91 92 /* list of current executing modes 93 * Note that few modes do not actually exist. 94 */ 95 static char *ppc_modes[] = { 96 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 97 "EPP", "EPP", "EPP", "ECP", 98 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 99 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 100 }; 101 102 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 103 104 #ifdef __i386__ 105 /* 106 * BIOS printer list - used by BIOS probe. 107 */ 108 #define BIOS_PPC_PORTS 0x408 109 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 110 #define BIOS_MAX_PPC 4 111 #endif 112 113 /* 114 * ppc_ecp_sync() XXX 115 */ 116 void 117 ppc_ecp_sync(device_t dev) { 118 119 int i, r; 120 struct ppc_data *ppc = DEVTOSOFTC(dev); 121 122 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 123 return; 124 125 r = r_ecr(ppc); 126 if ((r & 0xe0) != PPC_ECR_EPP) 127 return; 128 129 for (i = 0; i < 100; i++) { 130 r = r_ecr(ppc); 131 if (r & 0x1) 132 return; 133 DELAY(100); 134 } 135 136 device_printf(dev, "ECP sync failed as data still present in FIFO.\n"); 137 138 return; 139 } 140 141 /* 142 * ppc_detect_fifo() 143 * 144 * Detect parallel port FIFO 145 */ 146 static int 147 ppc_detect_fifo(struct ppc_data *ppc) 148 { 149 char ecr_sav; 150 char ctr_sav, ctr, cc; 151 short i; 152 153 /* save registers */ 154 ecr_sav = r_ecr(ppc); 155 ctr_sav = r_ctr(ppc); 156 157 /* enter ECP configuration mode, no interrupt, no DMA */ 158 w_ecr(ppc, 0xf4); 159 160 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 161 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 162 163 /* XXX 16 and 32 bits implementations not supported */ 164 if (ppc->ppc_pword != PPC_PWORD_8) { 165 LOG_PPC(__func__, ppc, "PWord not supported"); 166 goto error; 167 } 168 169 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 170 ctr = r_ctr(ppc); 171 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 172 173 /* enter ECP test mode, no interrupt, no DMA */ 174 w_ecr(ppc, 0xd4); 175 176 /* flush the FIFO */ 177 for (i=0; i<1024; i++) { 178 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 179 break; 180 cc = r_fifo(ppc); 181 } 182 183 if (i >= 1024) { 184 LOG_PPC(__func__, ppc, "can't flush FIFO"); 185 goto error; 186 } 187 188 /* enable interrupts, no DMA */ 189 w_ecr(ppc, 0xd0); 190 191 /* determine readIntrThreshold 192 * fill the FIFO until serviceIntr is set 193 */ 194 for (i=0; i<1024; i++) { 195 w_fifo(ppc, (char)i); 196 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 197 /* readThreshold reached */ 198 ppc->ppc_rthr = i+1; 199 } 200 if (r_ecr(ppc) & PPC_FIFO_FULL) { 201 ppc->ppc_fifo = i+1; 202 break; 203 } 204 } 205 206 if (i >= 1024) { 207 LOG_PPC(__func__, ppc, "can't fill FIFO"); 208 goto error; 209 } 210 211 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 212 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 213 w_ecr(ppc, 0xd0); /* enable interrupts */ 214 215 /* determine writeIntrThreshold 216 * empty the FIFO until serviceIntr is set 217 */ 218 for (i=ppc->ppc_fifo; i>0; i--) { 219 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 220 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 221 goto error; 222 } 223 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 224 /* writeIntrThreshold reached */ 225 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 226 } 227 /* if FIFO empty before the last byte, error */ 228 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 229 LOG_PPC(__func__, ppc, "data lost in FIFO"); 230 goto error; 231 } 232 } 233 234 /* FIFO must be empty after the last byte */ 235 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 236 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 237 goto error; 238 } 239 240 w_ctr(ppc, ctr_sav); 241 w_ecr(ppc, ecr_sav); 242 243 return (0); 244 245 error: 246 w_ctr(ppc, ctr_sav); 247 w_ecr(ppc, ecr_sav); 248 249 return (EINVAL); 250 } 251 252 static int 253 ppc_detect_port(struct ppc_data *ppc) 254 { 255 256 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 257 w_dtr(ppc, 0xaa); 258 if (r_dtr(ppc) != 0xaa) 259 return (0); 260 261 return (1); 262 } 263 264 /* 265 * EPP timeout, according to the PC87332 manual 266 * Semantics of clearing EPP timeout bit. 267 * PC87332 - reading SPP_STR does it... 268 * SMC - write 1 to EPP timeout bit XXX 269 * Others - (?) write 0 to EPP timeout bit 270 */ 271 static void 272 ppc_reset_epp_timeout(struct ppc_data *ppc) 273 { 274 register char r; 275 276 r = r_str(ppc); 277 w_str(ppc, r | 0x1); 278 w_str(ppc, r & 0xfe); 279 280 return; 281 } 282 283 static int 284 ppc_check_epp_timeout(struct ppc_data *ppc) 285 { 286 ppc_reset_epp_timeout(ppc); 287 288 return (!(r_str(ppc) & TIMEOUT)); 289 } 290 291 /* 292 * Configure current operating mode 293 */ 294 static int 295 ppc_generic_setmode(struct ppc_data *ppc, int mode) 296 { 297 u_char ecr = 0; 298 299 /* check if mode is available */ 300 if (mode && !(ppc->ppc_avm & mode)) 301 return (EINVAL); 302 303 /* if ECP mode, configure ecr register */ 304 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 305 /* return to byte mode (keeping direction bit), 306 * no interrupt, no DMA to be able to change to 307 * ECP 308 */ 309 w_ecr(ppc, PPC_ECR_RESET); 310 ecr = PPC_DISABLE_INTR; 311 312 if (mode & PPB_EPP) 313 return (EINVAL); 314 else if (mode & PPB_ECP) 315 /* select ECP mode */ 316 ecr |= PPC_ECR_ECP; 317 else if (mode & PPB_PS2) 318 /* select PS2 mode with ECP */ 319 ecr |= PPC_ECR_PS2; 320 else 321 /* select COMPATIBLE/NIBBLE mode */ 322 ecr |= PPC_ECR_STD; 323 324 w_ecr(ppc, ecr); 325 } 326 327 ppc->ppc_mode = mode; 328 329 return (0); 330 } 331 332 /* 333 * The ppc driver is free to choose options like FIFO or DMA 334 * if ECP mode is available. 335 * 336 * The 'RAW' option allows the upper drivers to force the ppc mode 337 * even with FIFO, DMA available. 338 */ 339 static int 340 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 341 { 342 u_char ecr = 0; 343 344 /* check if mode is available */ 345 if (mode && !(ppc->ppc_avm & mode)) 346 return (EINVAL); 347 348 /* if ECP mode, configure ecr register */ 349 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 350 /* return to byte mode (keeping direction bit), 351 * no interrupt, no DMA to be able to change to 352 * ECP or EPP mode 353 */ 354 w_ecr(ppc, PPC_ECR_RESET); 355 ecr = PPC_DISABLE_INTR; 356 357 if (mode & PPB_EPP) 358 /* select EPP mode */ 359 ecr |= PPC_ECR_EPP; 360 else if (mode & PPB_ECP) 361 /* select ECP mode */ 362 ecr |= PPC_ECR_ECP; 363 else if (mode & PPB_PS2) 364 /* select PS2 mode with ECP */ 365 ecr |= PPC_ECR_PS2; 366 else 367 /* select COMPATIBLE/NIBBLE mode */ 368 ecr |= PPC_ECR_STD; 369 370 w_ecr(ppc, ecr); 371 } 372 373 ppc->ppc_mode = mode; 374 375 return (0); 376 } 377 378 #ifdef PPC_PROBE_CHIPSET 379 /* 380 * ppc_pc873xx_detect 381 * 382 * Probe for a Natsemi PC873xx-family part. 383 * 384 * References in this function are to the National Semiconductor 385 * PC87332 datasheet TL/C/11930, May 1995 revision. 386 */ 387 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 388 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 389 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 390 391 static int pc873xx_regstab[] = { 392 PC873_FER, PC873_FAR, PC873_PTR, 393 PC873_FCR, PC873_PCR, PC873_PMC, 394 PC873_TUP, PC873_SID, PC873_PNP0, 395 PC873_PNP1, PC873_LPTBA, -1 396 }; 397 398 static char *pc873xx_rnametab[] = { 399 "FER", "FAR", "PTR", "FCR", "PCR", 400 "PMC", "TUP", "SID", "PNP0", "PNP1", 401 "LPTBA", NULL 402 }; 403 404 static int 405 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 406 { 407 static int index = 0; 408 int idport, irq; 409 int ptr, pcr, val, i; 410 411 while ((idport = pc873xx_basetab[index++])) { 412 413 /* XXX should check first to see if this location is already claimed */ 414 415 /* 416 * Pull the 873xx through the power-on ID cycle (2.2,1.). 417 * We can't use this to locate the chip as it may already have 418 * been used by the BIOS. 419 */ 420 (void)inb(idport); (void)inb(idport); 421 (void)inb(idport); (void)inb(idport); 422 423 /* 424 * Read the SID byte. Possible values are : 425 * 426 * 01010xxx PC87334 427 * 0001xxxx PC87332 428 * 01110xxx PC87306 429 * 00110xxx PC87303 430 */ 431 outb(idport, PC873_SID); 432 val = inb(idport + 1); 433 if ((val & 0xf0) == 0x10) { 434 ppc->ppc_model = NS_PC87332; 435 } else if ((val & 0xf8) == 0x70) { 436 ppc->ppc_model = NS_PC87306; 437 } else if ((val & 0xf8) == 0x50) { 438 ppc->ppc_model = NS_PC87334; 439 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 440 documentation, but probing 441 yielded 0x40... */ 442 ppc->ppc_model = NS_PC87303; 443 } else { 444 if (bootverbose && (val != 0xff)) 445 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 446 continue ; /* not recognised */ 447 } 448 449 /* print registers */ 450 if (bootverbose) { 451 printf("PC873xx"); 452 for (i=0; pc873xx_regstab[i] != -1; i++) { 453 outb(idport, pc873xx_regstab[i]); 454 printf(" %s=0x%x", pc873xx_rnametab[i], 455 inb(idport + 1) & 0xff); 456 } 457 printf("\n"); 458 } 459 460 /* 461 * We think we have one. Is it enabled and where we want it to be? 462 */ 463 outb(idport, PC873_FER); 464 val = inb(idport + 1); 465 if (!(val & PC873_PPENABLE)) { 466 if (bootverbose) 467 printf("PC873xx parallel port disabled\n"); 468 continue; 469 } 470 outb(idport, PC873_FAR); 471 val = inb(idport + 1); 472 /* XXX we should create a driver instance for every port found */ 473 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 474 475 /* First try to change the port address to that requested... */ 476 477 switch(ppc->ppc_base) { 478 case 0x378: 479 val &= 0xfc; 480 break; 481 482 case 0x3bc: 483 val &= 0xfd; 484 break; 485 486 case 0x278: 487 val &= 0xfe; 488 break; 489 490 default: 491 val &= 0xfd; 492 break; 493 } 494 495 outb(idport, PC873_FAR); 496 outb(idport + 1, val); 497 outb(idport + 1, val); 498 499 /* Check for success by reading back the value we supposedly 500 wrote and comparing...*/ 501 502 outb(idport, PC873_FAR); 503 val = inb(idport + 1) & 0x3; 504 505 /* If we fail, report the failure... */ 506 507 if (pc873xx_porttab[val] != ppc->ppc_base) { 508 if (bootverbose) 509 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 510 pc873xx_porttab[val], ppc->ppc_base); 511 } 512 continue; 513 } 514 515 outb(idport, PC873_PTR); 516 ptr = inb(idport + 1); 517 518 /* get irq settings */ 519 if (ppc->ppc_base == 0x378) 520 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 521 else 522 irq = pc873xx_irqtab[val]; 523 524 if (bootverbose) 525 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 526 527 /* 528 * Check if irq settings are correct 529 */ 530 if (irq != ppc->ppc_irq) { 531 /* 532 * If the chipset is not locked and base address is 0x378, 533 * we have another chance 534 */ 535 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 536 if (ppc->ppc_irq == 7) { 537 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 538 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 539 } else { 540 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 541 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 542 } 543 if (bootverbose) 544 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 545 } else { 546 if (bootverbose) 547 printf("PC873xx sorry, can't change irq setting\n"); 548 } 549 } else { 550 if (bootverbose) 551 printf("PC873xx irq settings are correct\n"); 552 } 553 554 outb(idport, PC873_PCR); 555 pcr = inb(idport + 1); 556 557 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 558 if (bootverbose) 559 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 560 561 ppc->ppc_avm |= PPB_NIBBLE; 562 if (bootverbose) 563 printf(", NIBBLE"); 564 565 if (pcr & PC873_EPPEN) { 566 ppc->ppc_avm |= PPB_EPP; 567 568 if (bootverbose) 569 printf(", EPP"); 570 571 if (pcr & PC873_EPP19) 572 ppc->ppc_epp = EPP_1_9; 573 else 574 ppc->ppc_epp = EPP_1_7; 575 576 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 577 outb(idport, PC873_PTR); 578 ptr = inb(idport + 1); 579 if (ptr & PC873_EPPRDIR) 580 printf(", Regular mode"); 581 else 582 printf(", Automatic mode"); 583 } 584 } else if (pcr & PC873_ECPEN) { 585 ppc->ppc_avm |= PPB_ECP; 586 if (bootverbose) 587 printf(", ECP"); 588 589 if (pcr & PC873_ECPCLK) { /* XXX */ 590 ppc->ppc_avm |= PPB_PS2; 591 if (bootverbose) 592 printf(", PS/2"); 593 } 594 } else { 595 outb(idport, PC873_PTR); 596 ptr = inb(idport + 1); 597 if (ptr & PC873_EXTENDED) { 598 ppc->ppc_avm |= PPB_SPP; 599 if (bootverbose) 600 printf(", SPP"); 601 } 602 } 603 } else { 604 if (bootverbose) 605 printf("PC873xx unlocked"); 606 607 if (chipset_mode & PPB_ECP) { 608 if ((chipset_mode & PPB_EPP) && bootverbose) 609 printf(", ECP+EPP not supported"); 610 611 pcr &= ~PC873_EPPEN; 612 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 613 outb(idport + 1, pcr); 614 outb(idport + 1, pcr); 615 616 if (bootverbose) 617 printf(", ECP"); 618 619 } else if (chipset_mode & PPB_EPP) { 620 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 621 pcr |= (PC873_EPPEN | PC873_EPP19); 622 outb(idport + 1, pcr); 623 outb(idport + 1, pcr); 624 625 ppc->ppc_epp = EPP_1_9; /* XXX */ 626 627 if (bootverbose) 628 printf(", EPP1.9"); 629 630 /* enable automatic direction turnover */ 631 if (ppc->ppc_model == NS_PC87332) { 632 outb(idport, PC873_PTR); 633 ptr = inb(idport + 1); 634 ptr &= ~PC873_EPPRDIR; 635 outb(idport + 1, ptr); 636 outb(idport + 1, ptr); 637 638 if (bootverbose) 639 printf(", Automatic mode"); 640 } 641 } else { 642 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 643 outb(idport + 1, pcr); 644 outb(idport + 1, pcr); 645 646 /* configure extended bit in PTR */ 647 outb(idport, PC873_PTR); 648 ptr = inb(idport + 1); 649 650 if (chipset_mode & PPB_PS2) { 651 ptr |= PC873_EXTENDED; 652 653 if (bootverbose) 654 printf(", PS/2"); 655 656 } else { 657 /* default to NIBBLE mode */ 658 ptr &= ~PC873_EXTENDED; 659 660 if (bootverbose) 661 printf(", NIBBLE"); 662 } 663 outb(idport + 1, ptr); 664 outb(idport + 1, ptr); 665 } 666 667 ppc->ppc_avm = chipset_mode; 668 } 669 670 if (bootverbose) 671 printf("\n"); 672 673 ppc->ppc_type = PPC_TYPE_GENERIC; 674 ppc_generic_setmode(ppc, chipset_mode); 675 676 return(chipset_mode); 677 } 678 return(-1); 679 } 680 681 /* 682 * ppc_smc37c66xgt_detect 683 * 684 * SMC FDC37C66xGT configuration. 685 */ 686 static int 687 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 688 { 689 int s, i; 690 u_char r; 691 int type = -1; 692 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 693 694 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 695 696 697 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 698 699 /* 700 * Detection: enter configuration mode and read CRD register. 701 */ 702 703 s = splhigh(); 704 outb(csr, SMC665_iCODE); 705 outb(csr, SMC665_iCODE); 706 splx(s); 707 708 outb(csr, 0xd); 709 if (inb(cio) == 0x65) { 710 type = SMC_37C665GT; 711 goto config; 712 } 713 714 for (i = 0; i < 2; i++) { 715 s = splhigh(); 716 outb(csr, SMC666_iCODE); 717 outb(csr, SMC666_iCODE); 718 splx(s); 719 720 outb(csr, 0xd); 721 if (inb(cio) == 0x66) { 722 type = SMC_37C666GT; 723 break; 724 } 725 726 /* Another chance, CSR may be hard-configured to be at 0x370 */ 727 csr = SMC666_CSR; 728 } 729 730 config: 731 /* 732 * If chipset not found, do not continue. 733 */ 734 if (type == -1) 735 return (-1); 736 737 /* select CR1 */ 738 outb(csr, 0x1); 739 740 /* read the port's address: bits 0 and 1 of CR1 */ 741 r = inb(cio) & SMC_CR1_ADDR; 742 if (port_address[(int)r] != ppc->ppc_base) 743 return (-1); 744 745 ppc->ppc_model = type; 746 747 /* 748 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 749 * If SPP mode is detected, try to set ECP+EPP mode 750 */ 751 752 if (bootverbose) { 753 outb(csr, 0x1); 754 device_printf(dev, "SMC registers CR1=0x%x", inb(cio) & 0xff); 755 756 outb(csr, 0x4); 757 printf(" CR4=0x%x", inb(cio) & 0xff); 758 } 759 760 /* select CR1 */ 761 outb(csr, 0x1); 762 763 if (!chipset_mode) { 764 /* autodetect mode */ 765 766 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 767 if (type == SMC_37C666GT) { 768 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 769 if (bootverbose) 770 printf(" configuration hardwired, supposing " \ 771 "ECP+EPP SPP"); 772 773 } else 774 if ((inb(cio) & SMC_CR1_MODE) == 0) { 775 /* already in extended parallel port mode, read CR4 */ 776 outb(csr, 0x4); 777 r = (inb(cio) & SMC_CR4_EMODE); 778 779 switch (r) { 780 case SMC_SPP: 781 ppc->ppc_avm |= PPB_SPP; 782 if (bootverbose) 783 printf(" SPP"); 784 break; 785 786 case SMC_EPPSPP: 787 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 788 if (bootverbose) 789 printf(" EPP SPP"); 790 break; 791 792 case SMC_ECP: 793 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 794 if (bootverbose) 795 printf(" ECP SPP"); 796 break; 797 798 case SMC_ECPEPP: 799 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 800 if (bootverbose) 801 printf(" ECP+EPP SPP"); 802 break; 803 } 804 } else { 805 /* not an extended port mode */ 806 ppc->ppc_avm |= PPB_SPP; 807 if (bootverbose) 808 printf(" SPP"); 809 } 810 811 } else { 812 /* mode forced */ 813 ppc->ppc_avm = chipset_mode; 814 815 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 816 if (type == SMC_37C666GT) 817 goto end_detect; 818 819 r = inb(cio); 820 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 821 /* do not use ECP when the mode is not forced to */ 822 outb(cio, r | SMC_CR1_MODE); 823 if (bootverbose) 824 printf(" SPP"); 825 } else { 826 /* an extended mode is selected */ 827 outb(cio, r & ~SMC_CR1_MODE); 828 829 /* read CR4 register and reset mode field */ 830 outb(csr, 0x4); 831 r = inb(cio) & ~SMC_CR4_EMODE; 832 833 if (chipset_mode & PPB_ECP) { 834 if (chipset_mode & PPB_EPP) { 835 outb(cio, r | SMC_ECPEPP); 836 if (bootverbose) 837 printf(" ECP+EPP"); 838 } else { 839 outb(cio, r | SMC_ECP); 840 if (bootverbose) 841 printf(" ECP"); 842 } 843 } else { 844 /* PPB_EPP is set */ 845 outb(cio, r | SMC_EPPSPP); 846 if (bootverbose) 847 printf(" EPP SPP"); 848 } 849 } 850 ppc->ppc_avm = chipset_mode; 851 } 852 853 /* set FIFO threshold to 16 */ 854 if (ppc->ppc_avm & PPB_ECP) { 855 /* select CRA */ 856 outb(csr, 0xa); 857 outb(cio, 16); 858 } 859 860 end_detect: 861 862 if (bootverbose) 863 printf ("\n"); 864 865 if (ppc->ppc_avm & PPB_EPP) { 866 /* select CR4 */ 867 outb(csr, 0x4); 868 r = inb(cio); 869 870 /* 871 * Set the EPP protocol... 872 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 873 */ 874 if (ppc->ppc_epp == EPP_1_9) 875 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 876 else 877 outb(cio, (r | SMC_CR4_EPPTYPE)); 878 } 879 880 /* end config mode */ 881 outb(csr, 0xaa); 882 883 ppc->ppc_type = PPC_TYPE_SMCLIKE; 884 ppc_smclike_setmode(ppc, chipset_mode); 885 886 return (chipset_mode); 887 } 888 889 /* 890 * SMC FDC37C935 configuration 891 * Found on many Alpha machines 892 */ 893 static int 894 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 895 { 896 int s; 897 int type = -1; 898 899 s = splhigh(); 900 outb(SMC935_CFG, 0x55); /* enter config mode */ 901 outb(SMC935_CFG, 0x55); 902 splx(s); 903 904 outb(SMC935_IND, SMC935_ID); /* check device id */ 905 if (inb(SMC935_DAT) == 0x2) 906 type = SMC_37C935; 907 908 if (type == -1) { 909 outb(SMC935_CFG, 0xaa); /* exit config mode */ 910 return (-1); 911 } 912 913 ppc->ppc_model = type; 914 915 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 916 outb(SMC935_DAT, 3); /* which is logical device 3 */ 917 918 /* set io port base */ 919 outb(SMC935_IND, SMC935_PORTHI); 920 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 921 outb(SMC935_IND, SMC935_PORTLO); 922 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 923 924 if (!chipset_mode) 925 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 926 else { 927 ppc->ppc_avm = chipset_mode; 928 outb(SMC935_IND, SMC935_PPMODE); 929 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 930 931 /* SPP + EPP or just plain SPP */ 932 if (chipset_mode & (PPB_SPP)) { 933 if (chipset_mode & PPB_EPP) { 934 if (ppc->ppc_epp == EPP_1_9) { 935 outb(SMC935_IND, SMC935_PPMODE); 936 outb(SMC935_DAT, SMC935_EPP19SPP); 937 } 938 if (ppc->ppc_epp == EPP_1_7) { 939 outb(SMC935_IND, SMC935_PPMODE); 940 outb(SMC935_DAT, SMC935_EPP17SPP); 941 } 942 } else { 943 outb(SMC935_IND, SMC935_PPMODE); 944 outb(SMC935_DAT, SMC935_SPP); 945 } 946 } 947 948 /* ECP + EPP or just plain ECP */ 949 if (chipset_mode & PPB_ECP) { 950 if (chipset_mode & PPB_EPP) { 951 if (ppc->ppc_epp == EPP_1_9) { 952 outb(SMC935_IND, SMC935_PPMODE); 953 outb(SMC935_DAT, SMC935_ECPEPP19); 954 } 955 if (ppc->ppc_epp == EPP_1_7) { 956 outb(SMC935_IND, SMC935_PPMODE); 957 outb(SMC935_DAT, SMC935_ECPEPP17); 958 } 959 } else { 960 outb(SMC935_IND, SMC935_PPMODE); 961 outb(SMC935_DAT, SMC935_ECP); 962 } 963 } 964 } 965 966 outb(SMC935_CFG, 0xaa); /* exit config mode */ 967 968 ppc->ppc_type = PPC_TYPE_SMCLIKE; 969 ppc_smclike_setmode(ppc, chipset_mode); 970 971 return (chipset_mode); 972 } 973 974 /* 975 * Winbond W83877F stuff 976 * 977 * EFER: extended function enable register 978 * EFIR: extended function index register 979 * EFDR: extended function data register 980 */ 981 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 982 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 983 984 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 985 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 986 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 987 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 988 989 static int 990 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 991 { 992 int i, j, efer; 993 unsigned char r, hefere, hefras; 994 995 for (i = 0; i < 4; i ++) { 996 /* first try to enable configuration registers */ 997 efer = w83877f_efers[i]; 998 999 /* write the key to the EFER */ 1000 for (j = 0; j < w83877f_keyiter[i]; j ++) 1001 outb (efer, w83877f_keys[i]); 1002 1003 /* then check HEFERE and HEFRAS bits */ 1004 outb (efir, 0x0c); 1005 hefere = inb(efdr) & WINB_HEFERE; 1006 1007 outb (efir, 0x16); 1008 hefras = inb(efdr) & WINB_HEFRAS; 1009 1010 /* 1011 * HEFRAS HEFERE 1012 * 0 1 write 89h to 250h (power-on default) 1013 * 1 0 write 86h twice to 3f0h 1014 * 1 1 write 87h twice to 3f0h 1015 * 0 0 write 88h to 250h 1016 */ 1017 if ((hefere | hefras) == w83877f_hefs[i]) 1018 goto found; 1019 } 1020 1021 return (-1); /* failed */ 1022 1023 found: 1024 /* check base port address - read from CR23 */ 1025 outb(efir, 0x23); 1026 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1027 return (-1); 1028 1029 /* read CHIP ID from CR9/bits0-3 */ 1030 outb(efir, 0x9); 1031 1032 switch (inb(efdr) & WINB_CHIPID) { 1033 case WINB_W83877F_ID: 1034 ppc->ppc_model = WINB_W83877F; 1035 break; 1036 1037 case WINB_W83877AF_ID: 1038 ppc->ppc_model = WINB_W83877AF; 1039 break; 1040 1041 default: 1042 ppc->ppc_model = WINB_UNKNOWN; 1043 } 1044 1045 if (bootverbose) { 1046 /* dump of registers */ 1047 device_printf(dev, "0x%x - ", w83877f_keys[i]); 1048 for (i = 0; i <= 0xd; i ++) { 1049 outb(efir, i); 1050 printf("0x%x ", inb(efdr)); 1051 } 1052 for (i = 0x10; i <= 0x17; i ++) { 1053 outb(efir, i); 1054 printf("0x%x ", inb(efdr)); 1055 } 1056 outb(efir, 0x1e); 1057 printf("0x%x ", inb(efdr)); 1058 for (i = 0x20; i <= 0x29; i ++) { 1059 outb(efir, i); 1060 printf("0x%x ", inb(efdr)); 1061 } 1062 printf("\n"); 1063 } 1064 1065 ppc->ppc_type = PPC_TYPE_GENERIC; 1066 1067 if (!chipset_mode) { 1068 /* autodetect mode */ 1069 1070 /* select CR0 */ 1071 outb(efir, 0x0); 1072 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1073 1074 /* select CR9 */ 1075 outb(efir, 0x9); 1076 r |= (inb(efdr) & WINB_PRTMODS2); 1077 1078 switch (r) { 1079 case WINB_W83757: 1080 if (bootverbose) 1081 device_printf(dev, "W83757 compatible mode\n"); 1082 return (-1); /* generic or SMC-like */ 1083 1084 case WINB_EXTFDC: 1085 case WINB_EXTADP: 1086 case WINB_EXT2FDD: 1087 case WINB_JOYSTICK: 1088 if (bootverbose) 1089 device_printf(dev, 1090 "not in parallel port mode\n"); 1091 return (-1); 1092 1093 case (WINB_PARALLEL | WINB_EPP_SPP): 1094 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1095 if (bootverbose) 1096 device_printf(dev, "EPP SPP\n"); 1097 break; 1098 1099 case (WINB_PARALLEL | WINB_ECP): 1100 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1101 if (bootverbose) 1102 device_printf(dev, "ECP SPP\n"); 1103 break; 1104 1105 case (WINB_PARALLEL | WINB_ECP_EPP): 1106 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1107 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1108 1109 if (bootverbose) 1110 device_printf(dev, "ECP+EPP SPP\n"); 1111 break; 1112 default: 1113 printf("%s: unknown case (0x%x)!\n", __func__, r); 1114 } 1115 1116 } else { 1117 /* mode forced */ 1118 1119 /* select CR9 and set PRTMODS2 bit */ 1120 outb(efir, 0x9); 1121 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1122 1123 /* select CR0 and reset PRTMODSx bits */ 1124 outb(efir, 0x0); 1125 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1126 1127 if (chipset_mode & PPB_ECP) { 1128 if (chipset_mode & PPB_EPP) { 1129 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1130 if (bootverbose) 1131 device_printf(dev, "ECP+EPP\n"); 1132 1133 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1134 1135 } else { 1136 outb(efdr, inb(efdr) | WINB_ECP); 1137 if (bootverbose) 1138 device_printf(dev, "ECP\n"); 1139 } 1140 } else { 1141 /* select EPP_SPP otherwise */ 1142 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1143 if (bootverbose) 1144 device_printf(dev, "EPP SPP\n"); 1145 } 1146 ppc->ppc_avm = chipset_mode; 1147 } 1148 1149 /* exit configuration mode */ 1150 outb(efer, 0xaa); 1151 1152 switch (ppc->ppc_type) { 1153 case PPC_TYPE_SMCLIKE: 1154 ppc_smclike_setmode(ppc, chipset_mode); 1155 break; 1156 default: 1157 ppc_generic_setmode(ppc, chipset_mode); 1158 break; 1159 } 1160 1161 return (chipset_mode); 1162 } 1163 #endif 1164 1165 /* 1166 * ppc_generic_detect 1167 */ 1168 static int 1169 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1170 { 1171 /* default to generic */ 1172 ppc->ppc_type = PPC_TYPE_GENERIC; 1173 1174 if (bootverbose) 1175 device_printf(ppc->ppc_dev, "SPP"); 1176 1177 /* first, check for ECP */ 1178 w_ecr(ppc, PPC_ECR_PS2); 1179 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1180 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1181 if (bootverbose) 1182 printf(" ECP "); 1183 1184 /* search for SMC style ECP+EPP mode */ 1185 w_ecr(ppc, PPC_ECR_EPP); 1186 } 1187 1188 /* try to reset EPP timeout bit */ 1189 if (ppc_check_epp_timeout(ppc)) { 1190 ppc->ppc_dtm |= PPB_EPP; 1191 1192 if (ppc->ppc_dtm & PPB_ECP) { 1193 /* SMC like chipset found */ 1194 ppc->ppc_model = SMC_LIKE; 1195 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1196 1197 if (bootverbose) 1198 printf(" ECP+EPP"); 1199 } else { 1200 if (bootverbose) 1201 printf(" EPP"); 1202 } 1203 } else { 1204 /* restore to standard mode */ 1205 w_ecr(ppc, PPC_ECR_STD); 1206 } 1207 1208 /* XXX try to detect NIBBLE and PS2 modes */ 1209 ppc->ppc_dtm |= PPB_NIBBLE; 1210 1211 if (chipset_mode) 1212 ppc->ppc_avm = chipset_mode; 1213 else 1214 ppc->ppc_avm = ppc->ppc_dtm; 1215 1216 if (bootverbose) 1217 printf("\n"); 1218 1219 switch (ppc->ppc_type) { 1220 case PPC_TYPE_SMCLIKE: 1221 ppc_smclike_setmode(ppc, chipset_mode); 1222 break; 1223 default: 1224 ppc_generic_setmode(ppc, chipset_mode); 1225 break; 1226 } 1227 1228 return (chipset_mode); 1229 } 1230 1231 /* 1232 * ppc_detect() 1233 * 1234 * mode is the mode suggested at boot 1235 */ 1236 static int 1237 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1238 1239 #ifdef PPC_PROBE_CHIPSET 1240 int i, mode; 1241 1242 /* list of supported chipsets */ 1243 int (*chipset_detect[])(struct ppc_data *, int) = { 1244 ppc_pc873xx_detect, 1245 ppc_smc37c66xgt_detect, 1246 ppc_w83877f_detect, 1247 ppc_smc37c935_detect, 1248 ppc_generic_detect, 1249 NULL 1250 }; 1251 #endif 1252 1253 /* if can't find the port and mode not forced return error */ 1254 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1255 return (EIO); /* failed, port not present */ 1256 1257 /* assume centronics compatible mode is supported */ 1258 ppc->ppc_avm = PPB_COMPATIBLE; 1259 1260 #ifdef PPC_PROBE_CHIPSET 1261 /* we have to differenciate available chipset modes, 1262 * chipset running modes and IEEE-1284 operating modes 1263 * 1264 * after detection, the port must support running in compatible mode 1265 */ 1266 if (ppc->ppc_flags & 0x40) { 1267 if (bootverbose) 1268 printf("ppc: chipset forced to generic\n"); 1269 #endif 1270 1271 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1272 1273 #ifdef PPC_PROBE_CHIPSET 1274 } else { 1275 for (i=0; chipset_detect[i] != NULL; i++) { 1276 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1277 ppc->ppc_mode = mode; 1278 break; 1279 } 1280 } 1281 } 1282 #endif 1283 1284 /* configure/detect ECP FIFO */ 1285 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1286 ppc_detect_fifo(ppc); 1287 1288 return (0); 1289 } 1290 1291 /* 1292 * ppc_exec_microseq() 1293 * 1294 * Execute a microsequence. 1295 * Microsequence mechanism is supposed to handle fast I/O operations. 1296 */ 1297 int 1298 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1299 { 1300 struct ppc_data *ppc = DEVTOSOFTC(dev); 1301 struct ppb_microseq *mi; 1302 char cc, *p; 1303 int i, iter, len; 1304 int error; 1305 1306 register int reg; 1307 register char mask; 1308 register int accum = 0; 1309 register char *ptr = 0; 1310 1311 struct ppb_microseq *stack = 0; 1312 1313 /* microsequence registers are equivalent to PC-like port registers */ 1314 1315 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1316 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1317 1318 #define INCR_PC (mi ++) /* increment program counter */ 1319 1320 mi = *p_msq; 1321 for (;;) { 1322 switch (mi->opcode) { 1323 case MS_OP_RSET: 1324 cc = r_reg(mi->arg[0].i, ppc); 1325 cc &= (char)mi->arg[2].i; /* clear mask */ 1326 cc |= (char)mi->arg[1].i; /* assert mask */ 1327 w_reg(mi->arg[0].i, ppc, cc); 1328 INCR_PC; 1329 break; 1330 1331 case MS_OP_RASSERT_P: 1332 reg = mi->arg[1].i; 1333 ptr = ppc->ppc_ptr; 1334 1335 if ((len = mi->arg[0].i) == MS_ACCUM) { 1336 accum = ppc->ppc_accum; 1337 for (; accum; accum--) 1338 w_reg(reg, ppc, *ptr++); 1339 ppc->ppc_accum = accum; 1340 } else 1341 for (i=0; i<len; i++) 1342 w_reg(reg, ppc, *ptr++); 1343 ppc->ppc_ptr = ptr; 1344 1345 INCR_PC; 1346 break; 1347 1348 case MS_OP_RFETCH_P: 1349 reg = mi->arg[1].i; 1350 mask = (char)mi->arg[2].i; 1351 ptr = ppc->ppc_ptr; 1352 1353 if ((len = mi->arg[0].i) == MS_ACCUM) { 1354 accum = ppc->ppc_accum; 1355 for (; accum; accum--) 1356 *ptr++ = r_reg(reg, ppc) & mask; 1357 ppc->ppc_accum = accum; 1358 } else 1359 for (i=0; i<len; i++) 1360 *ptr++ = r_reg(reg, ppc) & mask; 1361 ppc->ppc_ptr = ptr; 1362 1363 INCR_PC; 1364 break; 1365 1366 case MS_OP_RFETCH: 1367 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1368 (char)mi->arg[1].i; 1369 INCR_PC; 1370 break; 1371 1372 case MS_OP_RASSERT: 1373 case MS_OP_DELAY: 1374 1375 /* let's suppose the next instr. is the same */ 1376 prefetch: 1377 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1378 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1379 1380 if (mi->opcode == MS_OP_DELAY) { 1381 DELAY(mi->arg[0].i); 1382 INCR_PC; 1383 goto prefetch; 1384 } 1385 break; 1386 1387 case MS_OP_ADELAY: 1388 if (mi->arg[0].i) 1389 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1390 INCR_PC; 1391 break; 1392 1393 case MS_OP_TRIG: 1394 reg = mi->arg[0].i; 1395 iter = mi->arg[1].i; 1396 p = (char *)mi->arg[2].p; 1397 1398 /* XXX delay limited to 255 us */ 1399 for (i=0; i<iter; i++) { 1400 w_reg(reg, ppc, *p++); 1401 DELAY((unsigned char)*p++); 1402 } 1403 INCR_PC; 1404 break; 1405 1406 case MS_OP_SET: 1407 ppc->ppc_accum = mi->arg[0].i; 1408 INCR_PC; 1409 break; 1410 1411 case MS_OP_DBRA: 1412 if (--ppc->ppc_accum > 0) 1413 mi += mi->arg[0].i; 1414 INCR_PC; 1415 break; 1416 1417 case MS_OP_BRSET: 1418 cc = r_str(ppc); 1419 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1420 mi += mi->arg[1].i; 1421 INCR_PC; 1422 break; 1423 1424 case MS_OP_BRCLEAR: 1425 cc = r_str(ppc); 1426 if ((cc & (char)mi->arg[0].i) == 0) 1427 mi += mi->arg[1].i; 1428 INCR_PC; 1429 break; 1430 1431 case MS_OP_BRSTAT: 1432 cc = r_str(ppc); 1433 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1434 (char)mi->arg[0].i) 1435 mi += mi->arg[2].i; 1436 INCR_PC; 1437 break; 1438 1439 case MS_OP_C_CALL: 1440 /* 1441 * If the C call returns !0 then end the microseq. 1442 * The current state of ptr is passed to the C function 1443 */ 1444 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1445 return (error); 1446 1447 INCR_PC; 1448 break; 1449 1450 case MS_OP_PTR: 1451 ppc->ppc_ptr = (char *)mi->arg[0].p; 1452 INCR_PC; 1453 break; 1454 1455 case MS_OP_CALL: 1456 if (stack) 1457 panic("%s: too much calls", __func__); 1458 1459 if (mi->arg[0].p) { 1460 /* store the state of the actual 1461 * microsequence 1462 */ 1463 stack = mi; 1464 1465 /* jump to the new microsequence */ 1466 mi = (struct ppb_microseq *)mi->arg[0].p; 1467 } else 1468 INCR_PC; 1469 1470 break; 1471 1472 case MS_OP_SUBRET: 1473 /* retrieve microseq and pc state before the call */ 1474 mi = stack; 1475 1476 /* reset the stack */ 1477 stack = 0; 1478 1479 /* XXX return code */ 1480 1481 INCR_PC; 1482 break; 1483 1484 case MS_OP_PUT: 1485 case MS_OP_GET: 1486 case MS_OP_RET: 1487 /* can't return to ppb level during the execution 1488 * of a submicrosequence */ 1489 if (stack) 1490 panic("%s: can't return to ppb level", 1491 __func__); 1492 1493 /* update pc for ppb level of execution */ 1494 *p_msq = mi; 1495 1496 /* return to ppb level of execution */ 1497 return (0); 1498 1499 default: 1500 panic("%s: unknown microsequence opcode 0x%x", 1501 __func__, mi->opcode); 1502 } 1503 } 1504 1505 /* unreached */ 1506 } 1507 1508 static void 1509 ppcintr(void *arg) 1510 { 1511 struct ppc_data *ppc = arg; 1512 u_char ctr, ecr, str; 1513 1514 /* 1515 * If we have any child interrupt handlers registered, let 1516 * them handle this interrupt. 1517 * 1518 * XXX: If DMA is in progress should we just complete that w/o 1519 * doing this? 1520 */ 1521 if (ppc->ppc_child_handlers > 0) { 1522 intr_event_execute_handlers(curproc, ppc->ppc_intr_event); 1523 return; 1524 } 1525 1526 str = r_str(ppc); 1527 ctr = r_ctr(ppc); 1528 ecr = r_ecr(ppc); 1529 1530 #if defined(PPC_DEBUG) && PPC_DEBUG > 1 1531 printf("![%x/%x/%x]", ctr, ecr, str); 1532 #endif 1533 1534 /* don't use ecp mode with IRQENABLE set */ 1535 if (ctr & IRQENABLE) { 1536 return; 1537 } 1538 1539 /* interrupts are generated by nFault signal 1540 * only in ECP mode */ 1541 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1542 /* check if ppc driver has programmed the 1543 * nFault interrupt */ 1544 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1545 1546 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1547 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1548 } else { 1549 /* shall be handled by underlying layers XXX */ 1550 return; 1551 } 1552 } 1553 1554 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1555 /* disable interrupts (should be done by hardware though) */ 1556 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1557 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1558 ecr = r_ecr(ppc); 1559 1560 /* check if DMA completed */ 1561 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1562 #ifdef PPC_DEBUG 1563 printf("a"); 1564 #endif 1565 /* stop DMA */ 1566 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1567 ecr = r_ecr(ppc); 1568 1569 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1570 #ifdef PPC_DEBUG 1571 printf("d"); 1572 #endif 1573 ppc->ppc_dmadone(ppc); 1574 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1575 1576 /* wakeup the waiting process */ 1577 wakeup(ppc); 1578 } 1579 } 1580 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1581 1582 /* classic interrupt I/O */ 1583 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1584 } 1585 1586 return; 1587 } 1588 1589 int 1590 ppc_read(device_t dev, char *buf, int len, int mode) 1591 { 1592 return (EINVAL); 1593 } 1594 1595 int 1596 ppc_write(device_t dev, char *buf, int len, int how) 1597 { 1598 return (EINVAL); 1599 } 1600 1601 void 1602 ppc_reset_epp(device_t dev) 1603 { 1604 struct ppc_data *ppc = DEVTOSOFTC(dev); 1605 1606 ppc_reset_epp_timeout(ppc); 1607 1608 return; 1609 } 1610 1611 int 1612 ppc_setmode(device_t dev, int mode) 1613 { 1614 struct ppc_data *ppc = DEVTOSOFTC(dev); 1615 1616 switch (ppc->ppc_type) { 1617 case PPC_TYPE_SMCLIKE: 1618 return (ppc_smclike_setmode(ppc, mode)); 1619 break; 1620 1621 case PPC_TYPE_GENERIC: 1622 default: 1623 return (ppc_generic_setmode(ppc, mode)); 1624 break; 1625 } 1626 1627 /* not reached */ 1628 return (ENXIO); 1629 } 1630 1631 int 1632 ppc_probe(device_t dev, int rid) 1633 { 1634 #ifdef __i386__ 1635 static short next_bios_ppc = 0; 1636 #ifdef PC98 1637 unsigned int pc98_ieee_mode = 0x00; 1638 unsigned int tmp; 1639 #endif 1640 #endif 1641 struct ppc_data *ppc; 1642 int error; 1643 u_long port; 1644 1645 /* 1646 * Allocate the ppc_data structure. 1647 */ 1648 ppc = DEVTOSOFTC(dev); 1649 bzero(ppc, sizeof(struct ppc_data)); 1650 1651 ppc->rid_ioport = rid; 1652 1653 /* retrieve ISA parameters */ 1654 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1655 1656 #ifdef __i386__ 1657 /* 1658 * If port not specified, use bios list. 1659 */ 1660 if (error) { 1661 #ifdef PC98 1662 if (next_bios_ppc == 0) { 1663 /* Use default IEEE-1284 port of NEC PC-98x1 */ 1664 port = PC98_IEEE_1284_PORT; 1665 next_bios_ppc += 1; 1666 if (bootverbose) 1667 device_printf(dev, 1668 "parallel port found at 0x%x\n", 1669 (int) port); 1670 } 1671 #else 1672 if((next_bios_ppc < BIOS_MAX_PPC) && 1673 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1674 port = *(BIOS_PORTS+next_bios_ppc++); 1675 if (bootverbose) 1676 device_printf(dev, "parallel port found at 0x%x\n", 1677 (int) port); 1678 } else { 1679 device_printf(dev, "parallel port not found.\n"); 1680 return ENXIO; 1681 } 1682 #endif /* PC98 */ 1683 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1684 IO_LPTSIZE_EXTENDED); 1685 } 1686 #endif 1687 1688 /* IO port is mandatory */ 1689 1690 /* Try "extended" IO port range...*/ 1691 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1692 &ppc->rid_ioport, 0, ~0, 1693 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1694 1695 if (ppc->res_ioport != 0) { 1696 if (bootverbose) 1697 device_printf(dev, "using extended I/O port range\n"); 1698 } else { 1699 /* Failed? If so, then try the "normal" IO port range... */ 1700 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1701 &ppc->rid_ioport, 0, ~0, 1702 IO_LPTSIZE_NORMAL, 1703 RF_ACTIVE); 1704 if (ppc->res_ioport != 0) { 1705 if (bootverbose) 1706 device_printf(dev, "using normal I/O port range\n"); 1707 } else { 1708 device_printf(dev, "cannot reserve I/O port range\n"); 1709 goto error; 1710 } 1711 } 1712 1713 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1714 1715 ppc->ppc_flags = device_get_flags(dev); 1716 1717 if (!(ppc->ppc_flags & 0x20)) { 1718 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1719 &ppc->rid_irq, 1720 RF_SHAREABLE); 1721 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1722 &ppc->rid_drq, 1723 RF_ACTIVE); 1724 } 1725 1726 if (ppc->res_irq) 1727 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1728 if (ppc->res_drq) 1729 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1730 1731 ppc->ppc_dev = dev; 1732 ppc->ppc_model = GENERIC; 1733 1734 ppc->ppc_mode = PPB_COMPATIBLE; 1735 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1736 1737 ppc->ppc_type = PPC_TYPE_GENERIC; 1738 1739 #if defined(__i386__) && defined(PC98) 1740 /* 1741 * IEEE STD 1284 Function Check and Enable 1742 * for default IEEE-1284 port of NEC PC-98x1 1743 */ 1744 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1745 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1746 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1747 pc98_ieee_mode = tmp; 1748 if ((tmp & 0x10) == 0x10) { 1749 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); 1750 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1751 if ((tmp & 0x10) == 0x10) 1752 goto error; 1753 } else { 1754 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); 1755 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1756 if ((tmp & 0x10) != 0x10) 1757 goto error; 1758 } 1759 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); 1760 } 1761 #endif 1762 1763 /* 1764 * Try to detect the chipset and its mode. 1765 */ 1766 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1767 goto error; 1768 1769 return (0); 1770 1771 error: 1772 #if defined(__i386__) && defined(PC98) 1773 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1774 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1775 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); 1776 } 1777 #endif 1778 if (ppc->res_irq != 0) { 1779 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1780 ppc->res_irq); 1781 } 1782 if (ppc->res_ioport != 0) { 1783 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1784 ppc->res_ioport); 1785 } 1786 if (ppc->res_drq != 0) { 1787 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1788 ppc->res_drq); 1789 } 1790 return (ENXIO); 1791 } 1792 1793 int 1794 ppc_attach(device_t dev) 1795 { 1796 struct ppc_data *ppc = DEVTOSOFTC(dev); 1797 device_t ppbus; 1798 int error; 1799 1800 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1801 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1802 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1803 ppc_epp_protocol[ppc->ppc_epp] : ""); 1804 1805 if (ppc->ppc_fifo) 1806 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1807 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1808 1809 if (ppc->res_irq) { 1810 /* 1811 * Create an interrupt event to manage the handlers of 1812 * child devices. 1813 */ 1814 error = intr_event_create(&ppc->ppc_intr_event, ppc, 0, -1, 1815 NULL, NULL, NULL, NULL, "%s:", device_get_nameunit(dev)); 1816 if (error) { 1817 device_printf(dev, 1818 "failed to create interrupt event: %d\n", error); 1819 return (error); 1820 } 1821 1822 /* default to the tty mask for registration */ /* XXX */ 1823 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY, 1824 NULL, ppcintr, ppc, &ppc->intr_cookie); 1825 if (error) { 1826 device_printf(dev, 1827 "failed to register interrupt handler: %d\n", 1828 error); 1829 return (error); 1830 } 1831 } 1832 1833 /* add ppbus as a child of this isa to parallel bridge */ 1834 ppbus = device_add_child(dev, "ppbus", -1); 1835 1836 /* 1837 * Probe the ppbus and attach devices found. 1838 */ 1839 device_probe_and_attach(ppbus); 1840 1841 return (0); 1842 } 1843 1844 int 1845 ppc_detach(device_t dev) 1846 { 1847 struct ppc_data *ppc = DEVTOSOFTC(dev); 1848 device_t *children; 1849 int nchildren, i; 1850 1851 if (ppc->res_irq == 0) { 1852 return (ENXIO); 1853 } 1854 1855 /* detach & delete all children */ 1856 if (!device_get_children(dev, &children, &nchildren)) { 1857 for (i = 0; i < nchildren; i++) 1858 if (children[i]) 1859 device_delete_child(dev, children[i]); 1860 free(children, M_TEMP); 1861 } 1862 1863 if (ppc->res_irq != 0) { 1864 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1865 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1866 ppc->res_irq); 1867 } 1868 if (ppc->res_ioport != 0) { 1869 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1870 ppc->res_ioport); 1871 } 1872 if (ppc->res_drq != 0) { 1873 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1874 ppc->res_drq); 1875 } 1876 1877 return (0); 1878 } 1879 1880 u_char 1881 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1882 { 1883 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1884 switch (iop) { 1885 case PPB_OUTSB_EPP: 1886 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1887 break; 1888 case PPB_OUTSW_EPP: 1889 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1890 break; 1891 case PPB_OUTSL_EPP: 1892 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1893 break; 1894 case PPB_INSB_EPP: 1895 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1896 break; 1897 case PPB_INSW_EPP: 1898 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1899 break; 1900 case PPB_INSL_EPP: 1901 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1902 break; 1903 case PPB_RDTR: 1904 return (r_dtr(ppc)); 1905 case PPB_RSTR: 1906 return (r_str(ppc)); 1907 case PPB_RCTR: 1908 return (r_ctr(ppc)); 1909 case PPB_REPP_A: 1910 return (r_epp_A(ppc)); 1911 case PPB_REPP_D: 1912 return (r_epp_D(ppc)); 1913 case PPB_RECR: 1914 return (r_ecr(ppc)); 1915 case PPB_RFIFO: 1916 return (r_fifo(ppc)); 1917 case PPB_WDTR: 1918 w_dtr(ppc, byte); 1919 break; 1920 case PPB_WSTR: 1921 w_str(ppc, byte); 1922 break; 1923 case PPB_WCTR: 1924 w_ctr(ppc, byte); 1925 break; 1926 case PPB_WEPP_A: 1927 w_epp_A(ppc, byte); 1928 break; 1929 case PPB_WEPP_D: 1930 w_epp_D(ppc, byte); 1931 break; 1932 case PPB_WECR: 1933 w_ecr(ppc, byte); 1934 break; 1935 case PPB_WFIFO: 1936 w_fifo(ppc, byte); 1937 break; 1938 default: 1939 panic("%s: unknown I/O operation", __func__); 1940 break; 1941 } 1942 1943 return (0); /* not significative */ 1944 } 1945 1946 int 1947 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1948 { 1949 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1950 1951 switch (index) { 1952 case PPC_IVAR_EPP_PROTO: 1953 *val = (u_long)ppc->ppc_epp; 1954 break; 1955 default: 1956 return (ENOENT); 1957 } 1958 1959 return (0); 1960 } 1961 1962 /* 1963 * We allow child devices to allocate an IRQ resource at rid 0 for their 1964 * interrupt handlers. 1965 */ 1966 struct resource * 1967 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 1968 u_long start, u_long end, u_long count, u_int flags) 1969 { 1970 struct ppc_data *ppc = DEVTOSOFTC(bus); 1971 1972 switch (type) { 1973 case SYS_RES_IRQ: 1974 if (*rid == 0) 1975 return (ppc->res_irq); 1976 break; 1977 } 1978 return (NULL); 1979 } 1980 1981 int 1982 ppc_release_resource(device_t bus, device_t child, int type, int rid, 1983 struct resource *r) 1984 { 1985 #ifdef INVARIANTS 1986 struct ppc_data *ppc = DEVTOSOFTC(bus); 1987 #endif 1988 1989 switch (type) { 1990 case SYS_RES_IRQ: 1991 if (rid == 0) { 1992 KASSERT(r == ppc->res_irq, 1993 ("ppc child IRQ resource mismatch")); 1994 return (0); 1995 } 1996 break; 1997 } 1998 return (EINVAL); 1999 } 2000 2001 /* 2002 * If a child wants to add a handler for our IRQ, add it to our interrupt 2003 * event. Otherwise, fail the request. 2004 */ 2005 int 2006 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2007 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep) 2008 { 2009 struct ppc_data *ppc = DEVTOSOFTC(bus); 2010 int error; 2011 2012 if (r != ppc->res_irq) 2013 return (EINVAL); 2014 2015 /* We don't allow filters. */ 2016 if (filt != NULL) 2017 return (EINVAL); 2018 2019 error = intr_event_add_handler(ppc->ppc_intr_event, 2020 device_get_nameunit(child), NULL, ihand, arg, intr_priority(flags), 2021 flags, cookiep); 2022 if (error == 0) 2023 ppc->ppc_child_handlers++; 2024 return (error); 2025 } 2026 2027 int 2028 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *cookie) 2029 { 2030 struct ppc_data *ppc = DEVTOSOFTC(bus); 2031 int error; 2032 2033 if (r != ppc->res_irq) 2034 return (EINVAL); 2035 2036 KASSERT(intr_handler_source(cookie) == ppc, 2037 ("ppc_teardown_intr: source mismatch")); 2038 error = intr_event_remove_handler(cookie); 2039 if (error == 0) 2040 ppc->ppc_child_handlers--; 2041 return (error); 2042 } 2043 2044 MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2045