1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include "opt_ppc.h"
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/interrupt.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/mutex.h>
44 #include <sys/proc.h>
45
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <sys/rman.h>
49
50 #ifdef __i386__
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53 #include <machine/vmparam.h>
54 #include <machine/pc/bios.h>
55 #endif
56
57 #include <dev/ppbus/ppbconf.h>
58 #include <dev/ppbus/ppb_msq.h>
59
60 #include <dev/ppc/ppcvar.h>
61 #include <dev/ppc/ppcreg.h>
62
63 #include "ppbus_if.h"
64
65 static void ppcintr(void *arg);
66
67 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
68 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
69
70 #define LOG_PPC(function, ppc, string) \
71 if (bootverbose) printf("%s: %s\n", function, string)
72
73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
74
75 /*
76 * We use critical enter/exit for the simple config locking needed to
77 * detect the devices. We just want to make sure that both of our writes
78 * happen without someone else also writing to those config registers. Since
79 * we just do this at startup, Giant keeps multiple threads from executing,
80 * and critical_enter() then is all that's needed to keep us from being preempted
81 * during the critical sequences with the hardware.
82 *
83 * Note: this doesn't prevent multiple threads from putting the chips into
84 * config mode, but since we only do that to detect the type at startup the
85 * extra overhead isn't needed since Giant protects us from multiple entry
86 * and no other code changes these registers.
87 */
88 #define PPC_CONFIG_LOCK(ppc) critical_enter()
89 #define PPC_CONFIG_UNLOCK(ppc) critical_exit()
90
91 devclass_t ppc_devclass;
92 const char ppc_driver_name[] = "ppc";
93
94 static char *ppc_models[] = {
95 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
96 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
97 "SMC FDC37C935", "PC87303", 0
98 };
99
100 /* list of available modes */
101 static char *ppc_avms[] = {
102 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
103 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
104 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
105 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
106 };
107
108 /* list of current executing modes
109 * Note that few modes do not actually exist.
110 */
111 static char *ppc_modes[] = {
112 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
113 "EPP", "EPP", "EPP", "ECP",
114 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
115 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
116 };
117
118 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
119
120 #ifdef __i386__
121 /*
122 * BIOS printer list - used by BIOS probe.
123 */
124 #define BIOS_PPC_PORTS 0x408
125 #define BIOS_PORTS ((short *)BIOS_PADDRTOVADDR(BIOS_PPC_PORTS))
126 #define BIOS_MAX_PPC 4
127 #endif
128
129 /*
130 * ppc_ecp_sync() XXX
131 */
132 int
ppc_ecp_sync(device_t dev)133 ppc_ecp_sync(device_t dev)
134 {
135 int i, r;
136 struct ppc_data *ppc = DEVTOSOFTC(dev);
137
138 PPC_ASSERT_LOCKED(ppc);
139 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
140 return 0;
141
142 r = r_ecr(ppc);
143 if ((r & 0xe0) != PPC_ECR_EPP)
144 return 0;
145
146 for (i = 0; i < 100; i++) {
147 r = r_ecr(ppc);
148 if (r & 0x1)
149 return 0;
150 DELAY(100);
151 }
152
153 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
154
155 return 0;
156 }
157
158 /*
159 * ppc_detect_fifo()
160 *
161 * Detect parallel port FIFO
162 */
163 static int
ppc_detect_fifo(struct ppc_data * ppc)164 ppc_detect_fifo(struct ppc_data *ppc)
165 {
166 char ecr_sav;
167 char ctr_sav, ctr, cc;
168 short i;
169
170 /* save registers */
171 ecr_sav = r_ecr(ppc);
172 ctr_sav = r_ctr(ppc);
173
174 /* enter ECP configuration mode, no interrupt, no DMA */
175 w_ecr(ppc, 0xf4);
176
177 /* read PWord size - transfers in FIFO mode must be PWord aligned */
178 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
179
180 /* XXX 16 and 32 bits implementations not supported */
181 if (ppc->ppc_pword != PPC_PWORD_8) {
182 LOG_PPC(__func__, ppc, "PWord not supported");
183 goto error;
184 }
185
186 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
187 ctr = r_ctr(ppc);
188 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
189
190 /* enter ECP test mode, no interrupt, no DMA */
191 w_ecr(ppc, 0xd4);
192
193 /* flush the FIFO */
194 for (i=0; i<1024; i++) {
195 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
196 break;
197 cc = r_fifo(ppc);
198 }
199
200 if (i >= 1024) {
201 LOG_PPC(__func__, ppc, "can't flush FIFO");
202 goto error;
203 }
204
205 /* enable interrupts, no DMA */
206 w_ecr(ppc, 0xd0);
207
208 /* determine readIntrThreshold
209 * fill the FIFO until serviceIntr is set
210 */
211 for (i=0; i<1024; i++) {
212 w_fifo(ppc, (char)i);
213 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
214 /* readThreshold reached */
215 ppc->ppc_rthr = i+1;
216 }
217 if (r_ecr(ppc) & PPC_FIFO_FULL) {
218 ppc->ppc_fifo = i+1;
219 break;
220 }
221 }
222
223 if (i >= 1024) {
224 LOG_PPC(__func__, ppc, "can't fill FIFO");
225 goto error;
226 }
227
228 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
229 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
230 w_ecr(ppc, 0xd0); /* enable interrupts */
231
232 /* determine writeIntrThreshold
233 * empty the FIFO until serviceIntr is set
234 */
235 for (i=ppc->ppc_fifo; i>0; i--) {
236 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
237 LOG_PPC(__func__, ppc, "invalid data in FIFO");
238 goto error;
239 }
240 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
241 /* writeIntrThreshold reached */
242 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
243 }
244 /* if FIFO empty before the last byte, error */
245 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
246 LOG_PPC(__func__, ppc, "data lost in FIFO");
247 goto error;
248 }
249 }
250
251 /* FIFO must be empty after the last byte */
252 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
253 LOG_PPC(__func__, ppc, "can't empty the FIFO");
254 goto error;
255 }
256
257 w_ctr(ppc, ctr_sav);
258 w_ecr(ppc, ecr_sav);
259
260 return (0);
261
262 error:
263 w_ctr(ppc, ctr_sav);
264 w_ecr(ppc, ecr_sav);
265
266 return (EINVAL);
267 }
268
269 static int
ppc_detect_port(struct ppc_data * ppc)270 ppc_detect_port(struct ppc_data *ppc)
271 {
272
273 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
274 w_dtr(ppc, 0xaa);
275 if (r_dtr(ppc) != 0xaa)
276 return (0);
277
278 return (1);
279 }
280
281 /*
282 * EPP timeout, according to the PC87332 manual
283 * Semantics of clearing EPP timeout bit.
284 * PC87332 - reading SPP_STR does it...
285 * SMC - write 1 to EPP timeout bit XXX
286 * Others - (?) write 0 to EPP timeout bit
287 */
288 static void
ppc_reset_epp_timeout(struct ppc_data * ppc)289 ppc_reset_epp_timeout(struct ppc_data *ppc)
290 {
291 char r;
292
293 r = r_str(ppc);
294 w_str(ppc, r | 0x1);
295 w_str(ppc, r & 0xfe);
296
297 return;
298 }
299
300 static int
ppc_check_epp_timeout(struct ppc_data * ppc)301 ppc_check_epp_timeout(struct ppc_data *ppc)
302 {
303 ppc_reset_epp_timeout(ppc);
304
305 return (!(r_str(ppc) & TIMEOUT));
306 }
307
308 /*
309 * Configure current operating mode
310 */
311 static int
ppc_generic_setmode(struct ppc_data * ppc,int mode)312 ppc_generic_setmode(struct ppc_data *ppc, int mode)
313 {
314 u_char ecr = 0;
315
316 /* check if mode is available */
317 if (mode && !(ppc->ppc_avm & mode))
318 return (EINVAL);
319
320 /* if ECP mode, configure ecr register */
321 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
322 /* return to byte mode (keeping direction bit),
323 * no interrupt, no DMA to be able to change to
324 * ECP
325 */
326 w_ecr(ppc, PPC_ECR_RESET);
327 ecr = PPC_DISABLE_INTR;
328
329 if (mode & PPB_EPP)
330 return (EINVAL);
331 else if (mode & PPB_ECP)
332 /* select ECP mode */
333 ecr |= PPC_ECR_ECP;
334 else if (mode & PPB_PS2)
335 /* select PS2 mode with ECP */
336 ecr |= PPC_ECR_PS2;
337 else
338 /* select COMPATIBLE/NIBBLE mode */
339 ecr |= PPC_ECR_STD;
340
341 w_ecr(ppc, ecr);
342 }
343
344 ppc->ppc_mode = mode;
345
346 return (0);
347 }
348
349 /*
350 * The ppc driver is free to choose options like FIFO or DMA
351 * if ECP mode is available.
352 *
353 * The 'RAW' option allows the upper drivers to force the ppc mode
354 * even with FIFO, DMA available.
355 */
356 static int
ppc_smclike_setmode(struct ppc_data * ppc,int mode)357 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
358 {
359 u_char ecr = 0;
360
361 /* check if mode is available */
362 if (mode && !(ppc->ppc_avm & mode))
363 return (EINVAL);
364
365 /* if ECP mode, configure ecr register */
366 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
367 /* return to byte mode (keeping direction bit),
368 * no interrupt, no DMA to be able to change to
369 * ECP or EPP mode
370 */
371 w_ecr(ppc, PPC_ECR_RESET);
372 ecr = PPC_DISABLE_INTR;
373
374 if (mode & PPB_EPP)
375 /* select EPP mode */
376 ecr |= PPC_ECR_EPP;
377 else if (mode & PPB_ECP)
378 /* select ECP mode */
379 ecr |= PPC_ECR_ECP;
380 else if (mode & PPB_PS2)
381 /* select PS2 mode with ECP */
382 ecr |= PPC_ECR_PS2;
383 else
384 /* select COMPATIBLE/NIBBLE mode */
385 ecr |= PPC_ECR_STD;
386
387 w_ecr(ppc, ecr);
388 }
389
390 ppc->ppc_mode = mode;
391
392 return (0);
393 }
394
395 #ifdef PPC_PROBE_CHIPSET
396 /*
397 * ppc_pc873xx_detect
398 *
399 * Probe for a Natsemi PC873xx-family part.
400 *
401 * References in this function are to the National Semiconductor
402 * PC87332 datasheet TL/C/11930, May 1995 revision.
403 */
404 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
405 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
406 static int pc873xx_irqtab[] = {5, 7, 5, 0};
407
408 static int pc873xx_regstab[] = {
409 PC873_FER, PC873_FAR, PC873_PTR,
410 PC873_FCR, PC873_PCR, PC873_PMC,
411 PC873_TUP, PC873_SID, PC873_PNP0,
412 PC873_PNP1, PC873_LPTBA, -1
413 };
414
415 static char *pc873xx_rnametab[] = {
416 "FER", "FAR", "PTR", "FCR", "PCR",
417 "PMC", "TUP", "SID", "PNP0", "PNP1",
418 "LPTBA", NULL
419 };
420
421 static int
ppc_pc873xx_detect(struct ppc_data * ppc,int chipset_mode)422 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
423 {
424 static int index = 0;
425 int idport, irq;
426 int ptr, pcr, val, i;
427
428 while ((idport = pc873xx_basetab[index++])) {
429 /* XXX should check first to see if this location is already claimed */
430
431 /*
432 * Pull the 873xx through the power-on ID cycle (2.2,1.).
433 * We can't use this to locate the chip as it may already have
434 * been used by the BIOS.
435 */
436 (void)inb(idport); (void)inb(idport);
437 (void)inb(idport); (void)inb(idport);
438
439 /*
440 * Read the SID byte. Possible values are :
441 *
442 * 01010xxx PC87334
443 * 0001xxxx PC87332
444 * 01110xxx PC87306
445 * 00110xxx PC87303
446 */
447 outb(idport, PC873_SID);
448 val = inb(idport + 1);
449 if ((val & 0xf0) == 0x10) {
450 ppc->ppc_model = NS_PC87332;
451 } else if ((val & 0xf8) == 0x70) {
452 ppc->ppc_model = NS_PC87306;
453 } else if ((val & 0xf8) == 0x50) {
454 ppc->ppc_model = NS_PC87334;
455 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
456 documentation, but probing
457 yielded 0x40... */
458 ppc->ppc_model = NS_PC87303;
459 } else {
460 if (bootverbose && (val != 0xff))
461 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
462 continue ; /* not recognised */
463 }
464
465 /* print registers */
466 if (bootverbose) {
467 printf("PC873xx");
468 for (i=0; pc873xx_regstab[i] != -1; i++) {
469 outb(idport, pc873xx_regstab[i]);
470 printf(" %s=0x%x", pc873xx_rnametab[i],
471 inb(idport + 1) & 0xff);
472 }
473 printf("\n");
474 }
475
476 /*
477 * We think we have one. Is it enabled and where we want it to be?
478 */
479 outb(idport, PC873_FER);
480 val = inb(idport + 1);
481 if (!(val & PC873_PPENABLE)) {
482 if (bootverbose)
483 printf("PC873xx parallel port disabled\n");
484 continue;
485 }
486 outb(idport, PC873_FAR);
487 val = inb(idport + 1);
488 /* XXX we should create a driver instance for every port found */
489 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
490 /* First try to change the port address to that requested... */
491
492 switch (ppc->ppc_base) {
493 case 0x378:
494 val &= 0xfc;
495 break;
496
497 case 0x3bc:
498 val &= 0xfd;
499 break;
500
501 case 0x278:
502 val &= 0xfe;
503 break;
504
505 default:
506 val &= 0xfd;
507 break;
508 }
509
510 outb(idport, PC873_FAR);
511 outb(idport + 1, val);
512 outb(idport + 1, val);
513
514 /* Check for success by reading back the value we supposedly
515 wrote and comparing...*/
516
517 outb(idport, PC873_FAR);
518 val = inb(idport + 1) & 0x3;
519
520 /* If we fail, report the failure... */
521
522 if (pc873xx_porttab[val] != ppc->ppc_base) {
523 if (bootverbose)
524 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
525 pc873xx_porttab[val], ppc->ppc_base);
526 }
527 continue;
528 }
529
530 outb(idport, PC873_PTR);
531 ptr = inb(idport + 1);
532
533 /* get irq settings */
534 if (ppc->ppc_base == 0x378)
535 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
536 else
537 irq = pc873xx_irqtab[val];
538
539 if (bootverbose)
540 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
541
542 /*
543 * Check if irq settings are correct
544 */
545 if (irq != ppc->ppc_irq) {
546 /*
547 * If the chipset is not locked and base address is 0x378,
548 * we have another chance
549 */
550 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
551 if (ppc->ppc_irq == 7) {
552 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
553 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
554 } else {
555 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
556 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
557 }
558 if (bootverbose)
559 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
560 } else {
561 if (bootverbose)
562 printf("PC873xx sorry, can't change irq setting\n");
563 }
564 } else {
565 if (bootverbose)
566 printf("PC873xx irq settings are correct\n");
567 }
568
569 outb(idport, PC873_PCR);
570 pcr = inb(idport + 1);
571
572 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
573 if (bootverbose)
574 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
575
576 ppc->ppc_avm |= PPB_NIBBLE;
577 if (bootverbose)
578 printf(", NIBBLE");
579
580 if (pcr & PC873_EPPEN) {
581 ppc->ppc_avm |= PPB_EPP;
582
583 if (bootverbose)
584 printf(", EPP");
585
586 if (pcr & PC873_EPP19)
587 ppc->ppc_epp = EPP_1_9;
588 else
589 ppc->ppc_epp = EPP_1_7;
590
591 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
592 outb(idport, PC873_PTR);
593 ptr = inb(idport + 1);
594 if (ptr & PC873_EPPRDIR)
595 printf(", Regular mode");
596 else
597 printf(", Automatic mode");
598 }
599 } else if (pcr & PC873_ECPEN) {
600 ppc->ppc_avm |= PPB_ECP;
601 if (bootverbose)
602 printf(", ECP");
603
604 if (pcr & PC873_ECPCLK) { /* XXX */
605 ppc->ppc_avm |= PPB_PS2;
606 if (bootverbose)
607 printf(", PS/2");
608 }
609 } else {
610 outb(idport, PC873_PTR);
611 ptr = inb(idport + 1);
612 if (ptr & PC873_EXTENDED) {
613 ppc->ppc_avm |= PPB_SPP;
614 if (bootverbose)
615 printf(", SPP");
616 }
617 }
618 } else {
619 if (bootverbose)
620 printf("PC873xx unlocked");
621
622 if (chipset_mode & PPB_ECP) {
623 if ((chipset_mode & PPB_EPP) && bootverbose)
624 printf(", ECP+EPP not supported");
625
626 pcr &= ~PC873_EPPEN;
627 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
628 outb(idport + 1, pcr);
629 outb(idport + 1, pcr);
630
631 if (bootverbose)
632 printf(", ECP");
633
634 } else if (chipset_mode & PPB_EPP) {
635 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
636 pcr |= (PC873_EPPEN | PC873_EPP19);
637 outb(idport + 1, pcr);
638 outb(idport + 1, pcr);
639
640 ppc->ppc_epp = EPP_1_9; /* XXX */
641
642 if (bootverbose)
643 printf(", EPP1.9");
644
645 /* enable automatic direction turnover */
646 if (ppc->ppc_model == NS_PC87332) {
647 outb(idport, PC873_PTR);
648 ptr = inb(idport + 1);
649 ptr &= ~PC873_EPPRDIR;
650 outb(idport + 1, ptr);
651 outb(idport + 1, ptr);
652
653 if (bootverbose)
654 printf(", Automatic mode");
655 }
656 } else {
657 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
658 outb(idport + 1, pcr);
659 outb(idport + 1, pcr);
660
661 /* configure extended bit in PTR */
662 outb(idport, PC873_PTR);
663 ptr = inb(idport + 1);
664
665 if (chipset_mode & PPB_PS2) {
666 ptr |= PC873_EXTENDED;
667
668 if (bootverbose)
669 printf(", PS/2");
670
671 } else {
672 /* default to NIBBLE mode */
673 ptr &= ~PC873_EXTENDED;
674
675 if (bootverbose)
676 printf(", NIBBLE");
677 }
678 outb(idport + 1, ptr);
679 outb(idport + 1, ptr);
680 }
681
682 ppc->ppc_avm = chipset_mode;
683 }
684
685 if (bootverbose)
686 printf("\n");
687
688 ppc->ppc_type = PPC_TYPE_GENERIC;
689 ppc_generic_setmode(ppc, chipset_mode);
690
691 return(chipset_mode);
692 }
693 return(-1);
694 }
695
696 /*
697 * ppc_smc37c66xgt_detect
698 *
699 * SMC FDC37C66xGT configuration.
700 */
701 static int
ppc_smc37c66xgt_detect(struct ppc_data * ppc,int chipset_mode)702 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
703 {
704 int i;
705 u_char r;
706 int type = -1;
707 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
708
709 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
710
711 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
712
713 /*
714 * Detection: enter configuration mode and read CRD register.
715 */
716 PPC_CONFIG_LOCK(ppc);
717 outb(csr, SMC665_iCODE);
718 outb(csr, SMC665_iCODE);
719 PPC_CONFIG_UNLOCK(ppc);
720
721 outb(csr, 0xd);
722 if (inb(cio) == 0x65) {
723 type = SMC_37C665GT;
724 goto config;
725 }
726
727 for (i = 0; i < 2; i++) {
728 PPC_CONFIG_LOCK(ppc);
729 outb(csr, SMC666_iCODE);
730 outb(csr, SMC666_iCODE);
731 PPC_CONFIG_UNLOCK(ppc);
732
733 outb(csr, 0xd);
734 if (inb(cio) == 0x66) {
735 type = SMC_37C666GT;
736 break;
737 }
738
739 /* Another chance, CSR may be hard-configured to be at 0x370 */
740 csr = SMC666_CSR;
741 }
742
743 config:
744 /*
745 * If chipset not found, do not continue.
746 */
747 if (type == -1) {
748 outb(csr, 0xaa); /* end config mode */
749 return (-1);
750 }
751
752 /* select CR1 */
753 outb(csr, 0x1);
754
755 /* read the port's address: bits 0 and 1 of CR1 */
756 r = inb(cio) & SMC_CR1_ADDR;
757 if (port_address[(int)r] != ppc->ppc_base) {
758 outb(csr, 0xaa); /* end config mode */
759 return (-1);
760 }
761
762 ppc->ppc_model = type;
763
764 /*
765 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
766 * If SPP mode is detected, try to set ECP+EPP mode
767 */
768
769 if (bootverbose) {
770 outb(csr, 0x1);
771 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
772 inb(cio) & 0xff);
773
774 outb(csr, 0x4);
775 printf(" CR4=0x%x", inb(cio) & 0xff);
776 }
777
778 /* select CR1 */
779 outb(csr, 0x1);
780
781 if (!chipset_mode) {
782 /* autodetect mode */
783
784 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
785 if (type == SMC_37C666GT) {
786 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
787 if (bootverbose)
788 printf(" configuration hardwired, supposing " \
789 "ECP+EPP SPP");
790
791 } else
792 if ((inb(cio) & SMC_CR1_MODE) == 0) {
793 /* already in extended parallel port mode, read CR4 */
794 outb(csr, 0x4);
795 r = (inb(cio) & SMC_CR4_EMODE);
796
797 switch (r) {
798 case SMC_SPP:
799 ppc->ppc_avm |= PPB_SPP;
800 if (bootverbose)
801 printf(" SPP");
802 break;
803
804 case SMC_EPPSPP:
805 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
806 if (bootverbose)
807 printf(" EPP SPP");
808 break;
809
810 case SMC_ECP:
811 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
812 if (bootverbose)
813 printf(" ECP SPP");
814 break;
815
816 case SMC_ECPEPP:
817 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
818 if (bootverbose)
819 printf(" ECP+EPP SPP");
820 break;
821 }
822 } else {
823 /* not an extended port mode */
824 ppc->ppc_avm |= PPB_SPP;
825 if (bootverbose)
826 printf(" SPP");
827 }
828
829 } else {
830 /* mode forced */
831 ppc->ppc_avm = chipset_mode;
832
833 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
834 if (type == SMC_37C666GT)
835 goto end_detect;
836
837 r = inb(cio);
838 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
839 /* do not use ECP when the mode is not forced to */
840 outb(cio, r | SMC_CR1_MODE);
841 if (bootverbose)
842 printf(" SPP");
843 } else {
844 /* an extended mode is selected */
845 outb(cio, r & ~SMC_CR1_MODE);
846
847 /* read CR4 register and reset mode field */
848 outb(csr, 0x4);
849 r = inb(cio) & ~SMC_CR4_EMODE;
850
851 if (chipset_mode & PPB_ECP) {
852 if (chipset_mode & PPB_EPP) {
853 outb(cio, r | SMC_ECPEPP);
854 if (bootverbose)
855 printf(" ECP+EPP");
856 } else {
857 outb(cio, r | SMC_ECP);
858 if (bootverbose)
859 printf(" ECP");
860 }
861 } else {
862 /* PPB_EPP is set */
863 outb(cio, r | SMC_EPPSPP);
864 if (bootverbose)
865 printf(" EPP SPP");
866 }
867 }
868 ppc->ppc_avm = chipset_mode;
869 }
870
871 /* set FIFO threshold to 16 */
872 if (ppc->ppc_avm & PPB_ECP) {
873 /* select CRA */
874 outb(csr, 0xa);
875 outb(cio, 16);
876 }
877
878 end_detect:
879
880 if (bootverbose)
881 printf ("\n");
882
883 if (ppc->ppc_avm & PPB_EPP) {
884 /* select CR4 */
885 outb(csr, 0x4);
886 r = inb(cio);
887
888 /*
889 * Set the EPP protocol...
890 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
891 */
892 if (ppc->ppc_epp == EPP_1_9)
893 outb(cio, (r & ~SMC_CR4_EPPTYPE));
894 else
895 outb(cio, (r | SMC_CR4_EPPTYPE));
896 }
897
898 outb(csr, 0xaa); /* end config mode */
899
900 ppc->ppc_type = PPC_TYPE_SMCLIKE;
901 ppc_smclike_setmode(ppc, chipset_mode);
902
903 return (chipset_mode);
904 }
905
906 /*
907 * SMC FDC37C935 configuration
908 * Found on many Alpha machines
909 */
910 static int
ppc_smc37c935_detect(struct ppc_data * ppc,int chipset_mode)911 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
912 {
913 int type = -1;
914
915 PPC_CONFIG_LOCK(ppc);
916 outb(SMC935_CFG, 0x55); /* enter config mode */
917 outb(SMC935_CFG, 0x55);
918 PPC_CONFIG_UNLOCK(ppc);
919
920 outb(SMC935_IND, SMC935_ID); /* check device id */
921 if (inb(SMC935_DAT) == 0x2)
922 type = SMC_37C935;
923
924 if (type == -1) {
925 outb(SMC935_CFG, 0xaa); /* exit config mode */
926 return (-1);
927 }
928
929 ppc->ppc_model = type;
930
931 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
932 outb(SMC935_DAT, 3); /* which is logical device 3 */
933
934 /* set io port base */
935 outb(SMC935_IND, SMC935_PORTHI);
936 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
937 outb(SMC935_IND, SMC935_PORTLO);
938 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
939
940 if (!chipset_mode)
941 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
942 else {
943 ppc->ppc_avm = chipset_mode;
944 outb(SMC935_IND, SMC935_PPMODE);
945 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
946
947 /* SPP + EPP or just plain SPP */
948 if (chipset_mode & (PPB_SPP)) {
949 if (chipset_mode & PPB_EPP) {
950 if (ppc->ppc_epp == EPP_1_9) {
951 outb(SMC935_IND, SMC935_PPMODE);
952 outb(SMC935_DAT, SMC935_EPP19SPP);
953 }
954 if (ppc->ppc_epp == EPP_1_7) {
955 outb(SMC935_IND, SMC935_PPMODE);
956 outb(SMC935_DAT, SMC935_EPP17SPP);
957 }
958 } else {
959 outb(SMC935_IND, SMC935_PPMODE);
960 outb(SMC935_DAT, SMC935_SPP);
961 }
962 }
963
964 /* ECP + EPP or just plain ECP */
965 if (chipset_mode & PPB_ECP) {
966 if (chipset_mode & PPB_EPP) {
967 if (ppc->ppc_epp == EPP_1_9) {
968 outb(SMC935_IND, SMC935_PPMODE);
969 outb(SMC935_DAT, SMC935_ECPEPP19);
970 }
971 if (ppc->ppc_epp == EPP_1_7) {
972 outb(SMC935_IND, SMC935_PPMODE);
973 outb(SMC935_DAT, SMC935_ECPEPP17);
974 }
975 } else {
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_ECP);
978 }
979 }
980 }
981
982 outb(SMC935_CFG, 0xaa); /* exit config mode */
983
984 ppc->ppc_type = PPC_TYPE_SMCLIKE;
985 ppc_smclike_setmode(ppc, chipset_mode);
986
987 return (chipset_mode);
988 }
989
990 /*
991 * Winbond W83877F stuff
992 *
993 * EFER: extended function enable register
994 * EFIR: extended function index register
995 * EFDR: extended function data register
996 */
997 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
998 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
999
1000 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1001 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1002 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1003 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1004
1005 static int
ppc_w83877f_detect(struct ppc_data * ppc,int chipset_mode)1006 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1007 {
1008 int i, j, efer;
1009 unsigned char r, hefere, hefras;
1010
1011 for (i = 0; i < 4; i ++) {
1012 /* first try to enable configuration registers */
1013 efer = w83877f_efers[i];
1014
1015 /* write the key to the EFER */
1016 for (j = 0; j < w83877f_keyiter[i]; j ++)
1017 outb (efer, w83877f_keys[i]);
1018
1019 /* then check HEFERE and HEFRAS bits */
1020 outb (efir, 0x0c);
1021 hefere = inb(efdr) & WINB_HEFERE;
1022
1023 outb (efir, 0x16);
1024 hefras = inb(efdr) & WINB_HEFRAS;
1025
1026 /*
1027 * HEFRAS HEFERE
1028 * 0 1 write 89h to 250h (power-on default)
1029 * 1 0 write 86h twice to 3f0h
1030 * 1 1 write 87h twice to 3f0h
1031 * 0 0 write 88h to 250h
1032 */
1033 if ((hefere | hefras) == w83877f_hefs[i])
1034 goto found;
1035 }
1036
1037 return (-1); /* failed */
1038
1039 found:
1040 /* check base port address - read from CR23 */
1041 outb(efir, 0x23);
1042 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1043 return (-1);
1044
1045 /* read CHIP ID from CR9/bits0-3 */
1046 outb(efir, 0x9);
1047
1048 switch (inb(efdr) & WINB_CHIPID) {
1049 case WINB_W83877F_ID:
1050 ppc->ppc_model = WINB_W83877F;
1051 break;
1052
1053 case WINB_W83877AF_ID:
1054 ppc->ppc_model = WINB_W83877AF;
1055 break;
1056
1057 default:
1058 ppc->ppc_model = WINB_UNKNOWN;
1059 }
1060
1061 if (bootverbose) {
1062 /* dump of registers */
1063 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1064 for (i = 0; i <= 0xd; i ++) {
1065 outb(efir, i);
1066 printf("0x%x ", inb(efdr));
1067 }
1068 for (i = 0x10; i <= 0x17; i ++) {
1069 outb(efir, i);
1070 printf("0x%x ", inb(efdr));
1071 }
1072 outb(efir, 0x1e);
1073 printf("0x%x ", inb(efdr));
1074 for (i = 0x20; i <= 0x29; i ++) {
1075 outb(efir, i);
1076 printf("0x%x ", inb(efdr));
1077 }
1078 printf("\n");
1079 }
1080
1081 ppc->ppc_type = PPC_TYPE_GENERIC;
1082
1083 if (!chipset_mode) {
1084 /* autodetect mode */
1085
1086 /* select CR0 */
1087 outb(efir, 0x0);
1088 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1089
1090 /* select CR9 */
1091 outb(efir, 0x9);
1092 r |= (inb(efdr) & WINB_PRTMODS2);
1093
1094 switch (r) {
1095 case WINB_W83757:
1096 if (bootverbose)
1097 device_printf(ppc->ppc_dev,
1098 "W83757 compatible mode\n");
1099 return (-1); /* generic or SMC-like */
1100
1101 case WINB_EXTFDC:
1102 case WINB_EXTADP:
1103 case WINB_EXT2FDD:
1104 case WINB_JOYSTICK:
1105 if (bootverbose)
1106 device_printf(ppc->ppc_dev,
1107 "not in parallel port mode\n");
1108 return (-1);
1109
1110 case (WINB_PARALLEL | WINB_EPP_SPP):
1111 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1112 if (bootverbose)
1113 device_printf(ppc->ppc_dev, "EPP SPP\n");
1114 break;
1115
1116 case (WINB_PARALLEL | WINB_ECP):
1117 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1118 if (bootverbose)
1119 device_printf(ppc->ppc_dev, "ECP SPP\n");
1120 break;
1121
1122 case (WINB_PARALLEL | WINB_ECP_EPP):
1123 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1124 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1125
1126 if (bootverbose)
1127 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1128 break;
1129 default:
1130 printf("%s: unknown case (0x%x)!\n", __func__, r);
1131 }
1132
1133 } else {
1134 /* mode forced */
1135
1136 /* select CR9 and set PRTMODS2 bit */
1137 outb(efir, 0x9);
1138 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1139
1140 /* select CR0 and reset PRTMODSx bits */
1141 outb(efir, 0x0);
1142 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1143
1144 if (chipset_mode & PPB_ECP) {
1145 if (chipset_mode & PPB_EPP) {
1146 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1147 if (bootverbose)
1148 device_printf(ppc->ppc_dev,
1149 "ECP+EPP\n");
1150
1151 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1152
1153 } else {
1154 outb(efdr, inb(efdr) | WINB_ECP);
1155 if (bootverbose)
1156 device_printf(ppc->ppc_dev, "ECP\n");
1157 }
1158 } else {
1159 /* select EPP_SPP otherwise */
1160 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1161 if (bootverbose)
1162 device_printf(ppc->ppc_dev, "EPP SPP\n");
1163 }
1164 ppc->ppc_avm = chipset_mode;
1165 }
1166
1167 /* exit configuration mode */
1168 outb(efer, 0xaa);
1169
1170 switch (ppc->ppc_type) {
1171 case PPC_TYPE_SMCLIKE:
1172 ppc_smclike_setmode(ppc, chipset_mode);
1173 break;
1174 default:
1175 ppc_generic_setmode(ppc, chipset_mode);
1176 break;
1177 }
1178
1179 return (chipset_mode);
1180 }
1181 #endif
1182
1183 /*
1184 * ppc_generic_detect
1185 */
1186 static int
ppc_generic_detect(struct ppc_data * ppc,int chipset_mode)1187 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1188 {
1189 /* default to generic */
1190 ppc->ppc_type = PPC_TYPE_GENERIC;
1191
1192 if (bootverbose)
1193 device_printf(ppc->ppc_dev, "SPP");
1194
1195 /* first, check for ECP */
1196 w_ecr(ppc, PPC_ECR_PS2);
1197 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1198 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1199 if (bootverbose)
1200 printf(" ECP ");
1201
1202 /* search for SMC style ECP+EPP mode */
1203 w_ecr(ppc, PPC_ECR_EPP);
1204 }
1205
1206 /* try to reset EPP timeout bit */
1207 if (ppc_check_epp_timeout(ppc)) {
1208 ppc->ppc_dtm |= PPB_EPP;
1209
1210 if (ppc->ppc_dtm & PPB_ECP) {
1211 /* SMC like chipset found */
1212 ppc->ppc_model = SMC_LIKE;
1213 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1214
1215 if (bootverbose)
1216 printf(" ECP+EPP");
1217 } else {
1218 if (bootverbose)
1219 printf(" EPP");
1220 }
1221 } else {
1222 /* restore to standard mode */
1223 w_ecr(ppc, PPC_ECR_STD);
1224 }
1225
1226 /* XXX try to detect NIBBLE and PS2 modes */
1227 ppc->ppc_dtm |= PPB_NIBBLE;
1228
1229 if (chipset_mode)
1230 ppc->ppc_avm = chipset_mode;
1231 else
1232 ppc->ppc_avm = ppc->ppc_dtm;
1233
1234 if (bootverbose)
1235 printf("\n");
1236
1237 switch (ppc->ppc_type) {
1238 case PPC_TYPE_SMCLIKE:
1239 ppc_smclike_setmode(ppc, chipset_mode);
1240 break;
1241 default:
1242 ppc_generic_setmode(ppc, chipset_mode);
1243 break;
1244 }
1245
1246 return (chipset_mode);
1247 }
1248
1249 /*
1250 * ppc_detect()
1251 *
1252 * mode is the mode suggested at boot
1253 */
1254 static int
ppc_detect(struct ppc_data * ppc,int chipset_mode)1255 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1256 #ifdef PPC_PROBE_CHIPSET
1257 int i, mode;
1258
1259 /* list of supported chipsets */
1260 int (*chipset_detect[])(struct ppc_data *, int) = {
1261 ppc_pc873xx_detect,
1262 ppc_smc37c66xgt_detect,
1263 ppc_w83877f_detect,
1264 ppc_smc37c935_detect,
1265 ppc_generic_detect,
1266 NULL
1267 };
1268 #endif
1269
1270 /* if can't find the port and mode not forced return error */
1271 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1272 return (EIO); /* failed, port not present */
1273
1274 /* assume centronics compatible mode is supported */
1275 ppc->ppc_avm = PPB_COMPATIBLE;
1276
1277 #ifdef PPC_PROBE_CHIPSET
1278 /* we have to differenciate available chipset modes,
1279 * chipset running modes and IEEE-1284 operating modes
1280 *
1281 * after detection, the port must support running in compatible mode
1282 */
1283 if (ppc->ppc_flags & 0x40) {
1284 if (bootverbose)
1285 printf("ppc: chipset forced to generic\n");
1286 #endif
1287
1288 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1289
1290 #ifdef PPC_PROBE_CHIPSET
1291 } else {
1292 for (i=0; chipset_detect[i] != NULL; i++) {
1293 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1294 ppc->ppc_mode = mode;
1295 break;
1296 }
1297 }
1298 }
1299 #endif
1300
1301 /* configure/detect ECP FIFO */
1302 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1303 ppc_detect_fifo(ppc);
1304
1305 return (0);
1306 }
1307
1308 /*
1309 * ppc_exec_microseq()
1310 *
1311 * Execute a microsequence.
1312 * Microsequence mechanism is supposed to handle fast I/O operations.
1313 */
1314 int
ppc_exec_microseq(device_t dev,struct ppb_microseq ** p_msq)1315 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1316 {
1317 struct ppc_data *ppc = DEVTOSOFTC(dev);
1318 struct ppb_microseq *mi;
1319 char cc, *p;
1320 int i, iter, len;
1321 int error;
1322
1323 int reg;
1324 char mask;
1325 int accum = 0;
1326 char *ptr = NULL;
1327
1328 struct ppb_microseq *stack = NULL;
1329
1330 /* microsequence registers are equivalent to PC-like port registers */
1331
1332 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1333 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1334
1335 #define INCR_PC (mi ++) /* increment program counter */
1336
1337 PPC_ASSERT_LOCKED(ppc);
1338 mi = *p_msq;
1339 for (;;) {
1340 switch (mi->opcode) {
1341 case MS_OP_RSET:
1342 cc = r_reg(mi->arg[0].i, ppc);
1343 cc &= (char)mi->arg[2].i; /* clear mask */
1344 cc |= (char)mi->arg[1].i; /* assert mask */
1345 w_reg(mi->arg[0].i, ppc, cc);
1346 INCR_PC;
1347 break;
1348
1349 case MS_OP_RASSERT_P:
1350 reg = mi->arg[1].i;
1351 ptr = ppc->ppc_ptr;
1352
1353 if ((len = mi->arg[0].i) == MS_ACCUM) {
1354 accum = ppc->ppc_accum;
1355 for (; accum; accum--)
1356 w_reg(reg, ppc, *ptr++);
1357 ppc->ppc_accum = accum;
1358 } else
1359 for (i=0; i<len; i++)
1360 w_reg(reg, ppc, *ptr++);
1361 ppc->ppc_ptr = ptr;
1362
1363 INCR_PC;
1364 break;
1365
1366 case MS_OP_RFETCH_P:
1367 reg = mi->arg[1].i;
1368 mask = (char)mi->arg[2].i;
1369 ptr = ppc->ppc_ptr;
1370
1371 if ((len = mi->arg[0].i) == MS_ACCUM) {
1372 accum = ppc->ppc_accum;
1373 for (; accum; accum--)
1374 *ptr++ = r_reg(reg, ppc) & mask;
1375 ppc->ppc_accum = accum;
1376 } else
1377 for (i=0; i<len; i++)
1378 *ptr++ = r_reg(reg, ppc) & mask;
1379 ppc->ppc_ptr = ptr;
1380
1381 INCR_PC;
1382 break;
1383
1384 case MS_OP_RFETCH:
1385 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1386 (char)mi->arg[1].i;
1387 INCR_PC;
1388 break;
1389
1390 case MS_OP_RASSERT:
1391 case MS_OP_DELAY:
1392
1393 /* let's suppose the next instr. is the same */
1394 prefetch:
1395 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1396 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1397
1398 if (mi->opcode == MS_OP_DELAY) {
1399 DELAY(mi->arg[0].i);
1400 INCR_PC;
1401 goto prefetch;
1402 }
1403 break;
1404
1405 case MS_OP_ADELAY:
1406 if (mi->arg[0].i) {
1407 PPC_UNLOCK(ppc);
1408 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1409 PPC_LOCK(ppc);
1410 }
1411 INCR_PC;
1412 break;
1413
1414 case MS_OP_TRIG:
1415 reg = mi->arg[0].i;
1416 iter = mi->arg[1].i;
1417 p = (char *)mi->arg[2].p;
1418
1419 /* XXX delay limited to 255 us */
1420 for (i=0; i<iter; i++) {
1421 w_reg(reg, ppc, *p++);
1422 DELAY((unsigned char)*p++);
1423 }
1424 INCR_PC;
1425 break;
1426
1427 case MS_OP_SET:
1428 ppc->ppc_accum = mi->arg[0].i;
1429 INCR_PC;
1430 break;
1431
1432 case MS_OP_DBRA:
1433 if (--ppc->ppc_accum > 0)
1434 mi += mi->arg[0].i;
1435 INCR_PC;
1436 break;
1437
1438 case MS_OP_BRSET:
1439 cc = r_str(ppc);
1440 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1441 mi += mi->arg[1].i;
1442 INCR_PC;
1443 break;
1444
1445 case MS_OP_BRCLEAR:
1446 cc = r_str(ppc);
1447 if ((cc & (char)mi->arg[0].i) == 0)
1448 mi += mi->arg[1].i;
1449 INCR_PC;
1450 break;
1451
1452 case MS_OP_BRSTAT:
1453 cc = r_str(ppc);
1454 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1455 (char)mi->arg[0].i)
1456 mi += mi->arg[2].i;
1457 INCR_PC;
1458 break;
1459
1460 case MS_OP_C_CALL:
1461 /*
1462 * If the C call returns !0 then end the microseq.
1463 * The current state of ptr is passed to the C function
1464 */
1465 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1466 return (error);
1467
1468 INCR_PC;
1469 break;
1470
1471 case MS_OP_PTR:
1472 ppc->ppc_ptr = (char *)mi->arg[0].p;
1473 INCR_PC;
1474 break;
1475
1476 case MS_OP_CALL:
1477 if (stack)
1478 panic("%s: too much calls", __func__);
1479
1480 if (mi->arg[0].p) {
1481 /* store the state of the actual
1482 * microsequence
1483 */
1484 stack = mi;
1485
1486 /* jump to the new microsequence */
1487 mi = (struct ppb_microseq *)mi->arg[0].p;
1488 } else
1489 INCR_PC;
1490
1491 break;
1492
1493 case MS_OP_SUBRET:
1494 /* retrieve microseq and pc state before the call */
1495 mi = stack;
1496
1497 /* reset the stack */
1498 stack = NULL;
1499
1500 /* XXX return code */
1501
1502 INCR_PC;
1503 break;
1504
1505 case MS_OP_PUT:
1506 case MS_OP_GET:
1507 case MS_OP_RET:
1508 /* can't return to ppb level during the execution
1509 * of a submicrosequence */
1510 if (stack)
1511 panic("%s: can't return to ppb level",
1512 __func__);
1513
1514 /* update pc for ppb level of execution */
1515 *p_msq = mi;
1516
1517 /* return to ppb level of execution */
1518 return (0);
1519
1520 default:
1521 panic("%s: unknown microsequence opcode 0x%x",
1522 __func__, mi->opcode);
1523 }
1524 }
1525
1526 /* unreached */
1527 }
1528
1529 static void
ppcintr(void * arg)1530 ppcintr(void *arg)
1531 {
1532 struct ppc_data *ppc = arg;
1533 u_char ctr, ecr, str;
1534
1535 /*
1536 * If we have any child interrupt handlers registered, let
1537 * them handle this interrupt.
1538 *
1539 * XXX: If DMA is in progress should we just complete that w/o
1540 * doing this?
1541 */
1542 PPC_LOCK(ppc);
1543 if (ppc->ppc_intr_hook != NULL &&
1544 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) {
1545 PPC_UNLOCK(ppc);
1546 return;
1547 }
1548
1549 str = r_str(ppc);
1550 ctr = r_ctr(ppc);
1551 ecr = r_ecr(ppc);
1552
1553 #if defined(PPC_DEBUG) && PPC_DEBUG > 1
1554 printf("![%x/%x/%x]", ctr, ecr, str);
1555 #endif
1556
1557 /* don't use ecp mode with IRQENABLE set */
1558 if (ctr & IRQENABLE) {
1559 PPC_UNLOCK(ppc);
1560 return;
1561 }
1562
1563 /* interrupts are generated by nFault signal
1564 * only in ECP mode */
1565 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1566 /* check if ppc driver has programmed the
1567 * nFault interrupt */
1568 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1569 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1570 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1571 } else {
1572 /* shall be handled by underlying layers XXX */
1573 PPC_UNLOCK(ppc);
1574 return;
1575 }
1576 }
1577
1578 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1579 /* disable interrupts (should be done by hardware though) */
1580 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1581 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1582 ecr = r_ecr(ppc);
1583
1584 /* check if DMA completed */
1585 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1586 #ifdef PPC_DEBUG
1587 printf("a");
1588 #endif
1589 /* stop DMA */
1590 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1591 ecr = r_ecr(ppc);
1592
1593 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1594 #ifdef PPC_DEBUG
1595 printf("d");
1596 #endif
1597 ppc->ppc_dmadone(ppc);
1598 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1599
1600 /* wakeup the waiting process */
1601 wakeup(ppc);
1602 }
1603 }
1604 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1605 /* classic interrupt I/O */
1606 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1607 }
1608 PPC_UNLOCK(ppc);
1609
1610 return;
1611 }
1612
1613 int
ppc_read(device_t dev,char * buf,int len,int mode)1614 ppc_read(device_t dev, char *buf, int len, int mode)
1615 {
1616 return (EINVAL);
1617 }
1618
1619 int
ppc_write(device_t dev,char * buf,int len,int how)1620 ppc_write(device_t dev, char *buf, int len, int how)
1621 {
1622 return (EINVAL);
1623 }
1624
1625 int
ppc_reset_epp(device_t dev)1626 ppc_reset_epp(device_t dev)
1627 {
1628 struct ppc_data *ppc = DEVTOSOFTC(dev);
1629
1630 PPC_ASSERT_LOCKED(ppc);
1631 ppc_reset_epp_timeout(ppc);
1632
1633 return 0;
1634 }
1635
1636 int
ppc_setmode(device_t dev,int mode)1637 ppc_setmode(device_t dev, int mode)
1638 {
1639 struct ppc_data *ppc = DEVTOSOFTC(dev);
1640
1641 PPC_ASSERT_LOCKED(ppc);
1642 switch (ppc->ppc_type) {
1643 case PPC_TYPE_SMCLIKE:
1644 return (ppc_smclike_setmode(ppc, mode));
1645 break;
1646
1647 case PPC_TYPE_GENERIC:
1648 default:
1649 return (ppc_generic_setmode(ppc, mode));
1650 break;
1651 }
1652
1653 /* not reached */
1654 return (ENXIO);
1655 }
1656
1657 int
ppc_probe(device_t dev,int rid)1658 ppc_probe(device_t dev, int rid)
1659 {
1660 #ifdef __i386__
1661 static short next_bios_ppc = 0;
1662 #endif
1663 struct ppc_data *ppc;
1664 int error;
1665 rman_res_t port;
1666
1667 /*
1668 * Allocate the ppc_data structure.
1669 */
1670 ppc = DEVTOSOFTC(dev);
1671 bzero(ppc, sizeof(struct ppc_data));
1672
1673 ppc->rid_ioport = rid;
1674
1675 /* retrieve ISA parameters */
1676 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1677
1678 #ifdef __i386__
1679 /*
1680 * If port not specified, use bios list.
1681 */
1682 if (error) {
1683 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1684 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1685 port = *(BIOS_PORTS + next_bios_ppc++);
1686 if (bootverbose)
1687 device_printf(dev,
1688 "parallel port found at 0x%jx\n", port);
1689 } else {
1690 device_printf(dev, "parallel port not found.\n");
1691 return (ENXIO);
1692 }
1693 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1694 IO_LPTSIZE_EXTENDED);
1695 }
1696 #endif
1697
1698 /* IO port is mandatory */
1699
1700 /* Try "extended" IO port range...*/
1701 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1702 &ppc->rid_ioport,
1703 IO_LPTSIZE_EXTENDED,
1704 RF_ACTIVE);
1705
1706 if (ppc->res_ioport != 0) {
1707 if (bootverbose)
1708 device_printf(dev, "using extended I/O port range\n");
1709 } else {
1710 /* Failed? If so, then try the "normal" IO port range... */
1711 ppc->res_ioport = bus_alloc_resource_anywhere(dev,
1712 SYS_RES_IOPORT,
1713 &ppc->rid_ioport,
1714 IO_LPTSIZE_NORMAL,
1715 RF_ACTIVE);
1716 if (ppc->res_ioport != 0) {
1717 if (bootverbose)
1718 device_printf(dev, "using normal I/O port range\n");
1719 } else {
1720 if (bootverbose)
1721 device_printf(dev, "cannot reserve I/O port range\n");
1722 goto error;
1723 }
1724 }
1725
1726 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1727
1728 ppc->ppc_flags = device_get_flags(dev);
1729
1730 if (!(ppc->ppc_flags & 0x20)) {
1731 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1732 &ppc->rid_irq,
1733 RF_SHAREABLE);
1734 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1735 &ppc->rid_drq,
1736 RF_ACTIVE);
1737 }
1738
1739 if (ppc->res_irq)
1740 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1741 if (ppc->res_drq)
1742 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1743
1744 ppc->ppc_dev = dev;
1745 ppc->ppc_model = GENERIC;
1746
1747 ppc->ppc_mode = PPB_COMPATIBLE;
1748 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1749
1750 ppc->ppc_type = PPC_TYPE_GENERIC;
1751
1752 /*
1753 * Try to detect the chipset and its mode.
1754 */
1755 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1756 goto error;
1757
1758 return (0);
1759
1760 error:
1761 if (ppc->res_irq != 0) {
1762 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1763 ppc->res_irq);
1764 }
1765 if (ppc->res_ioport != 0) {
1766 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1767 ppc->res_ioport);
1768 }
1769 if (ppc->res_drq != 0) {
1770 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1771 ppc->res_drq);
1772 }
1773 return (ENXIO);
1774 }
1775
1776 int
ppc_attach(device_t dev)1777 ppc_attach(device_t dev)
1778 {
1779 struct ppc_data *ppc = DEVTOSOFTC(dev);
1780 int error;
1781
1782 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF);
1783
1784 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1785 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1786 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1787 ppc_epp_protocol[ppc->ppc_epp] : "");
1788
1789 if (ppc->ppc_fifo)
1790 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1791 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1792
1793 if (ppc->res_irq) {
1794 /* default to the tty mask for registration */ /* XXX */
1795 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY |
1796 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie);
1797 if (error) {
1798 device_printf(dev,
1799 "failed to register interrupt handler: %d\n",
1800 error);
1801 mtx_destroy(&ppc->ppc_lock);
1802 return (error);
1803 }
1804 }
1805
1806 /* add ppbus as a child of this isa to parallel bridge */
1807 ppc->ppbus = device_add_child(dev, "ppbus", -1);
1808
1809 /*
1810 * Probe the ppbus and attach devices found.
1811 */
1812 device_probe_and_attach(ppc->ppbus);
1813
1814 return (0);
1815 }
1816
1817 int
ppc_detach(device_t dev)1818 ppc_detach(device_t dev)
1819 {
1820 struct ppc_data *ppc = DEVTOSOFTC(dev);
1821
1822 if (ppc->res_irq == 0) {
1823 return (ENXIO);
1824 }
1825
1826 /* detach & delete all children */
1827 device_delete_children(dev);
1828
1829 if (ppc->res_irq != 0) {
1830 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1831 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1832 ppc->res_irq);
1833 }
1834 if (ppc->res_ioport != 0) {
1835 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1836 ppc->res_ioport);
1837 }
1838 if (ppc->res_drq != 0) {
1839 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1840 ppc->res_drq);
1841 }
1842
1843 mtx_destroy(&ppc->ppc_lock);
1844
1845 return (0);
1846 }
1847
1848 u_char
ppc_io(device_t ppcdev,int iop,u_char * addr,int cnt,u_char byte)1849 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1850 {
1851 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1852
1853 PPC_ASSERT_LOCKED(ppc);
1854 switch (iop) {
1855 case PPB_OUTSB_EPP:
1856 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1857 break;
1858 case PPB_OUTSW_EPP:
1859 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1860 break;
1861 case PPB_OUTSL_EPP:
1862 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1863 break;
1864 case PPB_INSB_EPP:
1865 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1866 break;
1867 case PPB_INSW_EPP:
1868 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1869 break;
1870 case PPB_INSL_EPP:
1871 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1872 break;
1873 case PPB_RDTR:
1874 return (r_dtr(ppc));
1875 case PPB_RSTR:
1876 return (r_str(ppc));
1877 case PPB_RCTR:
1878 return (r_ctr(ppc));
1879 case PPB_REPP_A:
1880 return (r_epp_A(ppc));
1881 case PPB_REPP_D:
1882 return (r_epp_D(ppc));
1883 case PPB_RECR:
1884 return (r_ecr(ppc));
1885 case PPB_RFIFO:
1886 return (r_fifo(ppc));
1887 case PPB_WDTR:
1888 w_dtr(ppc, byte);
1889 break;
1890 case PPB_WSTR:
1891 w_str(ppc, byte);
1892 break;
1893 case PPB_WCTR:
1894 w_ctr(ppc, byte);
1895 break;
1896 case PPB_WEPP_A:
1897 w_epp_A(ppc, byte);
1898 break;
1899 case PPB_WEPP_D:
1900 w_epp_D(ppc, byte);
1901 break;
1902 case PPB_WECR:
1903 w_ecr(ppc, byte);
1904 break;
1905 case PPB_WFIFO:
1906 w_fifo(ppc, byte);
1907 break;
1908 default:
1909 panic("%s: unknown I/O operation", __func__);
1910 break;
1911 }
1912
1913 return (0); /* not significative */
1914 }
1915
1916 int
ppc_read_ivar(device_t bus,device_t dev,int index,uintptr_t * val)1917 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1918 {
1919 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1920
1921 switch (index) {
1922 case PPC_IVAR_EPP_PROTO:
1923 PPC_ASSERT_LOCKED(ppc);
1924 *val = (u_long)ppc->ppc_epp;
1925 break;
1926 case PPC_IVAR_LOCK:
1927 *val = (uintptr_t)&ppc->ppc_lock;
1928 break;
1929 default:
1930 return (ENOENT);
1931 }
1932
1933 return (0);
1934 }
1935
1936 int
ppc_write_ivar(device_t bus,device_t dev,int index,uintptr_t val)1937 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
1938 {
1939 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1940
1941 switch (index) {
1942 case PPC_IVAR_INTR_HANDLER:
1943 PPC_ASSERT_LOCKED(ppc);
1944 if (dev != ppc->ppbus)
1945 return (EINVAL);
1946 if (val == 0) {
1947 ppc->ppc_intr_hook = NULL;
1948 break;
1949 }
1950 if (ppc->ppc_intr_hook != NULL)
1951 return (EBUSY);
1952 ppc->ppc_intr_hook = (void *)val;
1953 ppc->ppc_intr_arg = device_get_softc(dev);
1954 break;
1955 default:
1956 return (ENOENT);
1957 }
1958
1959 return (0);
1960 }
1961
1962 /*
1963 * We allow child devices to allocate an IRQ resource at rid 0 for their
1964 * interrupt handlers.
1965 */
1966 struct resource *
ppc_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)1967 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1968 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1969 {
1970 struct ppc_data *ppc = DEVTOSOFTC(bus);
1971
1972 switch (type) {
1973 case SYS_RES_IRQ:
1974 if (*rid == 0)
1975 return (ppc->res_irq);
1976 break;
1977 }
1978 return (NULL);
1979 }
1980
1981 int
ppc_release_resource(device_t bus,device_t child,int type,int rid,struct resource * r)1982 ppc_release_resource(device_t bus, device_t child, int type, int rid,
1983 struct resource *r)
1984 {
1985 #ifdef INVARIANTS
1986 struct ppc_data *ppc = DEVTOSOFTC(bus);
1987 #endif
1988
1989 switch (type) {
1990 case SYS_RES_IRQ:
1991 if (rid == 0) {
1992 KASSERT(r == ppc->res_irq,
1993 ("ppc child IRQ resource mismatch"));
1994 return (0);
1995 }
1996 break;
1997 }
1998 return (EINVAL);
1999 }
2000
2001 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);
2002