1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 Alexander Motin <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/ata.h>
37 #include <sys/bus.h>
38 #include <sys/conf.h>
39 #include <sys/endian.h>
40 #include <sys/malloc.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <vm/uma.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
47 #include <sys/rman.h>
48 #include <dev/pci/pcivar.h>
49 #include "mvs.h"
50
51 #include <cam/cam.h>
52 #include <cam/cam_ccb.h>
53 #include <cam/cam_sim.h>
54 #include <cam/cam_xpt_sim.h>
55 #include <cam/cam_debug.h>
56
57 /* local prototypes */
58 static int mvs_ch_init(device_t dev);
59 static int mvs_ch_deinit(device_t dev);
60 static int mvs_ch_suspend(device_t dev);
61 static int mvs_ch_resume(device_t dev);
62 static void mvs_dmainit(device_t dev);
63 static void mvs_dmasetupc_cb(void *xsc,
64 bus_dma_segment_t *segs, int nsegs, int error);
65 static void mvs_dmafini(device_t dev);
66 static void mvs_slotsalloc(device_t dev);
67 static void mvs_slotsfree(device_t dev);
68 static void mvs_setup_edma_queues(device_t dev);
69 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode);
70 static void mvs_ch_pm(void *arg);
71 static void mvs_ch_intr_locked(void *data);
72 static void mvs_ch_intr(void *data);
73 static void mvs_reset(device_t dev);
74 static void mvs_softreset(device_t dev, union ccb *ccb);
75
76 static int mvs_sata_connect(struct mvs_channel *ch);
77 static int mvs_sata_phy_reset(device_t dev);
78 static int mvs_wait(device_t dev, u_int s, u_int c, int t);
79 static void mvs_tfd_read(device_t dev, union ccb *ccb);
80 static void mvs_tfd_write(device_t dev, union ccb *ccb);
81 static void mvs_legacy_intr(device_t dev, int poll);
82 static void mvs_crbq_intr(device_t dev);
83 static void mvs_begin_transaction(device_t dev, union ccb *ccb);
84 static void mvs_legacy_execute_transaction(struct mvs_slot *slot);
85 static void mvs_timeout(void *arg);
86 static void mvs_dmasetprd(void *arg,
87 bus_dma_segment_t *segs, int nsegs, int error);
88 static void mvs_requeue_frozen(device_t dev);
89 static void mvs_execute_transaction(struct mvs_slot *slot);
90 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et);
91
92 static void mvs_issue_recovery(device_t dev);
93 static void mvs_process_read_log(device_t dev, union ccb *ccb);
94 static void mvs_process_request_sense(device_t dev, union ccb *ccb);
95
96 static void mvsaction(struct cam_sim *sim, union ccb *ccb);
97 static void mvspoll(struct cam_sim *sim);
98
99 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers");
100
101 #define recovery_type spriv_field0
102 #define RECOVERY_NONE 0
103 #define RECOVERY_READ_LOG 1
104 #define RECOVERY_REQUEST_SENSE 2
105 #define recovery_slot spriv_field1
106
107 static int
mvs_ch_probe(device_t dev)108 mvs_ch_probe(device_t dev)
109 {
110
111 device_set_desc_copy(dev, "Marvell SATA channel");
112 return (BUS_PROBE_DEFAULT);
113 }
114
115 static int
mvs_ch_attach(device_t dev)116 mvs_ch_attach(device_t dev)
117 {
118 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev));
119 struct mvs_channel *ch = device_get_softc(dev);
120 struct cam_devq *devq;
121 int rid, error, i, sata_rev = 0;
122
123 ch->dev = dev;
124 ch->unit = (intptr_t)device_get_ivars(dev);
125 ch->quirks = ctlr->quirks;
126 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF);
127 ch->pm_level = 0;
128 resource_int_value(device_get_name(dev),
129 device_get_unit(dev), "pm_level", &ch->pm_level);
130 if (ch->pm_level > 3)
131 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
132 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
133 resource_int_value(device_get_name(dev),
134 device_get_unit(dev), "sata_rev", &sata_rev);
135 for (i = 0; i < 16; i++) {
136 ch->user[i].revision = sata_rev;
137 ch->user[i].mode = 0;
138 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048;
139 ch->user[i].tags = MVS_MAX_SLOTS;
140 ch->curr[i] = ch->user[i];
141 if (ch->pm_level) {
142 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
143 CTS_SATA_CAPS_H_APST |
144 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
145 }
146 ch->user[i].caps |= CTS_SATA_CAPS_H_AN;
147 }
148 rid = ch->unit;
149 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
150 &rid, RF_ACTIVE)))
151 return (ENXIO);
152 mvs_dmainit(dev);
153 mvs_slotsalloc(dev);
154 mvs_ch_init(dev);
155 mtx_lock(&ch->mtx);
156 rid = ATA_IRQ_RID;
157 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
158 &rid, RF_SHAREABLE | RF_ACTIVE))) {
159 device_printf(dev, "Unable to map interrupt\n");
160 error = ENXIO;
161 goto err0;
162 }
163 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
164 mvs_ch_intr_locked, dev, &ch->ih))) {
165 device_printf(dev, "Unable to setup interrupt\n");
166 error = ENXIO;
167 goto err1;
168 }
169 /* Create the device queue for our SIM. */
170 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1);
171 if (devq == NULL) {
172 device_printf(dev, "Unable to allocate simq\n");
173 error = ENOMEM;
174 goto err1;
175 }
176 /* Construct SIM entry */
177 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch,
178 device_get_unit(dev), &ch->mtx,
179 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1,
180 devq);
181 if (ch->sim == NULL) {
182 cam_simq_free(devq);
183 device_printf(dev, "unable to allocate sim\n");
184 error = ENOMEM;
185 goto err1;
186 }
187 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
188 device_printf(dev, "unable to register xpt bus\n");
189 error = ENXIO;
190 goto err2;
191 }
192 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
193 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
194 device_printf(dev, "unable to create path\n");
195 error = ENXIO;
196 goto err3;
197 }
198 if (ch->pm_level > 3) {
199 callout_reset(&ch->pm_timer,
200 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
201 mvs_ch_pm, dev);
202 }
203 mtx_unlock(&ch->mtx);
204 return (0);
205
206 err3:
207 xpt_bus_deregister(cam_sim_path(ch->sim));
208 err2:
209 cam_sim_free(ch->sim, /*free_devq*/TRUE);
210 err1:
211 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
212 err0:
213 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
214 mtx_unlock(&ch->mtx);
215 mtx_destroy(&ch->mtx);
216 return (error);
217 }
218
219 static int
mvs_ch_detach(device_t dev)220 mvs_ch_detach(device_t dev)
221 {
222 struct mvs_channel *ch = device_get_softc(dev);
223
224 mtx_lock(&ch->mtx);
225 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
226 /* Forget about reset. */
227 if (ch->resetting) {
228 ch->resetting = 0;
229 xpt_release_simq(ch->sim, TRUE);
230 }
231 xpt_free_path(ch->path);
232 xpt_bus_deregister(cam_sim_path(ch->sim));
233 cam_sim_free(ch->sim, /*free_devq*/TRUE);
234 mtx_unlock(&ch->mtx);
235
236 if (ch->pm_level > 3)
237 callout_drain(&ch->pm_timer);
238 callout_drain(&ch->reset_timer);
239 bus_teardown_intr(dev, ch->r_irq, ch->ih);
240 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
241
242 mvs_ch_deinit(dev);
243 mvs_slotsfree(dev);
244 mvs_dmafini(dev);
245
246 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
247 mtx_destroy(&ch->mtx);
248 return (0);
249 }
250
251 static int
mvs_ch_init(device_t dev)252 mvs_ch_init(device_t dev)
253 {
254 struct mvs_channel *ch = device_get_softc(dev);
255 uint32_t reg;
256
257 /* Disable port interrupts */
258 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
259 /* Stop EDMA */
260 ch->curr_mode = MVS_EDMA_UNKNOWN;
261 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
262 /* Clear and configure FIS interrupts. */
263 ATA_OUTL(ch->r_mem, SATA_FISIC, 0);
264 reg = ATA_INL(ch->r_mem, SATA_FISC);
265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
266 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
267 reg = ATA_INL(ch->r_mem, SATA_FISIM);
268 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
269 ATA_OUTL(ch->r_mem, SATA_FISC, reg);
270 /* Clear SATA error register. */
271 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
272 /* Clear any outstanding error interrupts. */
273 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
274 /* Unmask all error interrupts */
275 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
276 return (0);
277 }
278
279 static int
mvs_ch_deinit(device_t dev)280 mvs_ch_deinit(device_t dev)
281 {
282 struct mvs_channel *ch = device_get_softc(dev);
283
284 /* Stop EDMA */
285 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
286 /* Disable port interrupts. */
287 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
288 return (0);
289 }
290
291 static int
mvs_ch_suspend(device_t dev)292 mvs_ch_suspend(device_t dev)
293 {
294 struct mvs_channel *ch = device_get_softc(dev);
295
296 mtx_lock(&ch->mtx);
297 xpt_freeze_simq(ch->sim, 1);
298 while (ch->oslots)
299 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100);
300 /* Forget about reset. */
301 if (ch->resetting) {
302 ch->resetting = 0;
303 callout_stop(&ch->reset_timer);
304 xpt_release_simq(ch->sim, TRUE);
305 }
306 mvs_ch_deinit(dev);
307 mtx_unlock(&ch->mtx);
308 return (0);
309 }
310
311 static int
mvs_ch_resume(device_t dev)312 mvs_ch_resume(device_t dev)
313 {
314 struct mvs_channel *ch = device_get_softc(dev);
315
316 mtx_lock(&ch->mtx);
317 mvs_ch_init(dev);
318 mvs_reset(dev);
319 xpt_release_simq(ch->sim, TRUE);
320 mtx_unlock(&ch->mtx);
321 return (0);
322 }
323
324 struct mvs_dc_cb_args {
325 bus_addr_t maddr;
326 int error;
327 };
328
329 static void
mvs_dmainit(device_t dev)330 mvs_dmainit(device_t dev)
331 {
332 struct mvs_channel *ch = device_get_softc(dev);
333 struct mvs_dc_cb_args dcba;
334
335 /* EDMA command request area. */
336 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
337 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
338 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE,
339 0, NULL, NULL, &ch->dma.workrq_tag))
340 goto error;
341 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0,
342 &ch->dma.workrq_map))
343 goto error;
344 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map,
345 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
346 dcba.error) {
347 bus_dmamem_free(ch->dma.workrq_tag,
348 ch->dma.workrq, ch->dma.workrq_map);
349 goto error;
350 }
351 ch->dma.workrq_bus = dcba.maddr;
352 /* EDMA command response area. */
353 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0,
354 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
355 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE,
356 0, NULL, NULL, &ch->dma.workrp_tag))
357 goto error;
358 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0,
359 &ch->dma.workrp_map))
360 goto error;
361 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map,
362 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
363 dcba.error) {
364 bus_dmamem_free(ch->dma.workrp_tag,
365 ch->dma.workrp, ch->dma.workrp_map);
366 goto error;
367 }
368 ch->dma.workrp_bus = dcba.maddr;
369 /* Data area. */
370 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX,
371 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
372 NULL, NULL,
373 MVS_SG_ENTRIES * PAGE_SIZE, MVS_SG_ENTRIES, MVS_EPRD_MAX,
374 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
375 goto error;
376 }
377 return;
378
379 error:
380 device_printf(dev, "WARNING - DMA initialization failed\n");
381 mvs_dmafini(dev);
382 }
383
384 static void
mvs_dmasetupc_cb(void * xsc,bus_dma_segment_t * segs,int nsegs,int error)385 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
386 {
387 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc;
388
389 if (!(dcba->error = error))
390 dcba->maddr = segs[0].ds_addr;
391 }
392
393 static void
mvs_dmafini(device_t dev)394 mvs_dmafini(device_t dev)
395 {
396 struct mvs_channel *ch = device_get_softc(dev);
397
398 if (ch->dma.data_tag) {
399 bus_dma_tag_destroy(ch->dma.data_tag);
400 ch->dma.data_tag = NULL;
401 }
402 if (ch->dma.workrp_bus) {
403 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map);
404 bus_dmamem_free(ch->dma.workrp_tag,
405 ch->dma.workrp, ch->dma.workrp_map);
406 ch->dma.workrp_bus = 0;
407 ch->dma.workrp = NULL;
408 }
409 if (ch->dma.workrp_tag) {
410 bus_dma_tag_destroy(ch->dma.workrp_tag);
411 ch->dma.workrp_tag = NULL;
412 }
413 if (ch->dma.workrq_bus) {
414 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map);
415 bus_dmamem_free(ch->dma.workrq_tag,
416 ch->dma.workrq, ch->dma.workrq_map);
417 ch->dma.workrq_bus = 0;
418 ch->dma.workrq = NULL;
419 }
420 if (ch->dma.workrq_tag) {
421 bus_dma_tag_destroy(ch->dma.workrq_tag);
422 ch->dma.workrq_tag = NULL;
423 }
424 }
425
426 static void
mvs_slotsalloc(device_t dev)427 mvs_slotsalloc(device_t dev)
428 {
429 struct mvs_channel *ch = device_get_softc(dev);
430 int i;
431
432 /* Alloc and setup command/dma slots */
433 bzero(ch->slot, sizeof(ch->slot));
434 for (i = 0; i < MVS_MAX_SLOTS; i++) {
435 struct mvs_slot *slot = &ch->slot[i];
436
437 slot->dev = dev;
438 slot->slot = i;
439 slot->state = MVS_SLOT_EMPTY;
440 slot->eprd_offset = MVS_EPRD_OFFSET + MVS_EPRD_SIZE * i;
441 slot->ccb = NULL;
442 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
443
444 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
445 device_printf(ch->dev, "FAILURE - create data_map\n");
446 }
447 }
448
449 static void
mvs_slotsfree(device_t dev)450 mvs_slotsfree(device_t dev)
451 {
452 struct mvs_channel *ch = device_get_softc(dev);
453 int i;
454
455 /* Free all dma slots */
456 for (i = 0; i < MVS_MAX_SLOTS; i++) {
457 struct mvs_slot *slot = &ch->slot[i];
458
459 callout_drain(&slot->timeout);
460 if (slot->dma.data_map) {
461 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
462 slot->dma.data_map = NULL;
463 }
464 }
465 }
466
467 static void
mvs_setup_edma_queues(device_t dev)468 mvs_setup_edma_queues(device_t dev)
469 {
470 struct mvs_channel *ch = device_get_softc(dev);
471 uint64_t work;
472
473 /* Requests queue. */
474 work = ch->dma.workrq_bus;
475 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32);
476 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff);
477 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff);
478 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
479 BUS_DMASYNC_PREWRITE);
480 /* Responses queue. */
481 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE);
482 work = ch->dma.workrp_bus;
483 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32);
484 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff);
485 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff);
486 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
487 BUS_DMASYNC_PREREAD);
488 ch->out_idx = 0;
489 ch->in_idx = 0;
490 }
491
492 static void
mvs_set_edma_mode(device_t dev,enum mvs_edma_mode mode)493 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode)
494 {
495 struct mvs_channel *ch = device_get_softc(dev);
496 int timeout;
497 uint32_t ecfg, fcfg, hc, ltm, unkn;
498
499 if (mode == ch->curr_mode)
500 return;
501 /* If we are running, we should stop first. */
502 if (ch->curr_mode != MVS_EDMA_OFF) {
503 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA);
504 timeout = 0;
505 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
506 DELAY(1000);
507 if (timeout++ > 1000) {
508 device_printf(dev, "stopping EDMA engine failed\n");
509 break;
510 }
511 }
512 }
513 ch->curr_mode = mode;
514 ch->fbs_enabled = 0;
515 ch->fake_busy = 0;
516 /* Report mode to controller. Needed for correct CCC operation. */
517 MVS_EDMA(device_get_parent(dev), dev, mode);
518 /* Configure new mode. */
519 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN;
520 if (ch->pm_present) {
521 ecfg |= EDMA_CFG_EMASKRXPM;
522 if (ch->quirks & MVS_Q_GENIIE) {
523 ecfg |= EDMA_CFG_EEDMAFBS;
524 ch->fbs_enabled = 1;
525 }
526 }
527 if (ch->quirks & MVS_Q_GENI)
528 ecfg |= EDMA_CFG_ERDBSZ;
529 else if (ch->quirks & MVS_Q_GENII)
530 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN;
531 if (ch->quirks & MVS_Q_CT)
532 ecfg |= EDMA_CFG_ECUTTHROUGHEN;
533 if (mode != MVS_EDMA_OFF)
534 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN;
535 if (mode == MVS_EDMA_QUEUED)
536 ecfg |= EDMA_CFG_EQUE;
537 else if (mode == MVS_EDMA_NCQ)
538 ecfg |= EDMA_CFG_ESATANATVCMDQUE;
539 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg);
540 mvs_setup_edma_queues(dev);
541 if (ch->quirks & MVS_Q_GENIIE) {
542 /* Configure FBS-related registers */
543 fcfg = ATA_INL(ch->r_mem, SATA_FISC);
544 ltm = ATA_INL(ch->r_mem, SATA_LTM);
545 hc = ATA_INL(ch->r_mem, EDMA_HC);
546 if (ch->fbs_enabled) {
547 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP;
548 if (mode == MVS_EDMA_NCQ) {
549 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
550 hc &= ~EDMA_IE_EDEVERR;
551 } else {
552 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0;
553 hc |= EDMA_IE_EDEVERR;
554 }
555 ltm |= (1 << 8);
556 } else {
557 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP;
558 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
559 hc |= EDMA_IE_EDEVERR;
560 ltm &= ~(1 << 8);
561 }
562 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg);
563 ATA_OUTL(ch->r_mem, SATA_LTM, ltm);
564 ATA_OUTL(ch->r_mem, EDMA_HC, hc);
565 /* This is some magic, required to handle several DRQs
566 * with basic DMA. */
567 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
568 if (mode == MVS_EDMA_OFF)
569 unkn |= 1;
570 else
571 unkn &= ~1;
572 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn);
573 }
574 /* Run EDMA. */
575 if (mode != MVS_EDMA_OFF)
576 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA);
577 }
578
579 devclass_t mvs_devclass;
580 devclass_t mvsch_devclass;
581 static device_method_t mvsch_methods[] = {
582 DEVMETHOD(device_probe, mvs_ch_probe),
583 DEVMETHOD(device_attach, mvs_ch_attach),
584 DEVMETHOD(device_detach, mvs_ch_detach),
585 DEVMETHOD(device_suspend, mvs_ch_suspend),
586 DEVMETHOD(device_resume, mvs_ch_resume),
587 { 0, 0 }
588 };
589 static driver_t mvsch_driver = {
590 "mvsch",
591 mvsch_methods,
592 sizeof(struct mvs_channel)
593 };
594 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0);
595 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0);
596
597 static void
mvs_phy_check_events(device_t dev,u_int32_t serr)598 mvs_phy_check_events(device_t dev, u_int32_t serr)
599 {
600 struct mvs_channel *ch = device_get_softc(dev);
601
602 if (ch->pm_level == 0) {
603 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
604 union ccb *ccb;
605
606 if (bootverbose) {
607 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
608 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
609 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) {
610 device_printf(dev, "CONNECT requested\n");
611 } else
612 device_printf(dev, "DISCONNECT requested\n");
613 }
614 mvs_reset(dev);
615 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
616 return;
617 if (xpt_create_path(&ccb->ccb_h.path, NULL,
618 cam_sim_path(ch->sim),
619 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
620 xpt_free_ccb(ccb);
621 return;
622 }
623 xpt_rescan(ccb);
624 }
625 }
626
627 static void
mvs_notify_events(device_t dev)628 mvs_notify_events(device_t dev)
629 {
630 struct mvs_channel *ch = device_get_softc(dev);
631 struct cam_path *dpath;
632 uint32_t fis;
633 int d;
634
635 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */
636 fis = ATA_INL(ch->r_mem, SATA_FISDW0);
637 if ((fis & 0x80ff) == 0x80a1)
638 d = (fis & 0x0f00) >> 8;
639 else
640 d = ch->pm_present ? 15 : 0;
641 if (bootverbose)
642 device_printf(dev, "SNTF %d\n", d);
643 if (xpt_create_path(&dpath, NULL,
644 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) {
645 xpt_async(AC_SCSI_AEN, dpath, NULL);
646 xpt_free_path(dpath);
647 }
648 }
649
650 static void
mvs_ch_intr_locked(void * data)651 mvs_ch_intr_locked(void *data)
652 {
653 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
654 device_t dev = (device_t)arg->arg;
655 struct mvs_channel *ch = device_get_softc(dev);
656
657 mtx_lock(&ch->mtx);
658 mvs_ch_intr(data);
659 mtx_unlock(&ch->mtx);
660 }
661
662 static void
mvs_ch_pm(void * arg)663 mvs_ch_pm(void *arg)
664 {
665 device_t dev = (device_t)arg;
666 struct mvs_channel *ch = device_get_softc(dev);
667 uint32_t work;
668
669 if (ch->numrslots != 0)
670 return;
671 /* If we are idle - request power state transition. */
672 work = ATA_INL(ch->r_mem, SATA_SC);
673 work &= ~SATA_SC_SPM_MASK;
674 if (ch->pm_level == 4)
675 work |= SATA_SC_SPM_PARTIAL;
676 else
677 work |= SATA_SC_SPM_SLUMBER;
678 ATA_OUTL(ch->r_mem, SATA_SC, work);
679 }
680
681 static void
mvs_ch_pm_wake(device_t dev)682 mvs_ch_pm_wake(device_t dev)
683 {
684 struct mvs_channel *ch = device_get_softc(dev);
685 uint32_t work;
686 int timeout = 0;
687
688 work = ATA_INL(ch->r_mem, SATA_SS);
689 if (work & SATA_SS_IPM_ACTIVE)
690 return;
691 /* If we are not in active state - request power state transition. */
692 work = ATA_INL(ch->r_mem, SATA_SC);
693 work &= ~SATA_SC_SPM_MASK;
694 work |= SATA_SC_SPM_ACTIVE;
695 ATA_OUTL(ch->r_mem, SATA_SC, work);
696 /* Wait for transition to happen. */
697 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
698 timeout++ < 100) {
699 DELAY(100);
700 }
701 }
702
703 static void
mvs_ch_intr(void * data)704 mvs_ch_intr(void *data)
705 {
706 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
707 device_t dev = (device_t)arg->arg;
708 struct mvs_channel *ch = device_get_softc(dev);
709 uint32_t iec, serr = 0, fisic = 0;
710 enum mvs_err_type et;
711 int i, ccs, port = -1, selfdis = 0;
712 int edma = (ch->numtslots != 0 || ch->numdslots != 0);
713
714 /* New item in response queue. */
715 if ((arg->cause & 2) && edma)
716 mvs_crbq_intr(dev);
717 /* Some error or special event. */
718 if (arg->cause & 1) {
719 iec = ATA_INL(ch->r_mem, EDMA_IEC);
720 if (iec & EDMA_IE_SERRINT) {
721 serr = ATA_INL(ch->r_mem, SATA_SE);
722 ATA_OUTL(ch->r_mem, SATA_SE, serr);
723 }
724 /* EDMA self-disabled due to error. */
725 if (iec & EDMA_IE_ESELFDIS)
726 selfdis = 1;
727 /* Transport interrupt. */
728 if (iec & EDMA_IE_ETRANSINT) {
729 /* For Gen-I this bit means self-disable. */
730 if (ch->quirks & MVS_Q_GENI)
731 selfdis = 1;
732 /* For Gen-II this bit means SDB-N. */
733 else if (ch->quirks & MVS_Q_GENII)
734 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1;
735 else /* For Gen-IIe - read FIS interrupt cause. */
736 fisic = ATA_INL(ch->r_mem, SATA_FISIC);
737 }
738 if (selfdis)
739 ch->curr_mode = MVS_EDMA_UNKNOWN;
740 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec);
741 /* Interface errors or Device error. */
742 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) {
743 port = -1;
744 if (ch->numpslots != 0) {
745 ccs = 0;
746 } else {
747 if (ch->quirks & MVS_Q_GENIIE)
748 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
749 else
750 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
751 /* Check if error is one-PMP-port-specific, */
752 if (ch->fbs_enabled) {
753 /* Which ports were active. */
754 for (i = 0; i < 16; i++) {
755 if (ch->numrslotspd[i] == 0)
756 continue;
757 if (port == -1)
758 port = i;
759 else if (port != i) {
760 port = -2;
761 break;
762 }
763 }
764 /* If several ports were active and EDMA still enabled -
765 * other ports are probably unaffected and may continue.
766 */
767 if (port == -2 && !selfdis) {
768 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
769 port = ffs(p) - 1;
770 if (port != (fls(p) - 1))
771 port = -2;
772 }
773 }
774 }
775 mvs_requeue_frozen(dev);
776 for (i = 0; i < MVS_MAX_SLOTS; i++) {
777 /* XXX: reqests in loading state. */
778 if (((ch->rslots >> i) & 1) == 0)
779 continue;
780 if (port >= 0 &&
781 ch->slot[i].ccb->ccb_h.target_id != port)
782 continue;
783 if (iec & EDMA_IE_EDEVERR) { /* Device error. */
784 if (port != -2) {
785 if (ch->numtslots == 0) {
786 /* Untagged operation. */
787 if (i == ccs)
788 et = MVS_ERR_TFE;
789 else
790 et = MVS_ERR_INNOCENT;
791 } else {
792 /* Tagged operation. */
793 et = MVS_ERR_NCQ;
794 }
795 } else {
796 et = MVS_ERR_TFE;
797 ch->fatalerr = 1;
798 }
799 } else if (iec & 0xfc1e9000) {
800 if (ch->numtslots == 0 &&
801 i != ccs && port != -2)
802 et = MVS_ERR_INNOCENT;
803 else
804 et = MVS_ERR_SATA;
805 } else
806 et = MVS_ERR_INVALID;
807 mvs_end_transaction(&ch->slot[i], et);
808 }
809 }
810 /* Process SDB-N. */
811 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1)
812 mvs_notify_events(dev);
813 if (fisic)
814 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic);
815 /* Process hot-plug. */
816 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) ||
817 (serr & SATA_SE_PHY_CHANGED))
818 mvs_phy_check_events(dev, serr);
819 }
820 /* Legacy mode device interrupt. */
821 if ((arg->cause & 2) && !edma)
822 mvs_legacy_intr(dev, arg->cause & 4);
823 }
824
825 static uint8_t
mvs_getstatus(device_t dev,int clear)826 mvs_getstatus(device_t dev, int clear)
827 {
828 struct mvs_channel *ch = device_get_softc(dev);
829 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT);
830
831 if (ch->fake_busy) {
832 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR))
833 ch->fake_busy = 0;
834 else
835 status |= ATA_S_BUSY;
836 }
837 return (status);
838 }
839
840 static void
mvs_legacy_intr(device_t dev,int poll)841 mvs_legacy_intr(device_t dev, int poll)
842 {
843 struct mvs_channel *ch = device_get_softc(dev);
844 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */
845 union ccb *ccb = slot->ccb;
846 enum mvs_err_type et = MVS_ERR_NONE;
847 int port;
848 u_int length, resid, size;
849 uint8_t buf[2];
850 uint8_t status, ireason;
851
852 /* Clear interrupt and get status. */
853 status = mvs_getstatus(dev, 1);
854 if (slot->state < MVS_SLOT_RUNNING)
855 return;
856 port = ccb->ccb_h.target_id & 0x0f;
857 /* Wait a bit for late !BUSY status update. */
858 if (status & ATA_S_BUSY) {
859 if (poll)
860 return;
861 DELAY(100);
862 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) {
863 DELAY(1000);
864 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY)
865 return;
866 }
867 }
868 /* If we got an error, we are done. */
869 if (status & ATA_S_ERROR) {
870 et = MVS_ERR_TFE;
871 goto end_finished;
872 }
873 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */
874 ccb->ataio.res.status = status;
875 /* Are we moving data? */
876 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
877 /* If data read command - get them. */
878 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
879 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
880 device_printf(dev, "timeout waiting for read DRQ\n");
881 et = MVS_ERR_TIMEOUT;
882 xpt_freeze_simq(ch->sim, 1);
883 ch->toslots |= (1 << slot->slot);
884 goto end_finished;
885 }
886 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
887 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
888 ch->transfersize / 2);
889 }
890 /* Update how far we've gotten. */
891 ch->donecount += ch->transfersize;
892 /* Do we need more? */
893 if (ccb->ataio.dxfer_len > ch->donecount) {
894 /* Set this transfer size according to HW capabilities */
895 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount,
896 ch->transfersize);
897 /* If data write command - put them */
898 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
899 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
900 device_printf(dev,
901 "timeout waiting for write DRQ\n");
902 et = MVS_ERR_TIMEOUT;
903 xpt_freeze_simq(ch->sim, 1);
904 ch->toslots |= (1 << slot->slot);
905 goto end_finished;
906 }
907 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
908 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
909 ch->transfersize / 2);
910 return;
911 }
912 /* If data read command, return & wait for interrupt */
913 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
914 return;
915 }
916 }
917 } else if (ch->basic_dma) { /* ATAPI DMA */
918 if (status & ATA_S_DWF)
919 et = MVS_ERR_TFE;
920 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
921 et = MVS_ERR_TFE;
922 /* Stop basic DMA. */
923 ATA_OUTL(ch->r_mem, DMA_C, 0);
924 goto end_finished;
925 } else { /* ATAPI PIO */
926 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) |
927 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8);
928 size = min(ch->transfersize, length);
929 ireason = ATA_INB(ch->r_mem,ATA_IREASON);
930 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) |
931 (status & ATA_S_DRQ)) {
932 case ATAPI_P_CMDOUT:
933 device_printf(dev, "ATAPI CMDOUT\n");
934 /* Return wait for interrupt */
935 return;
936
937 case ATAPI_P_WRITE:
938 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
939 device_printf(dev, "trying to write on read buffer\n");
940 et = MVS_ERR_TFE;
941 goto end_finished;
942 break;
943 }
944 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
945 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
946 (size + 1) / 2);
947 for (resid = ch->transfersize + (size & 1);
948 resid < length; resid += sizeof(int16_t))
949 ATA_OUTW(ch->r_mem, ATA_DATA, 0);
950 ch->donecount += length;
951 /* Set next transfer size according to HW capabilities */
952 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
953 ch->curr[ccb->ccb_h.target_id].bytecount);
954 /* Return wait for interrupt */
955 return;
956
957 case ATAPI_P_READ:
958 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
959 device_printf(dev, "trying to read on write buffer\n");
960 et = MVS_ERR_TFE;
961 goto end_finished;
962 }
963 if (size >= 2) {
964 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
965 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
966 size / 2);
967 }
968 if (size & 1) {
969 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1);
970 ((uint8_t *)ccb->csio.data_ptr + ch->donecount +
971 (size & ~1))[0] = buf[0];
972 }
973 for (resid = ch->transfersize + (size & 1);
974 resid < length; resid += sizeof(int16_t))
975 ATA_INW(ch->r_mem, ATA_DATA);
976 ch->donecount += length;
977 /* Set next transfer size according to HW capabilities */
978 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
979 ch->curr[ccb->ccb_h.target_id].bytecount);
980 /* Return wait for interrupt */
981 return;
982
983 case ATAPI_P_DONEDRQ:
984 device_printf(dev,
985 "WARNING - DONEDRQ non conformant device\n");
986 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
987 ATA_INSW_STRM(ch->r_mem, ATA_DATA,
988 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
989 length / 2);
990 ch->donecount += length;
991 }
992 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
993 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
994 (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
995 length / 2);
996 ch->donecount += length;
997 }
998 else
999 et = MVS_ERR_TFE;
1000 /* FALLTHROUGH */
1001
1002 case ATAPI_P_ABORT:
1003 case ATAPI_P_DONE:
1004 if (status & (ATA_S_ERROR | ATA_S_DWF))
1005 et = MVS_ERR_TFE;
1006 goto end_finished;
1007
1008 default:
1009 device_printf(dev, "unknown transfer phase"
1010 " (status %02x, ireason %02x)\n",
1011 status, ireason);
1012 et = MVS_ERR_TFE;
1013 }
1014 }
1015
1016 end_finished:
1017 mvs_end_transaction(slot, et);
1018 }
1019
1020 static void
mvs_crbq_intr(device_t dev)1021 mvs_crbq_intr(device_t dev)
1022 {
1023 struct mvs_channel *ch = device_get_softc(dev);
1024 struct mvs_crpb *crpb;
1025 union ccb *ccb;
1026 int in_idx, fin_idx, cin_idx, slot;
1027 uint32_t val;
1028 uint16_t flags;
1029
1030 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1031 if (val == 0)
1032 val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1033 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >>
1034 EDMA_RESQP_ERPQP_SHIFT;
1035 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1036 BUS_DMASYNC_POSTREAD);
1037 fin_idx = cin_idx = ch->in_idx;
1038 ch->in_idx = in_idx;
1039 while (in_idx != cin_idx) {
1040 crpb = (struct mvs_crpb *)
1041 (ch->dma.workrp + MVS_CRPB_OFFSET +
1042 (MVS_CRPB_SIZE * cin_idx));
1043 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK;
1044 flags = le16toh(crpb->rspflg);
1045 /*
1046 * Handle only successful completions here.
1047 * Errors will be handled by main intr handler.
1048 */
1049 #if defined(__i386__) || defined(__amd64__)
1050 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) {
1051 device_printf(dev, "Unfilled CRPB "
1052 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1053 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots);
1054 } else
1055 #endif
1056 if (ch->numtslots != 0 ||
1057 (flags & EDMA_IE_EDEVERR) == 0) {
1058 #if defined(__i386__) || defined(__amd64__)
1059 crpb->id = 0xffff;
1060 crpb->rspflg = 0xffff;
1061 #endif
1062 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) {
1063 ccb = ch->slot[slot].ccb;
1064 ccb->ataio.res.status =
1065 (flags & MVS_CRPB_ATASTS_MASK) >>
1066 MVS_CRPB_ATASTS_SHIFT;
1067 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE);
1068 } else {
1069 device_printf(dev, "Unused tag in CRPB "
1070 "%d (%d->%d) tag %d flags %04x rs %08x\n",
1071 cin_idx, fin_idx, in_idx, slot, flags,
1072 ch->rslots);
1073 }
1074 } else {
1075 device_printf(dev,
1076 "CRPB with error %d tag %d flags %04x\n",
1077 cin_idx, slot, flags);
1078 }
1079 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1);
1080 }
1081 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1082 BUS_DMASYNC_PREREAD);
1083 if (cin_idx == ch->in_idx) {
1084 ATA_OUTL(ch->r_mem, EDMA_RESQOP,
1085 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT));
1086 }
1087 }
1088
1089 /* Must be called with channel locked. */
1090 static int
mvs_check_collision(device_t dev,union ccb * ccb)1091 mvs_check_collision(device_t dev, union ccb *ccb)
1092 {
1093 struct mvs_channel *ch = device_get_softc(dev);
1094
1095 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1096 /* NCQ DMA */
1097 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1098 /* Can't mix NCQ and non-NCQ DMA commands. */
1099 if (ch->numdslots != 0)
1100 return (1);
1101 /* Can't mix NCQ and PIO commands. */
1102 if (ch->numpslots != 0)
1103 return (1);
1104 /* If we have no FBS */
1105 if (!ch->fbs_enabled) {
1106 /* Tagged command while tagged to other target is active. */
1107 if (ch->numtslots != 0 &&
1108 ch->taggedtarget != ccb->ccb_h.target_id)
1109 return (1);
1110 }
1111 /* Non-NCQ DMA */
1112 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1113 /* Can't mix non-NCQ DMA and NCQ commands. */
1114 if (ch->numtslots != 0)
1115 return (1);
1116 /* Can't mix non-NCQ DMA and PIO commands. */
1117 if (ch->numpslots != 0)
1118 return (1);
1119 /* PIO */
1120 } else {
1121 /* Can't mix PIO with anything. */
1122 if (ch->numrslots != 0)
1123 return (1);
1124 }
1125 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1126 /* Atomic command while anything active. */
1127 if (ch->numrslots != 0)
1128 return (1);
1129 }
1130 } else { /* ATAPI */
1131 /* ATAPI goes without EDMA, so can't mix it with anything. */
1132 if (ch->numrslots != 0)
1133 return (1);
1134 }
1135 /* We have some atomic command running. */
1136 if (ch->aslots != 0)
1137 return (1);
1138 return (0);
1139 }
1140
1141 static void
mvs_tfd_read(device_t dev,union ccb * ccb)1142 mvs_tfd_read(device_t dev, union ccb *ccb)
1143 {
1144 struct mvs_channel *ch = device_get_softc(dev);
1145 struct ata_res *res = &ccb->ataio.res;
1146
1147 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT);
1148 res->error = ATA_INB(ch->r_mem, ATA_ERROR);
1149 res->device = ATA_INB(ch->r_mem, ATA_DRIVE);
1150 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB);
1151 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT);
1152 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR);
1153 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1154 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1155 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
1156 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT);
1157 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR);
1158 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1159 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1160 }
1161
1162 static void
mvs_tfd_write(device_t dev,union ccb * ccb)1163 mvs_tfd_write(device_t dev, union ccb *ccb)
1164 {
1165 struct mvs_channel *ch = device_get_softc(dev);
1166 struct ata_cmd *cmd = &ccb->ataio.cmd;
1167
1168 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device);
1169 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control);
1170 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp);
1171 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features);
1172 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp);
1173 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count);
1174 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp);
1175 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low);
1176 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp);
1177 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid);
1178 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp);
1179 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high);
1180 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command);
1181 }
1182
1183 /* Must be called with channel locked. */
1184 static void
mvs_begin_transaction(device_t dev,union ccb * ccb)1185 mvs_begin_transaction(device_t dev, union ccb *ccb)
1186 {
1187 struct mvs_channel *ch = device_get_softc(dev);
1188 struct mvs_slot *slot;
1189 int slotn, tag;
1190
1191 if (ch->pm_level > 0)
1192 mvs_ch_pm_wake(dev);
1193 /* Softreset is a special case. */
1194 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1195 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1196 mvs_softreset(dev, ccb);
1197 return;
1198 }
1199 /* Choose empty slot. */
1200 slotn = ffs(~ch->oslots) - 1;
1201 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1202 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1203 if (ch->quirks & MVS_Q_GENIIE)
1204 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1;
1205 else
1206 tag = slotn;
1207 } else
1208 tag = 0;
1209 /* Occupy chosen slot. */
1210 slot = &ch->slot[slotn];
1211 slot->ccb = ccb;
1212 slot->tag = tag;
1213 /* Stop PM timer. */
1214 if (ch->numrslots == 0 && ch->pm_level > 3)
1215 callout_stop(&ch->pm_timer);
1216 /* Update channel stats. */
1217 ch->oslots |= (1 << slot->slot);
1218 ch->numrslots++;
1219 ch->numrslotspd[ccb->ccb_h.target_id]++;
1220 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1221 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1222 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag);
1223 ch->numtslots++;
1224 ch->numtslotspd[ccb->ccb_h.target_id]++;
1225 ch->taggedtarget = ccb->ccb_h.target_id;
1226 mvs_set_edma_mode(dev, MVS_EDMA_NCQ);
1227 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1228 ch->numdslots++;
1229 mvs_set_edma_mode(dev, MVS_EDMA_ON);
1230 } else {
1231 ch->numpslots++;
1232 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1233 }
1234 if (ccb->ataio.cmd.flags &
1235 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1236 ch->aslots |= (1 << slot->slot);
1237 }
1238 } else {
1239 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1240 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
1241 ch->numpslots++;
1242 /* Use ATAPI DMA only for commands without under-/overruns. */
1243 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1244 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA &&
1245 (ch->quirks & MVS_Q_SOC) == 0 &&
1246 (cdb[0] == 0x08 ||
1247 cdb[0] == 0x0a ||
1248 cdb[0] == 0x28 ||
1249 cdb[0] == 0x2a ||
1250 cdb[0] == 0x88 ||
1251 cdb[0] == 0x8a ||
1252 cdb[0] == 0xa8 ||
1253 cdb[0] == 0xaa ||
1254 cdb[0] == 0xbe)) {
1255 ch->basic_dma = 1;
1256 }
1257 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1258 }
1259 if (ch->numpslots == 0 || ch->basic_dma) {
1260 slot->state = MVS_SLOT_LOADING;
1261 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map,
1262 ccb, mvs_dmasetprd, slot, 0);
1263 } else
1264 mvs_legacy_execute_transaction(slot);
1265 }
1266
1267 /* Locked by busdma engine. */
1268 static void
mvs_dmasetprd(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1269 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1270 {
1271 struct mvs_slot *slot = arg;
1272 struct mvs_channel *ch = device_get_softc(slot->dev);
1273 struct mvs_eprd *eprd;
1274 int i;
1275
1276 if (error) {
1277 device_printf(slot->dev, "DMA load error\n");
1278 mvs_end_transaction(slot, MVS_ERR_INVALID);
1279 return;
1280 }
1281 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n"));
1282 /* If there is only one segment - no need to use S/G table on Gen-IIe. */
1283 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) {
1284 slot->dma.addr = segs[0].ds_addr;
1285 slot->dma.len = segs[0].ds_len;
1286 } else {
1287 slot->dma.addr = 0;
1288 /* Get a piece of the workspace for this EPRD */
1289 eprd = (struct mvs_eprd *)(ch->dma.workrq + slot->eprd_offset);
1290 /* Fill S/G table */
1291 for (i = 0; i < nsegs; i++) {
1292 eprd[i].prdbal = htole32(segs[i].ds_addr);
1293 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK);
1294 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16);
1295 }
1296 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF);
1297 }
1298 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1299 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1300 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1301 if (ch->basic_dma)
1302 mvs_legacy_execute_transaction(slot);
1303 else
1304 mvs_execute_transaction(slot);
1305 }
1306
1307 static void
mvs_legacy_execute_transaction(struct mvs_slot * slot)1308 mvs_legacy_execute_transaction(struct mvs_slot *slot)
1309 {
1310 device_t dev = slot->dev;
1311 struct mvs_channel *ch = device_get_softc(dev);
1312 bus_addr_t eprd;
1313 union ccb *ccb = slot->ccb;
1314 int port = ccb->ccb_h.target_id & 0x0f;
1315 int timeout;
1316
1317 slot->state = MVS_SLOT_RUNNING;
1318 ch->rslots |= (1 << slot->slot);
1319 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
1320 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1321 mvs_tfd_write(dev, ccb);
1322 /* Device reset doesn't interrupt. */
1323 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) {
1324 int timeout = 1000000;
1325 do {
1326 DELAY(10);
1327 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS);
1328 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--);
1329 mvs_legacy_intr(dev, 1);
1330 return;
1331 }
1332 ch->donecount = 0;
1333 if (ccb->ataio.cmd.command == ATA_READ_MUL ||
1334 ccb->ataio.cmd.command == ATA_READ_MUL48 ||
1335 ccb->ataio.cmd.command == ATA_WRITE_MUL ||
1336 ccb->ataio.cmd.command == ATA_WRITE_MUL48) {
1337 ch->transfersize = min(ccb->ataio.dxfer_len,
1338 ch->curr[port].bytecount);
1339 } else
1340 ch->transfersize = min(ccb->ataio.dxfer_len, 512);
1341 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1342 ch->fake_busy = 1;
1343 /* If data write command - output the data */
1344 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1345 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
1346 device_printf(dev,
1347 "timeout waiting for write DRQ\n");
1348 xpt_freeze_simq(ch->sim, 1);
1349 ch->toslots |= (1 << slot->slot);
1350 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1351 return;
1352 }
1353 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1354 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
1355 ch->transfersize / 2);
1356 }
1357 } else {
1358 ch->donecount = 0;
1359 ch->transfersize = min(ccb->csio.dxfer_len,
1360 ch->curr[port].bytecount);
1361 /* Write ATA PACKET command. */
1362 if (ch->basic_dma) {
1363 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA);
1364 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0);
1365 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0);
1366 } else {
1367 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0);
1368 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize);
1369 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8);
1370 }
1371 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD);
1372 ch->fake_busy = 1;
1373 /* Wait for ready to write ATAPI command block */
1374 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) {
1375 device_printf(dev, "timeout waiting for ATAPI !BUSY\n");
1376 xpt_freeze_simq(ch->sim, 1);
1377 ch->toslots |= (1 << slot->slot);
1378 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1379 return;
1380 }
1381 timeout = 5000;
1382 while (timeout--) {
1383 int reason = ATA_INB(ch->r_mem, ATA_IREASON);
1384 int status = ATA_INB(ch->r_mem, ATA_STATUS);
1385
1386 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
1387 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
1388 break;
1389 DELAY(20);
1390 }
1391 if (timeout <= 0) {
1392 device_printf(dev,
1393 "timeout waiting for ATAPI command ready\n");
1394 xpt_freeze_simq(ch->sim, 1);
1395 ch->toslots |= (1 << slot->slot);
1396 mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1397 return;
1398 }
1399 /* Write ATAPI command. */
1400 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1401 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1402 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes),
1403 ch->curr[port].atapi / 2);
1404 DELAY(10);
1405 if (ch->basic_dma) {
1406 /* Start basic DMA. */
1407 eprd = ch->dma.workrq_bus + slot->eprd_offset;
1408 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd);
1409 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16);
1410 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START |
1411 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ?
1412 DMA_C_READ : 0));
1413 }
1414 }
1415 /* Start command execution timeout */
1416 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1417 mvs_timeout, slot, 0);
1418 }
1419
1420 /* Must be called with channel locked. */
1421 static void
mvs_execute_transaction(struct mvs_slot * slot)1422 mvs_execute_transaction(struct mvs_slot *slot)
1423 {
1424 device_t dev = slot->dev;
1425 struct mvs_channel *ch = device_get_softc(dev);
1426 bus_addr_t eprd;
1427 struct mvs_crqb *crqb;
1428 struct mvs_crqb_gen2e *crqb2e;
1429 union ccb *ccb = slot->ccb;
1430 int port = ccb->ccb_h.target_id & 0x0f;
1431 int i;
1432
1433 /* Get address of the prepared EPRD */
1434 eprd = ch->dma.workrq_bus + slot->eprd_offset;
1435 /* Prepare CRQB. Gen IIe uses different CRQB format. */
1436 if (ch->quirks & MVS_Q_GENIIE) {
1437 crqb2e = (struct mvs_crqb_gen2e *)
1438 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1439 crqb2e->ctrlflg = htole32(
1440 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) |
1441 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) |
1442 (port << MVS_CRQB2E_PMP_SHIFT) |
1443 (slot->slot << MVS_CRQB2E_HTAG_SHIFT));
1444 /* If there is only one segment - no need to use S/G table. */
1445 if (slot->dma.addr != 0) {
1446 eprd = slot->dma.addr;
1447 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD);
1448 crqb2e->drbc = slot->dma.len;
1449 }
1450 crqb2e->cprdbl = htole32(eprd);
1451 crqb2e->cprdbh = htole32((eprd >> 16) >> 16);
1452 crqb2e->cmd[0] = 0;
1453 crqb2e->cmd[1] = 0;
1454 crqb2e->cmd[2] = ccb->ataio.cmd.command;
1455 crqb2e->cmd[3] = ccb->ataio.cmd.features;
1456 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low;
1457 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid;
1458 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high;
1459 crqb2e->cmd[7] = ccb->ataio.cmd.device;
1460 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp;
1461 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp;
1462 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp;
1463 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp;
1464 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1465 crqb2e->cmd[12] = slot->tag << 3;
1466 crqb2e->cmd[13] = 0;
1467 } else {
1468 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count;
1469 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp;
1470 }
1471 crqb2e->cmd[14] = 0;
1472 crqb2e->cmd[15] = 0;
1473 } else {
1474 crqb = (struct mvs_crqb *)
1475 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1476 crqb->cprdbl = htole32(eprd);
1477 crqb->cprdbh = htole32((eprd >> 16) >> 16);
1478 crqb->ctrlflg = htole16(
1479 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) |
1480 (slot->slot << MVS_CRQB_TAG_SHIFT) |
1481 (port << MVS_CRQB_PMP_SHIFT));
1482 i = 0;
1483 /*
1484 * Controller can handle only 11 of 12 ATA registers,
1485 * so we have to choose which one to skip.
1486 */
1487 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1488 crqb->cmd[i++] = ccb->ataio.cmd.features_exp;
1489 crqb->cmd[i++] = 0x11;
1490 }
1491 crqb->cmd[i++] = ccb->ataio.cmd.features;
1492 crqb->cmd[i++] = 0x11;
1493 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1494 crqb->cmd[i++] = (slot->tag << 3) |
1495 (ccb->ataio.cmd.sector_count & 0x07);
1496 crqb->cmd[i++] = 0x12;
1497 } else {
1498 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp;
1499 crqb->cmd[i++] = 0x12;
1500 crqb->cmd[i++] = ccb->ataio.cmd.sector_count;
1501 crqb->cmd[i++] = 0x12;
1502 }
1503 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp;
1504 crqb->cmd[i++] = 0x13;
1505 crqb->cmd[i++] = ccb->ataio.cmd.lba_low;
1506 crqb->cmd[i++] = 0x13;
1507 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp;
1508 crqb->cmd[i++] = 0x14;
1509 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid;
1510 crqb->cmd[i++] = 0x14;
1511 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp;
1512 crqb->cmd[i++] = 0x15;
1513 crqb->cmd[i++] = ccb->ataio.cmd.lba_high;
1514 crqb->cmd[i++] = 0x15;
1515 crqb->cmd[i++] = ccb->ataio.cmd.device;
1516 crqb->cmd[i++] = 0x16;
1517 crqb->cmd[i++] = ccb->ataio.cmd.command;
1518 crqb->cmd[i++] = 0x97;
1519 }
1520 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1521 BUS_DMASYNC_PREWRITE);
1522 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1523 BUS_DMASYNC_PREREAD);
1524 slot->state = MVS_SLOT_RUNNING;
1525 ch->rslots |= (1 << slot->slot);
1526 /* Issue command to the controller. */
1527 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1);
1528 ATA_OUTL(ch->r_mem, EDMA_REQQIP,
1529 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1530 /* Start command execution timeout */
1531 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout, 0,
1532 mvs_timeout, slot, 0);
1533 return;
1534 }
1535
1536 /* Must be called with channel locked. */
1537 static void
mvs_process_timeout(device_t dev)1538 mvs_process_timeout(device_t dev)
1539 {
1540 struct mvs_channel *ch = device_get_softc(dev);
1541 int i;
1542
1543 mtx_assert(&ch->mtx, MA_OWNED);
1544 /* Handle the rest of commands. */
1545 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1546 /* Do we have a running request on slot? */
1547 if (ch->slot[i].state < MVS_SLOT_RUNNING)
1548 continue;
1549 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT);
1550 }
1551 }
1552
1553 /* Must be called with channel locked. */
1554 static void
mvs_rearm_timeout(device_t dev)1555 mvs_rearm_timeout(device_t dev)
1556 {
1557 struct mvs_channel *ch = device_get_softc(dev);
1558 int i;
1559
1560 mtx_assert(&ch->mtx, MA_OWNED);
1561 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1562 struct mvs_slot *slot = &ch->slot[i];
1563
1564 /* Do we have a running request on slot? */
1565 if (slot->state < MVS_SLOT_RUNNING)
1566 continue;
1567 if ((ch->toslots & (1 << i)) == 0)
1568 continue;
1569 callout_reset_sbt(&slot->timeout,
1570 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1571 mvs_timeout, slot, 0);
1572 }
1573 }
1574
1575 /* Locked by callout mechanism. */
1576 static void
mvs_timeout(void * arg)1577 mvs_timeout(void *arg)
1578 {
1579 struct mvs_slot *slot = arg;
1580 device_t dev = slot->dev;
1581 struct mvs_channel *ch = device_get_softc(dev);
1582
1583 /* Check for stale timeout. */
1584 if (slot->state < MVS_SLOT_RUNNING)
1585 return;
1586 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1587 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x "
1588 "dma_c %08x dma_s %08x rs %08x status %02x\n",
1589 ATA_INL(ch->r_mem, EDMA_IEC),
1590 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
1591 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
1592 ATA_INL(ch->r_mem, DMA_S), ch->rslots,
1593 ATA_INB(ch->r_mem, ATA_ALTSTAT));
1594 /* Handle frozen command. */
1595 mvs_requeue_frozen(dev);
1596 /* We wait for other commands timeout and pray. */
1597 if (ch->toslots == 0)
1598 xpt_freeze_simq(ch->sim, 1);
1599 ch->toslots |= (1 << slot->slot);
1600 if ((ch->rslots & ~ch->toslots) == 0)
1601 mvs_process_timeout(dev);
1602 else
1603 device_printf(dev, " ... waiting for slots %08x\n",
1604 ch->rslots & ~ch->toslots);
1605 }
1606
1607 /* Must be called with channel locked. */
1608 static void
mvs_end_transaction(struct mvs_slot * slot,enum mvs_err_type et)1609 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
1610 {
1611 device_t dev = slot->dev;
1612 struct mvs_channel *ch = device_get_softc(dev);
1613 union ccb *ccb = slot->ccb;
1614 int lastto;
1615
1616 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1617 BUS_DMASYNC_POSTWRITE);
1618 /* Read result registers to the result struct
1619 * May be incorrect if several commands finished same time,
1620 * so read only when sure or have to.
1621 */
1622 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1623 struct ata_res *res = &ccb->ataio.res;
1624
1625 if ((et == MVS_ERR_TFE) ||
1626 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1627 mvs_tfd_read(dev, ccb);
1628 } else
1629 bzero(res, sizeof(*res));
1630 } else {
1631 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1632 ch->basic_dma == 0)
1633 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount;
1634 }
1635 if (ch->numpslots == 0 || ch->basic_dma) {
1636 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1637 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1638 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1639 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1640 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1641 }
1642 }
1643 if (et != MVS_ERR_NONE)
1644 ch->eslots |= (1 << slot->slot);
1645 /* In case of error, freeze device for proper recovery. */
1646 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) &&
1647 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1648 xpt_freeze_devq(ccb->ccb_h.path, 1);
1649 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1650 }
1651 /* Set proper result status. */
1652 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1653 switch (et) {
1654 case MVS_ERR_NONE:
1655 ccb->ccb_h.status |= CAM_REQ_CMP;
1656 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1657 ccb->csio.scsi_status = SCSI_STATUS_OK;
1658 break;
1659 case MVS_ERR_INVALID:
1660 ch->fatalerr = 1;
1661 ccb->ccb_h.status |= CAM_REQ_INVALID;
1662 break;
1663 case MVS_ERR_INNOCENT:
1664 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1665 break;
1666 case MVS_ERR_TFE:
1667 case MVS_ERR_NCQ:
1668 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1669 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1670 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1671 } else {
1672 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1673 }
1674 break;
1675 case MVS_ERR_SATA:
1676 ch->fatalerr = 1;
1677 if (!ch->recoverycmd) {
1678 xpt_freeze_simq(ch->sim, 1);
1679 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1680 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1681 }
1682 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1683 break;
1684 case MVS_ERR_TIMEOUT:
1685 if (!ch->recoverycmd) {
1686 xpt_freeze_simq(ch->sim, 1);
1687 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1688 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1689 }
1690 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1691 break;
1692 default:
1693 ch->fatalerr = 1;
1694 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1695 }
1696 /* Free slot. */
1697 ch->oslots &= ~(1 << slot->slot);
1698 ch->rslots &= ~(1 << slot->slot);
1699 ch->aslots &= ~(1 << slot->slot);
1700 slot->state = MVS_SLOT_EMPTY;
1701 slot->ccb = NULL;
1702 /* Update channel stats. */
1703 ch->numrslots--;
1704 ch->numrslotspd[ccb->ccb_h.target_id]--;
1705 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1706 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1707 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag);
1708 ch->numtslots--;
1709 ch->numtslotspd[ccb->ccb_h.target_id]--;
1710 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1711 ch->numdslots--;
1712 } else {
1713 ch->numpslots--;
1714 }
1715 } else {
1716 ch->numpslots--;
1717 ch->basic_dma = 0;
1718 }
1719 /* Cancel timeout state if request completed normally. */
1720 if (et != MVS_ERR_TIMEOUT) {
1721 lastto = (ch->toslots == (1 << slot->slot));
1722 ch->toslots &= ~(1 << slot->slot);
1723 if (lastto)
1724 xpt_release_simq(ch->sim, TRUE);
1725 }
1726 /* If it was our READ LOG command - process it. */
1727 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1728 mvs_process_read_log(dev, ccb);
1729 /* If it was our REQUEST SENSE command - process it. */
1730 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1731 mvs_process_request_sense(dev, ccb);
1732 /* If it was NCQ or ATAPI command error, put result on hold. */
1733 } else if (et == MVS_ERR_NCQ ||
1734 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1735 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1736 ch->hold[slot->slot] = ccb;
1737 ch->holdtag[slot->slot] = slot->tag;
1738 ch->numhslots++;
1739 } else
1740 xpt_done(ccb);
1741 /* If we have no other active commands, ... */
1742 if (ch->rslots == 0) {
1743 /* if there was fatal error - reset port. */
1744 if (ch->toslots != 0 || ch->fatalerr) {
1745 mvs_reset(dev);
1746 } else {
1747 /* if we have slots in error, we can reinit port. */
1748 if (ch->eslots != 0) {
1749 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1750 ch->eslots = 0;
1751 }
1752 /* if there commands on hold, we can do READ LOG. */
1753 if (!ch->recoverycmd && ch->numhslots)
1754 mvs_issue_recovery(dev);
1755 }
1756 /* If all the rest of commands are in timeout - give them chance. */
1757 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1758 et != MVS_ERR_TIMEOUT)
1759 mvs_rearm_timeout(dev);
1760 /* Unfreeze frozen command. */
1761 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
1762 union ccb *fccb = ch->frozen;
1763 ch->frozen = NULL;
1764 mvs_begin_transaction(dev, fccb);
1765 xpt_release_simq(ch->sim, TRUE);
1766 }
1767 /* Start PM timer. */
1768 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1769 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1770 callout_schedule(&ch->pm_timer,
1771 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1772 }
1773 }
1774
1775 static void
mvs_issue_recovery(device_t dev)1776 mvs_issue_recovery(device_t dev)
1777 {
1778 struct mvs_channel *ch = device_get_softc(dev);
1779 union ccb *ccb;
1780 struct ccb_ataio *ataio;
1781 struct ccb_scsiio *csio;
1782 int i;
1783
1784 /* Find some held command. */
1785 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1786 if (ch->hold[i])
1787 break;
1788 }
1789 ccb = xpt_alloc_ccb_nowait();
1790 if (ccb == NULL) {
1791 device_printf(dev, "Unable to allocate recovery command\n");
1792 completeall:
1793 /* We can't do anything -- complete held commands. */
1794 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1795 if (ch->hold[i] == NULL)
1796 continue;
1797 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1798 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1799 xpt_done(ch->hold[i]);
1800 ch->hold[i] = NULL;
1801 ch->numhslots--;
1802 }
1803 mvs_reset(dev);
1804 return;
1805 }
1806 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
1807 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1808 /* READ LOG */
1809 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1810 ccb->ccb_h.func_code = XPT_ATA_IO;
1811 ccb->ccb_h.flags = CAM_DIR_IN;
1812 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1813 ataio = &ccb->ataio;
1814 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT);
1815 if (ataio->data_ptr == NULL) {
1816 xpt_free_ccb(ccb);
1817 device_printf(dev,
1818 "Unable to allocate memory for READ LOG command\n");
1819 goto completeall;
1820 }
1821 ataio->dxfer_len = 512;
1822 bzero(&ataio->cmd, sizeof(ataio->cmd));
1823 ataio->cmd.flags = CAM_ATAIO_48BIT;
1824 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1825 ataio->cmd.sector_count = 1;
1826 ataio->cmd.sector_count_exp = 0;
1827 ataio->cmd.lba_low = 0x10;
1828 ataio->cmd.lba_mid = 0;
1829 ataio->cmd.lba_mid_exp = 0;
1830 } else {
1831 /* REQUEST SENSE */
1832 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1833 ccb->ccb_h.recovery_slot = i;
1834 ccb->ccb_h.func_code = XPT_SCSI_IO;
1835 ccb->ccb_h.flags = CAM_DIR_IN;
1836 ccb->ccb_h.status = 0;
1837 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1838 csio = &ccb->csio;
1839 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1840 csio->dxfer_len = ch->hold[i]->csio.sense_len;
1841 csio->cdb_len = 6;
1842 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1843 csio->cdb_io.cdb_bytes[0] = 0x03;
1844 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1845 }
1846 /* Freeze SIM while doing recovery. */
1847 ch->recoverycmd = 1;
1848 xpt_freeze_simq(ch->sim, 1);
1849 mvs_begin_transaction(dev, ccb);
1850 }
1851
1852 static void
mvs_process_read_log(device_t dev,union ccb * ccb)1853 mvs_process_read_log(device_t dev, union ccb *ccb)
1854 {
1855 struct mvs_channel *ch = device_get_softc(dev);
1856 uint8_t *data;
1857 struct ata_res *res;
1858 int i;
1859
1860 ch->recoverycmd = 0;
1861
1862 data = ccb->ataio.data_ptr;
1863 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1864 (data[0] & 0x80) == 0) {
1865 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1866 if (!ch->hold[i])
1867 continue;
1868 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1869 continue;
1870 if ((data[0] & 0x1F) == ch->holdtag[i]) {
1871 res = &ch->hold[i]->ataio.res;
1872 res->status = data[2];
1873 res->error = data[3];
1874 res->lba_low = data[4];
1875 res->lba_mid = data[5];
1876 res->lba_high = data[6];
1877 res->device = data[7];
1878 res->lba_low_exp = data[8];
1879 res->lba_mid_exp = data[9];
1880 res->lba_high_exp = data[10];
1881 res->sector_count = data[12];
1882 res->sector_count_exp = data[13];
1883 } else {
1884 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1885 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1886 }
1887 xpt_done(ch->hold[i]);
1888 ch->hold[i] = NULL;
1889 ch->numhslots--;
1890 }
1891 } else {
1892 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1893 device_printf(dev, "Error while READ LOG EXT\n");
1894 else if ((data[0] & 0x80) == 0) {
1895 device_printf(dev,
1896 "Non-queued command error in READ LOG EXT\n");
1897 }
1898 for (i = 0; i < MVS_MAX_SLOTS; i++) {
1899 if (!ch->hold[i])
1900 continue;
1901 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1902 continue;
1903 xpt_done(ch->hold[i]);
1904 ch->hold[i] = NULL;
1905 ch->numhslots--;
1906 }
1907 }
1908 free(ccb->ataio.data_ptr, M_MVS);
1909 xpt_free_ccb(ccb);
1910 xpt_release_simq(ch->sim, TRUE);
1911 }
1912
1913 static void
mvs_process_request_sense(device_t dev,union ccb * ccb)1914 mvs_process_request_sense(device_t dev, union ccb *ccb)
1915 {
1916 struct mvs_channel *ch = device_get_softc(dev);
1917 int i;
1918
1919 ch->recoverycmd = 0;
1920
1921 i = ccb->ccb_h.recovery_slot;
1922 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
1923 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
1924 } else {
1925 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1926 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
1927 }
1928 xpt_done(ch->hold[i]);
1929 ch->hold[i] = NULL;
1930 ch->numhslots--;
1931 xpt_free_ccb(ccb);
1932 xpt_release_simq(ch->sim, TRUE);
1933 }
1934
1935 static int
mvs_wait(device_t dev,u_int s,u_int c,int t)1936 mvs_wait(device_t dev, u_int s, u_int c, int t)
1937 {
1938 int timeout = 0;
1939 uint8_t st;
1940
1941 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) {
1942 if (timeout >= t) {
1943 if (t != 0)
1944 device_printf(dev, "Wait status %02x\n", st);
1945 return (-1);
1946 }
1947 DELAY(1000);
1948 timeout++;
1949 }
1950 return (timeout);
1951 }
1952
1953 static void
mvs_requeue_frozen(device_t dev)1954 mvs_requeue_frozen(device_t dev)
1955 {
1956 struct mvs_channel *ch = device_get_softc(dev);
1957 union ccb *fccb = ch->frozen;
1958
1959 if (fccb) {
1960 ch->frozen = NULL;
1961 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1962 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1963 xpt_freeze_devq(fccb->ccb_h.path, 1);
1964 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1965 }
1966 xpt_done(fccb);
1967 }
1968 }
1969
1970 static void
mvs_reset_to(void * arg)1971 mvs_reset_to(void *arg)
1972 {
1973 device_t dev = arg;
1974 struct mvs_channel *ch = device_get_softc(dev);
1975 int t;
1976
1977 if (ch->resetting == 0)
1978 return;
1979 ch->resetting--;
1980 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) {
1981 if (bootverbose) {
1982 device_printf(dev,
1983 "MVS reset: device ready after %dms\n",
1984 (310 - ch->resetting) * 100);
1985 }
1986 ch->resetting = 0;
1987 xpt_release_simq(ch->sim, TRUE);
1988 return;
1989 }
1990 if (ch->resetting == 0) {
1991 device_printf(dev,
1992 "MVS reset: device not ready after 31000ms\n");
1993 xpt_release_simq(ch->sim, TRUE);
1994 return;
1995 }
1996 callout_schedule(&ch->reset_timer, hz / 10);
1997 }
1998
1999 static void
mvs_errata(device_t dev)2000 mvs_errata(device_t dev)
2001 {
2002 struct mvs_channel *ch = device_get_softc(dev);
2003 uint32_t val;
2004
2005 if (ch->quirks & MVS_Q_SOC65) {
2006 val = ATA_INL(ch->r_mem, SATA_PHYM3);
2007 val &= ~(0x3 << 27); /* SELMUPF = 1 */
2008 val |= (0x1 << 27);
2009 val &= ~(0x3 << 29); /* SELMUPI = 1 */
2010 val |= (0x1 << 29);
2011 ATA_OUTL(ch->r_mem, SATA_PHYM3, val);
2012
2013 val = ATA_INL(ch->r_mem, SATA_PHYM4);
2014 val &= ~0x1; /* SATU_OD8 = 0 */
2015 val |= (0x1 << 16); /* reserved bit 16 = 1 */
2016 ATA_OUTL(ch->r_mem, SATA_PHYM4, val);
2017
2018 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
2019 val &= ~0xf; /* TXAMP[3:0] = 8 */
2020 val |= 0x8;
2021 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2022 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val);
2023
2024 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
2025 val &= ~0xf; /* TXAMP[3:0] = 8 */
2026 val |= 0x8;
2027 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */
2028 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val);
2029 }
2030 }
2031
2032 static void
mvs_reset(device_t dev)2033 mvs_reset(device_t dev)
2034 {
2035 struct mvs_channel *ch = device_get_softc(dev);
2036 int i;
2037
2038 xpt_freeze_simq(ch->sim, 1);
2039 if (bootverbose)
2040 device_printf(dev, "MVS reset...\n");
2041 /* Forget about previous reset. */
2042 if (ch->resetting) {
2043 ch->resetting = 0;
2044 callout_stop(&ch->reset_timer);
2045 xpt_release_simq(ch->sim, TRUE);
2046 }
2047 /* Requeue freezed command. */
2048 mvs_requeue_frozen(dev);
2049 /* Kill the engine and requeue all running commands. */
2050 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2051 ATA_OUTL(ch->r_mem, DMA_C, 0);
2052 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2053 /* Do we have a running request on slot? */
2054 if (ch->slot[i].state < MVS_SLOT_RUNNING)
2055 continue;
2056 /* XXX; Commands in loading state. */
2057 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT);
2058 }
2059 for (i = 0; i < MVS_MAX_SLOTS; i++) {
2060 if (!ch->hold[i])
2061 continue;
2062 xpt_done(ch->hold[i]);
2063 ch->hold[i] = NULL;
2064 ch->numhslots--;
2065 }
2066 if (ch->toslots != 0)
2067 xpt_release_simq(ch->sim, TRUE);
2068 ch->eslots = 0;
2069 ch->toslots = 0;
2070 ch->fatalerr = 0;
2071 ch->fake_busy = 0;
2072 /* Tell the XPT about the event */
2073 xpt_async(AC_BUS_RESET, ch->path, NULL);
2074 ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
2075 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST);
2076 DELAY(25);
2077 ATA_OUTL(ch->r_mem, EDMA_CMD, 0);
2078 mvs_errata(dev);
2079 /* Reset and reconnect PHY, */
2080 if (!mvs_sata_phy_reset(dev)) {
2081 if (bootverbose)
2082 device_printf(dev, "MVS reset: device not found\n");
2083 ch->devices = 0;
2084 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2085 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2086 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2087 xpt_release_simq(ch->sim, TRUE);
2088 return;
2089 }
2090 if (bootverbose)
2091 device_printf(dev, "MVS reset: device found\n");
2092 /* Wait for clearing busy status. */
2093 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ,
2094 dumping ? 31000 : 0)) < 0) {
2095 if (dumping) {
2096 device_printf(dev,
2097 "MVS reset: device not ready after 31000ms\n");
2098 } else
2099 ch->resetting = 310;
2100 } else if (bootverbose)
2101 device_printf(dev, "MVS reset: device ready after %dms\n", i);
2102 ch->devices = 1;
2103 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2104 ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2105 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2106 if (ch->resetting)
2107 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev);
2108 else
2109 xpt_release_simq(ch->sim, TRUE);
2110 }
2111
2112 static void
mvs_softreset(device_t dev,union ccb * ccb)2113 mvs_softreset(device_t dev, union ccb *ccb)
2114 {
2115 struct mvs_channel *ch = device_get_softc(dev);
2116 int port = ccb->ccb_h.target_id & 0x0f;
2117 int i, stuck;
2118 uint8_t status;
2119
2120 mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2121 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
2122 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2123 DELAY(10000);
2124 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2125 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2126 /* Wait for clearing busy status. */
2127 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
2128 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2129 stuck = 1;
2130 } else {
2131 status = mvs_getstatus(dev, 0);
2132 if (status & ATA_S_ERROR)
2133 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2134 else
2135 ccb->ccb_h.status |= CAM_REQ_CMP;
2136 if (status & ATA_S_DRQ)
2137 stuck = 1;
2138 else
2139 stuck = 0;
2140 }
2141 mvs_tfd_read(dev, ccb);
2142
2143 /*
2144 * XXX: If some device on PMP failed to soft-reset,
2145 * try to recover by sending dummy soft-reset to PMP.
2146 */
2147 if (stuck && ch->pm_present && port != 15) {
2148 ATA_OUTB(ch->r_mem, SATA_SATAICTL,
2149 15 << SATA_SATAICTL_PMPTX_SHIFT);
2150 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2151 DELAY(10000);
2152 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2153 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
2154 }
2155
2156 xpt_done(ccb);
2157 }
2158
2159 static int
mvs_sata_connect(struct mvs_channel * ch)2160 mvs_sata_connect(struct mvs_channel *ch)
2161 {
2162 u_int32_t status;
2163 int timeout, found = 0;
2164
2165 /* Wait up to 100ms for "connect well" */
2166 for (timeout = 0; timeout < 1000 ; timeout++) {
2167 status = ATA_INL(ch->r_mem, SATA_SS);
2168 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE)
2169 found = 1;
2170 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
2171 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
2172 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE))
2173 break;
2174 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) {
2175 if (bootverbose) {
2176 device_printf(ch->dev, "SATA offline status=%08x\n",
2177 status);
2178 }
2179 return (0);
2180 }
2181 if (found == 0 && timeout >= 100)
2182 break;
2183 DELAY(100);
2184 }
2185 if (timeout >= 1000 || !found) {
2186 if (bootverbose) {
2187 device_printf(ch->dev,
2188 "SATA connect timeout time=%dus status=%08x\n",
2189 timeout * 100, status);
2190 }
2191 return (0);
2192 }
2193 if (bootverbose) {
2194 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2195 timeout * 100, status);
2196 }
2197 /* Clear SATA error register */
2198 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2199 return (1);
2200 }
2201
2202 static int
mvs_sata_phy_reset(device_t dev)2203 mvs_sata_phy_reset(device_t dev)
2204 {
2205 struct mvs_channel *ch = device_get_softc(dev);
2206 int sata_rev;
2207 uint32_t val;
2208
2209 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2210 if (sata_rev == 1)
2211 val = SATA_SC_SPD_SPEED_GEN1;
2212 else if (sata_rev == 2)
2213 val = SATA_SC_SPD_SPEED_GEN2;
2214 else if (sata_rev == 3)
2215 val = SATA_SC_SPD_SPEED_GEN3;
2216 else
2217 val = 0;
2218 ATA_OUTL(ch->r_mem, SATA_SC,
2219 SATA_SC_DET_RESET | val |
2220 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER);
2221 DELAY(1000);
2222 ATA_OUTL(ch->r_mem, SATA_SC,
2223 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2224 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER)));
2225 if (!mvs_sata_connect(ch)) {
2226 if (ch->pm_level > 0)
2227 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE);
2228 return (0);
2229 }
2230 return (1);
2231 }
2232
2233 static int
mvs_check_ids(device_t dev,union ccb * ccb)2234 mvs_check_ids(device_t dev, union ccb *ccb)
2235 {
2236 struct mvs_channel *ch = device_get_softc(dev);
2237
2238 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) {
2239 ccb->ccb_h.status = CAM_TID_INVALID;
2240 xpt_done(ccb);
2241 return (-1);
2242 }
2243 if (ccb->ccb_h.target_lun != 0) {
2244 ccb->ccb_h.status = CAM_LUN_INVALID;
2245 xpt_done(ccb);
2246 return (-1);
2247 }
2248 /*
2249 * It's a programming error to see AUXILIARY register requests.
2250 */
2251 KASSERT(ccb->ccb_h.func_code != XPT_ATA_IO ||
2252 ((ccb->ataio.ata_flags & ATA_FLAG_AUX) == 0),
2253 ("AUX register unsupported"));
2254 return (0);
2255 }
2256
2257 static void
mvsaction(struct cam_sim * sim,union ccb * ccb)2258 mvsaction(struct cam_sim *sim, union ccb *ccb)
2259 {
2260 device_t dev, parent;
2261 struct mvs_channel *ch;
2262
2263 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n",
2264 ccb->ccb_h.func_code));
2265
2266 ch = (struct mvs_channel *)cam_sim_softc(sim);
2267 dev = ch->dev;
2268 switch (ccb->ccb_h.func_code) {
2269 /* Common cases first */
2270 case XPT_ATA_IO: /* Execute the requested I/O operation */
2271 case XPT_SCSI_IO:
2272 if (mvs_check_ids(dev, ccb))
2273 return;
2274 if (ch->devices == 0 ||
2275 (ch->pm_present == 0 &&
2276 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2277 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2278 break;
2279 }
2280 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2281 /* Check for command collision. */
2282 if (mvs_check_collision(dev, ccb)) {
2283 /* Freeze command. */
2284 ch->frozen = ccb;
2285 /* We have only one frozen slot, so freeze simq also. */
2286 xpt_freeze_simq(ch->sim, 1);
2287 return;
2288 }
2289 mvs_begin_transaction(dev, ccb);
2290 return;
2291 case XPT_ABORT: /* Abort the specified CCB */
2292 /* XXX Implement */
2293 ccb->ccb_h.status = CAM_REQ_INVALID;
2294 break;
2295 case XPT_SET_TRAN_SETTINGS:
2296 {
2297 struct ccb_trans_settings *cts = &ccb->cts;
2298 struct mvs_device *d;
2299
2300 if (mvs_check_ids(dev, ccb))
2301 return;
2302 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2303 d = &ch->curr[ccb->ccb_h.target_id];
2304 else
2305 d = &ch->user[ccb->ccb_h.target_id];
2306 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2307 d->revision = cts->xport_specific.sata.revision;
2308 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2309 d->mode = cts->xport_specific.sata.mode;
2310 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) {
2311 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048,
2312 cts->xport_specific.sata.bytecount);
2313 }
2314 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2315 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags);
2316 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2317 ch->pm_present = cts->xport_specific.sata.pm_present;
2318 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2319 d->atapi = cts->xport_specific.sata.atapi;
2320 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2321 d->caps = cts->xport_specific.sata.caps;
2322 ccb->ccb_h.status = CAM_REQ_CMP;
2323 break;
2324 }
2325 case XPT_GET_TRAN_SETTINGS:
2326 /* Get default/user set transfer settings for the target */
2327 {
2328 struct ccb_trans_settings *cts = &ccb->cts;
2329 struct mvs_device *d;
2330 uint32_t status;
2331
2332 if (mvs_check_ids(dev, ccb))
2333 return;
2334 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2335 d = &ch->curr[ccb->ccb_h.target_id];
2336 else
2337 d = &ch->user[ccb->ccb_h.target_id];
2338 cts->protocol = PROTO_UNSPECIFIED;
2339 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2340 cts->transport = XPORT_SATA;
2341 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2342 cts->proto_specific.valid = 0;
2343 cts->xport_specific.sata.valid = 0;
2344 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2345 (ccb->ccb_h.target_id == 15 ||
2346 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2347 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
2348 if (status & 0x0f0) {
2349 cts->xport_specific.sata.revision =
2350 (status & 0x0f0) >> 4;
2351 cts->xport_specific.sata.valid |=
2352 CTS_SATA_VALID_REVISION;
2353 }
2354 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2355 // if (ch->pm_level)
2356 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2357 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2358 cts->xport_specific.sata.caps &=
2359 ch->user[ccb->ccb_h.target_id].caps;
2360 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2361 } else {
2362 cts->xport_specific.sata.revision = d->revision;
2363 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2364 cts->xport_specific.sata.caps = d->caps;
2365 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* &&
2366 (ch->quirks & MVS_Q_GENIIE) == 0*/)
2367 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN;
2368 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2369 }
2370 cts->xport_specific.sata.mode = d->mode;
2371 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2372 cts->xport_specific.sata.bytecount = d->bytecount;
2373 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2374 cts->xport_specific.sata.pm_present = ch->pm_present;
2375 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2376 cts->xport_specific.sata.tags = d->tags;
2377 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2378 cts->xport_specific.sata.atapi = d->atapi;
2379 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2380 ccb->ccb_h.status = CAM_REQ_CMP;
2381 break;
2382 }
2383 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2384 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2385 mvs_reset(dev);
2386 ccb->ccb_h.status = CAM_REQ_CMP;
2387 break;
2388 case XPT_TERM_IO: /* Terminate the I/O process */
2389 /* XXX Implement */
2390 ccb->ccb_h.status = CAM_REQ_INVALID;
2391 break;
2392 case XPT_PATH_INQ: /* Path routing inquiry */
2393 {
2394 struct ccb_pathinq *cpi = &ccb->cpi;
2395
2396 parent = device_get_parent(dev);
2397 cpi->version_num = 1; /* XXX??? */
2398 cpi->hba_inquiry = PI_SDTR_ABLE;
2399 if (!(ch->quirks & MVS_Q_GENI)) {
2400 cpi->hba_inquiry |= PI_SATAPM;
2401 /* Gen-II is extremely slow with NCQ on PMP. */
2402 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0)
2403 cpi->hba_inquiry |= PI_TAG_ABLE;
2404 }
2405 cpi->target_sprt = 0;
2406 cpi->hba_misc = PIM_SEQSCAN;
2407 cpi->hba_eng_cnt = 0;
2408 if (!(ch->quirks & MVS_Q_GENI))
2409 cpi->max_target = 15;
2410 else
2411 cpi->max_target = 0;
2412 cpi->max_lun = 0;
2413 cpi->initiator_id = 0;
2414 cpi->bus_id = cam_sim_bus(sim);
2415 cpi->base_transfer_speed = 150000;
2416 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2417 strlcpy(cpi->hba_vid, "Marvell", HBA_IDLEN);
2418 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2419 cpi->unit_number = cam_sim_unit(sim);
2420 cpi->transport = XPORT_SATA;
2421 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2422 cpi->protocol = PROTO_ATA;
2423 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2424 cpi->maxio = maxphys;
2425 if ((ch->quirks & MVS_Q_SOC) == 0) {
2426 cpi->hba_vendor = pci_get_vendor(parent);
2427 cpi->hba_device = pci_get_device(parent);
2428 cpi->hba_subvendor = pci_get_subvendor(parent);
2429 cpi->hba_subdevice = pci_get_subdevice(parent);
2430 }
2431 cpi->ccb_h.status = CAM_REQ_CMP;
2432 break;
2433 }
2434 default:
2435 ccb->ccb_h.status = CAM_REQ_INVALID;
2436 break;
2437 }
2438 xpt_done(ccb);
2439 }
2440
2441 static void
mvspoll(struct cam_sim * sim)2442 mvspoll(struct cam_sim *sim)
2443 {
2444 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim);
2445 struct mvs_intr_arg arg;
2446
2447 arg.arg = ch->dev;
2448 arg.cause = 2 | 4; /* XXX */
2449 mvs_ch_intr(&arg);
2450 if (ch->resetting != 0 &&
2451 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2452 ch->resetpolldiv = 1000;
2453 mvs_reset_to(ch->dev);
2454 }
2455 }
2456