xref: /freebsd-13.1/sys/dev/mlx5/driver.h (revision 4deb6e4f) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 #include <linux/wait.h>
45 
46 #include <dev/mlx5/device.h>
47 #include <dev/mlx5/doorbell.h>
48 #include <dev/mlx5/srq.h>
49 
50 #define MLX5_QCOUNTER_SETS_NETDEV 64
51 #define MLX5_MAX_NUMBER_OF_VFS 128
52 
53 enum {
54 	MLX5_BOARD_ID_LEN = 64,
55 	MLX5_MAX_NAME_LEN = 16,
56 };
57 
58 enum {
59 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_ATOMIC_MODE_OFF		= 16,
89 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
90 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
98 };
99 
100 enum {
101 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
102 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
103 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
111 };
112 
113 enum {
114 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
115 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
116 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
117 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
118 };
119 
120 enum {
121 	MLX5_REG_QPTS		 = 0x4002,
122 	MLX5_REG_QETCR		 = 0x4005,
123 	MLX5_REG_QPDP		 = 0x4007,
124 	MLX5_REG_QTCT		 = 0x400A,
125 	MLX5_REG_QPDPM		 = 0x4013,
126 	MLX5_REG_QHLL		 = 0x4016,
127 	MLX5_REG_QCAM		 = 0x4019,
128 	MLX5_REG_DCBX_PARAM	 = 0x4020,
129 	MLX5_REG_DCBX_APP	 = 0x4021,
130 	MLX5_REG_FPGA_CAP	 = 0x4022,
131 	MLX5_REG_FPGA_CTRL	 = 0x4023,
132 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
133 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_PMLP		 = 0x5002,
136 	MLX5_REG_PMTU		 = 0x5003,
137 	MLX5_REG_PTYS		 = 0x5004,
138 	MLX5_REG_PAOS		 = 0x5006,
139 	MLX5_REG_PFCC		 = 0x5007,
140 	MLX5_REG_PPCNT		 = 0x5008,
141 	MLX5_REG_PUDE		 = 0x5009,
142 	MLX5_REG_PPTB		 = 0x500B,
143 	MLX5_REG_PBMC		 = 0x500C,
144 	MLX5_REG_PELC		 = 0x500E,
145 	MLX5_REG_PVLC		 = 0x500F,
146 	MLX5_REG_PMPE		 = 0x5010,
147 	MLX5_REG_PMAOS		 = 0x5012,
148 	MLX5_REG_PPLM		 = 0x5023,
149 	MLX5_REG_PDDR		 = 0x5031,
150 	MLX5_REG_PBSR		 = 0x5038,
151 	MLX5_REG_PCAM		 = 0x507f,
152 	MLX5_REG_NODE_DESC	 = 0x6001,
153 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
154 	MLX5_REG_MTMP		 = 0x900a,
155 	MLX5_REG_MCIA		 = 0x9014,
156 	MLX5_REG_MFRL		 = 0x9028,
157 	MLX5_REG_MPCNT		 = 0x9051,
158 	MLX5_REG_MCQI		 = 0x9061,
159 	MLX5_REG_MCC		 = 0x9062,
160 	MLX5_REG_MCDA		 = 0x9063,
161 	MLX5_REG_MCAM		 = 0x907f,
162 };
163 
164 enum dbg_rsc_type {
165 	MLX5_DBG_RSC_QP,
166 	MLX5_DBG_RSC_EQ,
167 	MLX5_DBG_RSC_CQ,
168 };
169 
170 enum {
171 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
172 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
173 	MLX5_INTERFACE_NUMBER       = 2,
174 };
175 
176 struct mlx5_field_desc {
177 	struct dentry	       *dent;
178 	int			i;
179 };
180 
181 struct mlx5_rsc_debug {
182 	struct mlx5_core_dev   *dev;
183 	void		       *object;
184 	enum dbg_rsc_type	type;
185 	struct dentry	       *root;
186 	struct mlx5_field_desc	fields[0];
187 };
188 
189 enum mlx5_dev_event {
190 	MLX5_DEV_EVENT_SYS_ERROR,
191 	MLX5_DEV_EVENT_PORT_UP,
192 	MLX5_DEV_EVENT_PORT_DOWN,
193 	MLX5_DEV_EVENT_PORT_INITIALIZED,
194 	MLX5_DEV_EVENT_LID_CHANGE,
195 	MLX5_DEV_EVENT_PKEY_CHANGE,
196 	MLX5_DEV_EVENT_GUID_CHANGE,
197 	MLX5_DEV_EVENT_CLIENT_REREG,
198 	MLX5_DEV_EVENT_VPORT_CHANGE,
199 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
201 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
202 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
203 };
204 
205 enum mlx5_port_status {
206 	MLX5_PORT_UP        = 1 << 0,
207 	MLX5_PORT_DOWN      = 1 << 1,
208 };
209 
210 enum {
211 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
212 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
213 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
214 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
215 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
216 	MLX5_VSC_DATA_OFFSET	 = 0x14,
217 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
218 };
219 
220 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
221 
222 struct mlx5_cmd_first {
223 	__be32		data[4];
224 };
225 
226 struct cache_ent;
227 struct mlx5_fw_page {
228 	union {
229 		struct rb_node rb_node;
230 		struct list_head list;
231 	};
232 	struct mlx5_cmd_first first;
233 	struct mlx5_core_dev *dev;
234 	bus_dmamap_t dma_map;
235 	bus_addr_t dma_addr;
236 	void *virt_addr;
237 	struct cache_ent *cache;
238 	u32 numpages;
239 	u16 load_done;
240 #define	MLX5_LOAD_ST_NONE 0
241 #define	MLX5_LOAD_ST_SUCCESS 1
242 #define	MLX5_LOAD_ST_FAILURE 2
243 	u16 func_id;
244 };
245 #define	mlx5_cmd_msg mlx5_fw_page
246 
247 struct mlx5_cmd_debug {
248 	struct dentry	       *dbg_root;
249 	struct dentry	       *dbg_in;
250 	struct dentry	       *dbg_out;
251 	struct dentry	       *dbg_outlen;
252 	struct dentry	       *dbg_status;
253 	struct dentry	       *dbg_run;
254 	void		       *in_msg;
255 	void		       *out_msg;
256 	u8			status;
257 	u16			inlen;
258 	u16			outlen;
259 };
260 
261 struct cache_ent {
262 	/* protect block chain allocations
263 	 */
264 	spinlock_t		lock;
265 	struct list_head	head;
266 };
267 
268 struct cmd_msg_cache {
269 	struct cache_ent	large;
270 	struct cache_ent	med;
271 
272 };
273 
274 struct mlx5_traffic_counter {
275 	u64         packets;
276 	u64         octets;
277 };
278 
279 enum mlx5_cmd_mode {
280 	MLX5_CMD_MODE_POLLING,
281 	MLX5_CMD_MODE_EVENTS
282 };
283 
284 struct mlx5_cmd_stats {
285 	u64		sum;
286 	u64		n;
287 	struct dentry  *root;
288 	struct dentry  *avg;
289 	struct dentry  *count;
290 	/* protect command average calculations */
291 	spinlock_t	lock;
292 };
293 
294 struct mlx5_cmd {
295 	struct mlx5_fw_page *cmd_page;
296 	bus_dma_tag_t dma_tag;
297 	struct sx dma_sx;
298 	struct mtx dma_mtx;
299 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
300 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
301 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
302 	struct cv dma_cv;
303 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
304 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
305 	void	       *cmd_buf;
306 	dma_addr_t	dma;
307 	u16		cmdif_rev;
308 	u8		log_sz;
309 	u8		log_stride;
310 	int		max_reg_cmds;
311 	int		events;
312 	u32 __iomem    *vector;
313 
314 	/* protect command queue allocations
315 	 */
316 	spinlock_t	alloc_lock;
317 
318 	/* protect token allocations
319 	 */
320 	spinlock_t	token_lock;
321 	u8		token;
322 	unsigned long	bitmask;
323 	struct semaphore sem;
324 	struct semaphore pages_sem;
325 	enum mlx5_cmd_mode mode;
326 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
327 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
328 	struct mlx5_cmd_debug dbg;
329 	struct cmd_msg_cache cache;
330 	int checksum_disabled;
331 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
332 };
333 
334 struct mlx5_port_caps {
335 	int	gid_table_len;
336 	int	pkey_table_len;
337 	u8	ext_port_cap;
338 };
339 
340 struct mlx5_buf {
341 	bus_dma_tag_t		dma_tag;
342 	bus_dmamap_t		dma_map;
343 	struct mlx5_core_dev   *dev;
344 	struct {
345 		void	       *buf;
346 	} direct;
347 	u64		       *page_list;
348 	int			npages;
349 	int			size;
350 	u8			page_shift;
351 	u8			load_done;
352 };
353 
354 struct mlx5_frag_buf {
355 	struct mlx5_buf_list	*frags;
356 	int			npages;
357 	int			size;
358 	u8			page_shift;
359 };
360 
361 struct mlx5_eq {
362 	struct mlx5_core_dev   *dev;
363 	__be32 __iomem	       *doorbell;
364 	u32			cons_index;
365 	struct mlx5_buf		buf;
366 	int			size;
367 	u8			irqn;
368 	u8			eqn;
369 	int			nent;
370 	u64			mask;
371 	struct list_head	list;
372 	int			index;
373 	struct mlx5_rsc_debug	*dbg;
374 };
375 
376 struct mlx5_core_psv {
377 	u32	psv_idx;
378 	struct psv_layout {
379 		u32	pd;
380 		u16	syndrome;
381 		u16	reserved;
382 		u16	bg;
383 		u16	app_tag;
384 		u32	ref_tag;
385 	} psv;
386 };
387 
388 struct mlx5_core_sig_ctx {
389 	struct mlx5_core_psv	psv_memory;
390 	struct mlx5_core_psv	psv_wire;
391 	struct ib_sig_err       err_item;
392 	bool			sig_status_checked;
393 	bool			sig_err_exists;
394 	u32			sigerr_count;
395 };
396 
397 enum {
398 	MLX5_MKEY_MR = 1,
399 	MLX5_MKEY_MW,
400 	MLX5_MKEY_MR_USER,
401 };
402 
403 struct mlx5_core_mkey {
404 	u64			iova;
405 	u64			size;
406 	u32			key;
407 	u32			pd;
408 	u32			type;
409 };
410 
411 struct mlx5_core_mr {
412 	u64			iova;
413 	u64			size;
414 	u32			key;
415 	u32			pd;
416 };
417 
418 enum mlx5_res_type {
419 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
420 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
421 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
422 	MLX5_RES_SRQ	= 3,
423 	MLX5_RES_XSRQ	= 4,
424 	MLX5_RES_DCT	= 5,
425 };
426 
427 struct mlx5_core_rsc_common {
428 	enum mlx5_res_type	res;
429 	atomic_t		refcount;
430 	struct completion	free;
431 };
432 
433 struct mlx5_uars_page {
434 	void __iomem	       *map;
435 	bool			wc;
436 	u32			index;
437 	struct list_head	list;
438 	unsigned int		bfregs;
439 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
440 	unsigned long	       *fp_bitmap;
441 	unsigned int		reg_avail;
442 	unsigned int		fp_avail;
443 	struct kref		ref_count;
444 	struct mlx5_core_dev   *mdev;
445 };
446 
447 struct mlx5_bfreg_head {
448 	/* protect blue flame registers allocations */
449 	struct mutex		lock;
450 	struct list_head	list;
451 };
452 
453 struct mlx5_bfreg_data {
454 	struct mlx5_bfreg_head	reg_head;
455 	struct mlx5_bfreg_head	wc_head;
456 };
457 
458 struct mlx5_sq_bfreg {
459 	void __iomem	       *map;
460 	struct mlx5_uars_page  *up;
461 	bool			wc;
462 	u32			index;
463 	unsigned int		offset;
464 };
465 
466 struct mlx5_core_srq {
467 	struct mlx5_core_rsc_common	common; /* must be first */
468 	u32				srqn;
469 	int				max;
470 	size_t				max_gs;
471 	size_t				max_avail_gather;
472 	int				wqe_shift;
473 	void				(*event)(struct mlx5_core_srq *, int);
474 	atomic_t			refcount;
475 	struct completion		free;
476 };
477 
478 struct mlx5_eq_table {
479 	void __iomem	       *update_ci;
480 	void __iomem	       *update_arm_ci;
481 	struct list_head	comp_eqs_list;
482 	struct mlx5_eq		pages_eq;
483 	struct mlx5_eq		async_eq;
484 	struct mlx5_eq		cmd_eq;
485 	int			num_comp_vectors;
486 	/* protect EQs list
487 	 */
488 	spinlock_t		lock;
489 };
490 
491 struct mlx5_core_health {
492 	struct mlx5_health_buffer __iomem	*health;
493 	__be32 __iomem		       *health_counter;
494 	struct timer_list		timer;
495 	u32				prev;
496 	int				miss_counter;
497 	u32				fatal_error;
498 	struct workqueue_struct	       *wq_watchdog;
499 	struct work_struct		work_watchdog;
500 	/* wq spinlock to synchronize draining */
501 	spinlock_t			wq_lock;
502 	struct workqueue_struct	       *wq;
503 	unsigned long			flags;
504 	struct work_struct		work;
505 	struct delayed_work		recover_work;
506 	unsigned int			last_reset_req;
507 	struct work_struct		work_cmd_completion;
508 	struct workqueue_struct	       *wq_cmd;
509 };
510 
511 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
512 
513 struct mlx5_cq_linear_array_entry {
514 	struct mlx5_core_cq * volatile cq;
515 };
516 
517 struct mlx5_cq_table {
518 	/* protect radix tree
519 	 */
520 	spinlock_t		writerlock;
521 	atomic_t		writercount;
522 	struct radix_tree_root	tree;
523 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
524 };
525 
526 struct mlx5_qp_table {
527 	/* protect radix tree
528 	 */
529 	spinlock_t		lock;
530 	struct radix_tree_root	tree;
531 };
532 
533 struct mlx5_srq_table {
534 	/* protect radix tree
535 	 */
536 	spinlock_t		lock;
537 	struct radix_tree_root	tree;
538 };
539 
540 struct mlx5_mr_table {
541 	/* protect radix tree
542 	 */
543 	spinlock_t		lock;
544 	struct radix_tree_root	tree;
545 };
546 
547 #ifdef RATELIMIT
548 struct mlx5_rl_entry {
549 	u32			rate;
550 	u16			burst;
551 	u16			index;
552 	u32			refcount;
553 };
554 
555 struct mlx5_rl_table {
556 	struct mutex		rl_lock;
557 	u16			max_size;
558 	u32			max_rate;
559 	u32			min_rate;
560 	struct mlx5_rl_entry   *rl_entry;
561 };
562 #endif
563 
564 struct mlx5_pme_stats {
565 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
566 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
567 };
568 
569 struct mlx5_priv {
570 	char			name[MLX5_MAX_NAME_LEN];
571 	struct mlx5_eq_table	eq_table;
572 	struct msix_entry	*msix_arr;
573 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
574 	int			disable_irqs;
575 
576 	/* pages stuff */
577 	struct workqueue_struct *pg_wq;
578 	struct rb_root		page_root;
579 	s64			fw_pages;
580 	atomic_t		reg_pages;
581 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
582 	struct mlx5_core_health health;
583 
584 	struct mlx5_srq_table	srq_table;
585 
586 	/* start: qp staff */
587 	struct mlx5_qp_table	qp_table;
588 	struct dentry	       *qp_debugfs;
589 	struct dentry	       *eq_debugfs;
590 	struct dentry	       *cq_debugfs;
591 	struct dentry	       *cmdif_debugfs;
592 	/* end: qp staff */
593 
594 	/* start: cq staff */
595 	struct mlx5_cq_table	cq_table;
596 	/* end: cq staff */
597 
598 	/* start: mr staff */
599 	struct mlx5_mr_table	mr_table;
600 	/* end: mr staff */
601 
602 	/* start: alloc staff */
603 	int			numa_node;
604 
605 	struct mutex   pgdir_mutex;
606 	struct list_head        pgdir_list;
607 	/* end: alloc staff */
608 	struct dentry	       *dbg_root;
609 
610 	/* protect mkey key part */
611 	spinlock_t		mkey_lock;
612 	u8			mkey_key;
613 
614 	struct list_head        dev_list;
615 	struct list_head        ctx_list;
616 	spinlock_t              ctx_lock;
617 	unsigned long		pci_dev_data;
618 #ifdef RATELIMIT
619 	struct mlx5_rl_table	rl_table;
620 #endif
621 	struct mlx5_pme_stats pme_stats;
622 
623 	struct mlx5_eswitch	*eswitch;
624 
625 	struct mlx5_bfreg_data		bfregs;
626 	struct mlx5_uars_page	       *uar;
627 };
628 
629 enum mlx5_device_state {
630 	MLX5_DEVICE_STATE_UP,
631 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
632 };
633 
634 enum mlx5_interface_state {
635 	MLX5_INTERFACE_STATE_UP = 0x1,
636 	MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
637 };
638 
639 enum mlx5_pci_status {
640 	MLX5_PCI_STATUS_DISABLED,
641 	MLX5_PCI_STATUS_ENABLED,
642 };
643 
644 #define	MLX5_MAX_RESERVED_GIDS	8
645 
646 struct mlx5_rsvd_gids {
647 	unsigned int start;
648 	unsigned int count;
649 	struct ida ida;
650 };
651 
652 struct mlx5_special_contexts {
653 	int resd_lkey;
654 };
655 
656 struct mlx5_flow_root_namespace;
657 struct mlx5_core_dev {
658 	struct pci_dev	       *pdev;
659 	/* sync pci state */
660 	struct mutex		pci_status_mutex;
661 	enum mlx5_pci_status	pci_status;
662 	char			board_id[MLX5_BOARD_ID_LEN];
663 	struct mlx5_cmd		cmd;
664 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
665 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
666 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
667 	struct {
668 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
669 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
670 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
671 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
672 	} caps;
673 	phys_addr_t		iseg_base;
674 	struct mlx5_init_seg __iomem *iseg;
675 	enum mlx5_device_state	state;
676 	/* sync interface state */
677 	struct mutex		intf_state_mutex;
678 	unsigned long		intf_state;
679 	void			(*event) (struct mlx5_core_dev *dev,
680 					  enum mlx5_dev_event event,
681 					  unsigned long param);
682 	struct mlx5_priv	priv;
683 	struct mlx5_profile	*profile;
684 	atomic_t		num_qps;
685 	u32			vsc_addr;
686 	u32			issi;
687 	struct mlx5_special_contexts special_contexts;
688 	unsigned int module_status[MLX5_MAX_PORTS];
689 	struct mlx5_flow_root_namespace *root_ns;
690 	struct mlx5_flow_root_namespace *fdb_root_ns;
691 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
692 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
693 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
694 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
695 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
696 	struct mlx5_crspace_regmap *dump_rege;
697 	uint32_t *dump_data;
698 	unsigned dump_size;
699 	bool dump_valid;
700 	bool dump_copyout;
701 	struct mtx dump_lock;
702 
703 	struct sysctl_ctx_list	sysctl_ctx;
704 	int			msix_eqvec;
705 	int			pwr_status;
706 	int			pwr_value;
707 
708 	struct {
709 		struct mlx5_rsvd_gids	reserved_gids;
710 		atomic_t		roce_en;
711 	} roce;
712 
713 	struct {
714 		spinlock_t	spinlock;
715 #define	MLX5_MPFS_TABLE_MAX 32
716 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
717 	} mpfs;
718 #ifdef CONFIG_MLX5_FPGA
719 	struct mlx5_fpga_device	*fpga;
720 #endif
721 };
722 
723 enum {
724 	MLX5_WOL_DISABLE       = 0,
725 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
726 	MLX5_WOL_MAGIC         = 1 << 2,
727 	MLX5_WOL_ARP           = 1 << 3,
728 	MLX5_WOL_BROADCAST     = 1 << 4,
729 	MLX5_WOL_MULTICAST     = 1 << 5,
730 	MLX5_WOL_UNICAST       = 1 << 6,
731 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
732 };
733 
734 struct mlx5_db {
735 	__be32			*db;
736 	union {
737 		struct mlx5_db_pgdir		*pgdir;
738 		struct mlx5_ib_user_db_page	*user_page;
739 	}			u;
740 	dma_addr_t		dma;
741 	int			index;
742 };
743 
744 struct mlx5_net_counters {
745 	u64	packets;
746 	u64	octets;
747 };
748 
749 struct mlx5_ptys_reg {
750 	u8	an_dis_admin;
751 	u8	an_dis_ap;
752 	u8	local_port;
753 	u8	proto_mask;
754 	u32	eth_proto_cap;
755 	u16	ib_link_width_cap;
756 	u16	ib_proto_cap;
757 	u32	eth_proto_admin;
758 	u16	ib_link_width_admin;
759 	u16	ib_proto_admin;
760 	u32	eth_proto_oper;
761 	u16	ib_link_width_oper;
762 	u16	ib_proto_oper;
763 	u32	eth_proto_lp_advertise;
764 };
765 
766 struct mlx5_pvlc_reg {
767 	u8	local_port;
768 	u8	vl_hw_cap;
769 	u8	vl_admin;
770 	u8	vl_operational;
771 };
772 
773 struct mlx5_pmtu_reg {
774 	u8	local_port;
775 	u16	max_mtu;
776 	u16	admin_mtu;
777 	u16	oper_mtu;
778 };
779 
780 struct mlx5_vport_counters {
781 	struct mlx5_net_counters	received_errors;
782 	struct mlx5_net_counters	transmit_errors;
783 	struct mlx5_net_counters	received_ib_unicast;
784 	struct mlx5_net_counters	transmitted_ib_unicast;
785 	struct mlx5_net_counters	received_ib_multicast;
786 	struct mlx5_net_counters	transmitted_ib_multicast;
787 	struct mlx5_net_counters	received_eth_broadcast;
788 	struct mlx5_net_counters	transmitted_eth_broadcast;
789 	struct mlx5_net_counters	received_eth_unicast;
790 	struct mlx5_net_counters	transmitted_eth_unicast;
791 	struct mlx5_net_counters	received_eth_multicast;
792 	struct mlx5_net_counters	transmitted_eth_multicast;
793 };
794 
795 enum {
796 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
797 };
798 
799 struct mlx5_core_dct {
800 	struct mlx5_core_rsc_common	common; /* must be first */
801 	void (*event)(struct mlx5_core_dct *, int);
802 	int			dctn;
803 	struct completion	drained;
804 	struct mlx5_rsc_debug	*dbg;
805 	int			pid;
806 	u16			uid;
807 };
808 
809 enum {
810 	MLX5_COMP_EQ_SIZE = 1024,
811 };
812 
813 enum {
814 	MLX5_PTYS_IB = 1 << 0,
815 	MLX5_PTYS_EN = 1 << 2,
816 };
817 
818 struct mlx5_db_pgdir {
819 	struct list_head	list;
820 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
821 	struct mlx5_fw_page    *fw_page;
822 	__be32		       *db_page;
823 	dma_addr_t		db_dma;
824 };
825 
826 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
827 
828 struct mlx5_cmd_work_ent {
829 	struct mlx5_cmd_msg    *in;
830 	struct mlx5_cmd_msg    *out;
831 	int			uin_size;
832 	void		       *uout;
833 	int			uout_size;
834 	mlx5_cmd_cbk_t		callback;
835         struct delayed_work     cb_timeout_work;
836 	void		       *context;
837 	int			idx;
838 	struct completion	done;
839 	struct mlx5_cmd        *cmd;
840 	struct work_struct	work;
841 	struct mlx5_cmd_layout *lay;
842 	int			ret;
843 	int			page_queue;
844 	u8			status;
845 	u8			token;
846 	u64			ts1;
847 	u64			ts2;
848 	u16			op;
849 	u8			busy;
850 	bool			polling;
851 };
852 
853 struct mlx5_pas {
854 	u64	pa;
855 	u8	log_sz;
856 };
857 
858 enum port_state_policy {
859 	MLX5_POLICY_DOWN        = 0,
860 	MLX5_POLICY_UP          = 1,
861 	MLX5_POLICY_FOLLOW      = 2,
862 	MLX5_POLICY_INVALID     = 0xffffffff
863 };
864 
865 static inline void *
866 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
867 {
868 	return ((char *)buf->direct.buf + offset);
869 }
870 
871 
872 extern struct workqueue_struct *mlx5_core_wq;
873 
874 #define STRUCT_FIELD(header, field) \
875 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
876 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
877 
878 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
879 {
880 	return pci_get_drvdata(pdev);
881 }
882 
883 extern struct dentry *mlx5_debugfs_root;
884 
885 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
886 {
887 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
888 }
889 
890 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
891 {
892 	return ioread32be(&dev->iseg->fw_rev) >> 16;
893 }
894 
895 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
896 {
897 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
898 }
899 
900 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
901 {
902 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
903 }
904 
905 static inline int mlx5_get_gid_table_len(u16 param)
906 {
907 	if (param > 4) {
908 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
909 		return 0;
910 	}
911 
912 	return 8 * (1 << param);
913 }
914 
915 static inline void *mlx5_vzalloc(unsigned long size)
916 {
917 	void *rtn;
918 
919 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
920 	return rtn;
921 }
922 
923 static inline void *mlx5_vmalloc(unsigned long size)
924 {
925 	void *rtn;
926 
927 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
928 	if (!rtn)
929 		rtn = vmalloc(size);
930 	return rtn;
931 }
932 
933 static inline u32 mlx5_base_mkey(const u32 key)
934 {
935 	return key & 0xffffff00u;
936 }
937 
938 int mlx5_cmd_init(struct mlx5_core_dev *dev);
939 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
940 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
941 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
942 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
943 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
944 
945 struct mlx5_async_ctx {
946 	struct mlx5_core_dev *dev;
947 	atomic_t num_inflight;
948 	struct wait_queue_head wait;
949 };
950 
951 struct mlx5_async_work;
952 
953 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
954 
955 struct mlx5_async_work {
956 	struct mlx5_async_ctx *ctx;
957 	mlx5_async_cbk_t user_callback;
958 };
959 
960 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
961 			     struct mlx5_async_ctx *ctx);
962 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
963 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
964 		     void *out, int out_size, mlx5_async_cbk_t callback,
965 		     struct mlx5_async_work *work);
966 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
967 		  int out_size);
968 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
969 			  void *out, int out_size);
970 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
971 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
972 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
973 		     bool map_wc, bool fast_path);
974 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
975 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
976 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
977 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
978 int mlx5_health_init(struct mlx5_core_dev *dev);
979 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
980 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
981 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
982 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
983 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
984 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
985 
986 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
987 		   struct mlx5_buf *buf);
988 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
989 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
990 			 struct mlx5_srq_attr *in);
991 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
992 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
993 			struct mlx5_srq_attr *out);
994 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
995 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
996 		      u16 lwm, int is_srq);
997 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
998 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
999 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1000 			     struct mlx5_core_mr *mkey,
1001 			     struct mlx5_async_ctx *async_ctx, u32 *in,
1002 			     int inlen, u32 *out, int outlen,
1003 			     mlx5_async_cbk_t callback,
1004 			     struct mlx5_async_work *context);
1005 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1006 			  struct mlx5_core_mr *mr,
1007 			  u32 *in, int inlen);
1008 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1009 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1010 			 u32 *out, int outlen);
1011 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1012 			     u32 *mkey);
1013 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1014 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1015 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1016 		      u16 opmod, u8 port);
1017 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1018 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1019 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1020 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1021 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1022 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1023 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1024 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1025 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1026 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1027 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1028 				 s32 npages);
1029 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1030 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1031 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1032 void mlx5_register_debugfs(void);
1033 void mlx5_unregister_debugfs(void);
1034 int mlx5_eq_init(struct mlx5_core_dev *dev);
1035 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1036 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1037 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1038 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1039 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1040 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1041 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1042 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1043 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1044 		       int nent, u64 mask);
1045 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1046 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1047 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1048 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1049 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1050 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1051 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1052 				u64 addr);
1053 
1054 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1055 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1056 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1057 			 int size_in, void *data_out, int size_out,
1058 			 u16 reg_num, int arg, int write);
1059 
1060 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1061 
1062 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1063 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1064 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1065 		       u32 *out, int outlen);
1066 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1067 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1068 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1069 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1070 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1071 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1072 
1073 static inline struct domainset *
1074 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1075 {
1076 	return (linux_get_vm_domain_set(mdev->priv.numa_node));
1077 }
1078 
1079 const char *mlx5_command_str(int command);
1080 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1081 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1082 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1083 			 int npsvs, u32 *sig_index);
1084 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1085 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1086 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1087 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1088 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1089 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1090 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1091 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1092 			  struct mlx5_pvlc_reg *pvlc, int write);
1093 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1094 			  struct mlx5_ptys_reg *ptys, int write);
1095 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1096 			  struct mlx5_pmtu_reg *pmtu, int write);
1097 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1098 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1099 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1100 				int priority, int *is_enable);
1101 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1102 				 int priority, int enable);
1103 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1104 				void *out, int out_size);
1105 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1106 				 void *in, int in_size);
1107 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1108 				    void *out, int out_size);
1109 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1110 			       int in_size);
1111 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1112 				   u8 num_of_samples, u16 sample_index,
1113 				   void *out, int out_size);
1114 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1115 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1116 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1117 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1118 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1119 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1120 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1121 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1122 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1123 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1124 			       u16 *p_power, u8 *p_status);
1125 
1126 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1127 {
1128 	return mkey >> 8;
1129 }
1130 
1131 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1132 {
1133 	return mkey_idx << 8;
1134 }
1135 
1136 static inline u8 mlx5_mkey_variant(u32 mkey)
1137 {
1138 	return mkey & 0xff;
1139 }
1140 
1141 enum {
1142 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1143 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1144 };
1145 
1146 enum {
1147 	MAX_MR_CACHE_ENTRIES    = 15,
1148 };
1149 
1150 struct mlx5_interface {
1151 	void *			(*add)(struct mlx5_core_dev *dev);
1152 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1153 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1154 					 enum mlx5_dev_event event, unsigned long param);
1155 	void *                  (*get_dev)(void *context);
1156 	int			protocol;
1157 	struct list_head	list;
1158 };
1159 
1160 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1161 int mlx5_register_interface(struct mlx5_interface *intf);
1162 void mlx5_unregister_interface(struct mlx5_interface *intf);
1163 
1164 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1165 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1166     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1167     const u8 *mac, bool vlan, u16 vlan_id);
1168 
1169 struct mlx5_profile {
1170 	u64	mask;
1171 	u8	log_max_qp;
1172 	struct {
1173 		int	size;
1174 		int	limit;
1175 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1176 };
1177 
1178 enum {
1179 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1180 };
1181 
1182 enum {
1183 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1184 };
1185 
1186 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1187 {
1188 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1189 }
1190 #ifdef RATELIMIT
1191 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1192 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1193 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1194 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1195 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1196 
1197 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1198 {
1199 	return !!(dev->priv.rl_table.max_size);
1200 }
1201 #endif
1202 
1203 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1204 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1205 
1206 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1207 {
1208         return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1209                        MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1210                        MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1211 }
1212 
1213 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1214 {
1215         return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1216                        MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1217                        MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1218 }
1219 
1220 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1221 {
1222         return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1223                        MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1224                        MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1225 }
1226 
1227 #endif /* MLX5_DRIVER_H */
1228