1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30
31 #include "opt_ratelimit.h"
32
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 #include <linux/wait.h>
45
46 #include <dev/mlx5/device.h>
47 #include <dev/mlx5/doorbell.h>
48 #include <dev/mlx5/srq.h>
49
50 #define MLX5_QCOUNTER_SETS_NETDEV 64
51 #define MLX5_MAX_NUMBER_OF_VFS 128
52
53 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff
54
55 enum {
56 MLX5_BOARD_ID_LEN = 64,
57 MLX5_MAX_NAME_LEN = 16,
58 };
59
60 enum {
61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
62 };
63
64 enum {
65 CMD_OWNER_SW = 0x0,
66 CMD_OWNER_HW = 0x1,
67 CMD_STATUS_SUCCESS = 0,
68 };
69
70 enum mlx5_sqp_t {
71 MLX5_SQP_SMI = 0,
72 MLX5_SQP_GSI = 1,
73 MLX5_SQP_IEEE_1588 = 2,
74 MLX5_SQP_SNIFFER = 3,
75 MLX5_SQP_SYNC_UMR = 4,
76 };
77
78 enum {
79 MLX5_MAX_PORTS = 2,
80 };
81
82 enum {
83 MLX5_EQ_VEC_PAGES = 0,
84 MLX5_EQ_VEC_CMD = 1,
85 MLX5_EQ_VEC_ASYNC = 2,
86 MLX5_EQ_VEC_COMP_BASE,
87 };
88
89 enum {
90 MLX5_ATOMIC_MODE_OFF = 16,
91 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF,
92 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF,
93 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF,
94 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF,
95 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF,
96 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF,
97 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF,
98 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF,
99 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF,
100 };
101
102 enum {
103 MLX5_ATOMIC_MODE_DCT_OFF = 20,
104 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
105 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
106 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
107 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF,
108 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF,
109 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF,
110 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF,
111 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF,
112 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF,
113 };
114
115 enum {
116 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
117 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
118 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2,
119 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3,
120 };
121
122 enum {
123 MLX5_REG_QPTS = 0x4002,
124 MLX5_REG_QETCR = 0x4005,
125 MLX5_REG_QPDP = 0x4007,
126 MLX5_REG_QTCT = 0x400A,
127 MLX5_REG_QPDPM = 0x4013,
128 MLX5_REG_QHLL = 0x4016,
129 MLX5_REG_QCAM = 0x4019,
130 MLX5_REG_DCBX_PARAM = 0x4020,
131 MLX5_REG_DCBX_APP = 0x4021,
132 MLX5_REG_FPGA_CAP = 0x4022,
133 MLX5_REG_FPGA_CTRL = 0x4023,
134 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
135 MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
136 MLX5_REG_PCAP = 0x5001,
137 MLX5_REG_PMLP = 0x5002,
138 MLX5_REG_PMTU = 0x5003,
139 MLX5_REG_PTYS = 0x5004,
140 MLX5_REG_PAOS = 0x5006,
141 MLX5_REG_PFCC = 0x5007,
142 MLX5_REG_PPCNT = 0x5008,
143 MLX5_REG_PUDE = 0x5009,
144 MLX5_REG_PPTB = 0x500B,
145 MLX5_REG_PBMC = 0x500C,
146 MLX5_REG_PELC = 0x500E,
147 MLX5_REG_PVLC = 0x500F,
148 MLX5_REG_PMPE = 0x5010,
149 MLX5_REG_PMAOS = 0x5012,
150 MLX5_REG_PPLM = 0x5023,
151 MLX5_REG_PDDR = 0x5031,
152 MLX5_REG_PBSR = 0x5038,
153 MLX5_REG_PCAM = 0x507f,
154 MLX5_REG_NODE_DESC = 0x6001,
155 MLX5_REG_HOST_ENDIANNESS = 0x7004,
156 MLX5_REG_MTMP = 0x900a,
157 MLX5_REG_MCIA = 0x9014,
158 MLX5_REG_MFRL = 0x9028,
159 MLX5_REG_MPCNT = 0x9051,
160 MLX5_REG_MCQI = 0x9061,
161 MLX5_REG_MCC = 0x9062,
162 MLX5_REG_MCDA = 0x9063,
163 MLX5_REG_MCAM = 0x907f,
164 };
165
166 enum dbg_rsc_type {
167 MLX5_DBG_RSC_QP,
168 MLX5_DBG_RSC_EQ,
169 MLX5_DBG_RSC_CQ,
170 };
171
172 enum {
173 MLX5_INTERFACE_PROTOCOL_IB = 0,
174 MLX5_INTERFACE_PROTOCOL_ETH = 1,
175 MLX5_INTERFACE_NUMBER = 2,
176 };
177
178 struct mlx5_field_desc {
179 struct dentry *dent;
180 int i;
181 };
182
183 struct mlx5_rsc_debug {
184 struct mlx5_core_dev *dev;
185 void *object;
186 enum dbg_rsc_type type;
187 struct dentry *root;
188 struct mlx5_field_desc fields[0];
189 };
190
191 enum mlx5_dev_event {
192 MLX5_DEV_EVENT_SYS_ERROR,
193 MLX5_DEV_EVENT_PORT_UP,
194 MLX5_DEV_EVENT_PORT_DOWN,
195 MLX5_DEV_EVENT_PORT_INITIALIZED,
196 MLX5_DEV_EVENT_LID_CHANGE,
197 MLX5_DEV_EVENT_PKEY_CHANGE,
198 MLX5_DEV_EVENT_GUID_CHANGE,
199 MLX5_DEV_EVENT_CLIENT_REREG,
200 MLX5_DEV_EVENT_VPORT_CHANGE,
201 MLX5_DEV_EVENT_ERROR_STATE_DCBX,
202 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
203 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
204 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
205 };
206
207 enum mlx5_port_status {
208 MLX5_PORT_UP = 1 << 0,
209 MLX5_PORT_DOWN = 1 << 1,
210 };
211
212 enum {
213 MLX5_VSC_SPACE_SUPPORTED = 0x1,
214 MLX5_VSC_SPACE_OFFSET = 0x4,
215 MLX5_VSC_COUNTER_OFFSET = 0x8,
216 MLX5_VSC_SEMA_OFFSET = 0xC,
217 MLX5_VSC_ADDR_OFFSET = 0x10,
218 MLX5_VSC_DATA_OFFSET = 0x14,
219 MLX5_VSC_MAX_RETRIES = 0x1000,
220 };
221
222 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
223
224 struct mlx5_cmd_first {
225 __be32 data[4];
226 };
227
228 struct cache_ent;
229 struct mlx5_fw_page {
230 union {
231 struct rb_node rb_node;
232 struct list_head list;
233 };
234 struct mlx5_cmd_first first;
235 struct mlx5_core_dev *dev;
236 bus_dmamap_t dma_map;
237 bus_addr_t dma_addr;
238 void *virt_addr;
239 struct cache_ent *cache;
240 u32 numpages;
241 u16 load_done;
242 #define MLX5_LOAD_ST_NONE 0
243 #define MLX5_LOAD_ST_SUCCESS 1
244 #define MLX5_LOAD_ST_FAILURE 2
245 u16 func_id;
246 };
247 #define mlx5_cmd_msg mlx5_fw_page
248
249 struct mlx5_cmd_debug {
250 struct dentry *dbg_root;
251 struct dentry *dbg_in;
252 struct dentry *dbg_out;
253 struct dentry *dbg_outlen;
254 struct dentry *dbg_status;
255 struct dentry *dbg_run;
256 void *in_msg;
257 void *out_msg;
258 u8 status;
259 u16 inlen;
260 u16 outlen;
261 };
262
263 struct cache_ent {
264 /* protect block chain allocations
265 */
266 spinlock_t lock;
267 struct list_head head;
268 };
269
270 struct cmd_msg_cache {
271 struct cache_ent large;
272 struct cache_ent med;
273
274 };
275
276 struct mlx5_traffic_counter {
277 u64 packets;
278 u64 octets;
279 };
280
281 enum mlx5_cmd_mode {
282 MLX5_CMD_MODE_POLLING,
283 MLX5_CMD_MODE_EVENTS
284 };
285
286 struct mlx5_cmd_stats {
287 u64 sum;
288 u64 n;
289 struct dentry *root;
290 struct dentry *avg;
291 struct dentry *count;
292 /* protect command average calculations */
293 spinlock_t lock;
294 };
295
296 struct mlx5_cmd {
297 struct mlx5_fw_page *cmd_page;
298 bus_dma_tag_t dma_tag;
299 struct sx dma_sx;
300 struct mtx dma_mtx;
301 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
302 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
303 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
304 struct cv dma_cv;
305 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
306 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
307 void *cmd_buf;
308 dma_addr_t dma;
309 u16 cmdif_rev;
310 u8 log_sz;
311 u8 log_stride;
312 int max_reg_cmds;
313 int events;
314 u32 __iomem *vector;
315
316 /* protect command queue allocations
317 */
318 spinlock_t alloc_lock;
319
320 /* protect token allocations
321 */
322 spinlock_t token_lock;
323 u8 token;
324 unsigned long bitmask;
325 struct semaphore sem;
326 struct semaphore pages_sem;
327 enum mlx5_cmd_mode mode;
328 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
329 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
330 struct mlx5_cmd_debug dbg;
331 struct cmd_msg_cache cache;
332 int checksum_disabled;
333 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
334 };
335
336 struct mlx5_port_caps {
337 int gid_table_len;
338 int pkey_table_len;
339 u8 ext_port_cap;
340 };
341
342 struct mlx5_buf {
343 bus_dma_tag_t dma_tag;
344 bus_dmamap_t dma_map;
345 struct mlx5_core_dev *dev;
346 struct {
347 void *buf;
348 } direct;
349 u64 *page_list;
350 int npages;
351 int size;
352 u8 page_shift;
353 u8 load_done;
354 };
355
356 struct mlx5_frag_buf {
357 struct mlx5_buf_list *frags;
358 int npages;
359 int size;
360 u8 page_shift;
361 };
362
363 struct mlx5_eq {
364 struct mlx5_core_dev *dev;
365 __be32 __iomem *doorbell;
366 u32 cons_index;
367 struct mlx5_buf buf;
368 int size;
369 u8 irqn;
370 u8 eqn;
371 int nent;
372 u64 mask;
373 struct list_head list;
374 int index;
375 struct mlx5_rsc_debug *dbg;
376 };
377
378 struct mlx5_core_psv {
379 u32 psv_idx;
380 struct psv_layout {
381 u32 pd;
382 u16 syndrome;
383 u16 reserved;
384 u16 bg;
385 u16 app_tag;
386 u32 ref_tag;
387 } psv;
388 };
389
390 struct mlx5_core_sig_ctx {
391 struct mlx5_core_psv psv_memory;
392 struct mlx5_core_psv psv_wire;
393 struct ib_sig_err err_item;
394 bool sig_status_checked;
395 bool sig_err_exists;
396 u32 sigerr_count;
397 };
398
399 enum {
400 MLX5_MKEY_MR = 1,
401 MLX5_MKEY_MW,
402 MLX5_MKEY_MR_USER,
403 };
404
405 struct mlx5_core_mkey {
406 u64 iova;
407 u64 size;
408 u32 key;
409 u32 pd;
410 u32 type;
411 };
412
413 struct mlx5_core_mr {
414 u64 iova;
415 u64 size;
416 u32 key;
417 u32 pd;
418 };
419
420 enum mlx5_res_type {
421 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
422 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
423 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
424 MLX5_RES_SRQ = 3,
425 MLX5_RES_XSRQ = 4,
426 MLX5_RES_DCT = 5,
427 };
428
429 struct mlx5_core_rsc_common {
430 enum mlx5_res_type res;
431 atomic_t refcount;
432 struct completion free;
433 };
434
435 struct mlx5_uars_page {
436 void __iomem *map;
437 bool wc;
438 u32 index;
439 struct list_head list;
440 unsigned int bfregs;
441 unsigned long *reg_bitmap; /* for non fast path bf regs */
442 unsigned long *fp_bitmap;
443 unsigned int reg_avail;
444 unsigned int fp_avail;
445 struct kref ref_count;
446 struct mlx5_core_dev *mdev;
447 };
448
449 struct mlx5_bfreg_head {
450 /* protect blue flame registers allocations */
451 struct mutex lock;
452 struct list_head list;
453 };
454
455 struct mlx5_bfreg_data {
456 struct mlx5_bfreg_head reg_head;
457 struct mlx5_bfreg_head wc_head;
458 };
459
460 struct mlx5_sq_bfreg {
461 void __iomem *map;
462 struct mlx5_uars_page *up;
463 bool wc;
464 u32 index;
465 unsigned int offset;
466 };
467
468 struct mlx5_core_srq {
469 struct mlx5_core_rsc_common common; /* must be first */
470 u32 srqn;
471 int max;
472 size_t max_gs;
473 size_t max_avail_gather;
474 int wqe_shift;
475 void (*event)(struct mlx5_core_srq *, int);
476 atomic_t refcount;
477 struct completion free;
478 };
479
480 struct mlx5_eq_table {
481 void __iomem *update_ci;
482 void __iomem *update_arm_ci;
483 struct list_head comp_eqs_list;
484 struct mlx5_eq pages_eq;
485 struct mlx5_eq async_eq;
486 struct mlx5_eq cmd_eq;
487 int num_comp_vectors;
488 /* protect EQs list
489 */
490 spinlock_t lock;
491 };
492
493 struct mlx5_core_health {
494 struct mlx5_health_buffer __iomem *health;
495 __be32 __iomem *health_counter;
496 struct timer_list timer;
497 u32 prev;
498 int miss_counter;
499 u32 fatal_error;
500 struct workqueue_struct *wq_watchdog;
501 struct work_struct work_watchdog;
502 /* wq spinlock to synchronize draining */
503 spinlock_t wq_lock;
504 struct workqueue_struct *wq;
505 unsigned long flags;
506 struct work_struct work;
507 struct delayed_work recover_work;
508 unsigned int last_reset_req;
509 struct work_struct work_cmd_completion;
510 struct workqueue_struct *wq_cmd;
511 };
512
513 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024
514
515 struct mlx5_cq_linear_array_entry {
516 struct mlx5_core_cq * volatile cq;
517 };
518
519 struct mlx5_cq_table {
520 /* protect radix tree
521 */
522 spinlock_t writerlock;
523 atomic_t writercount;
524 struct radix_tree_root tree;
525 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
526 };
527
528 struct mlx5_qp_table {
529 /* protect radix tree
530 */
531 spinlock_t lock;
532 struct radix_tree_root tree;
533 };
534
535 struct mlx5_srq_table {
536 /* protect radix tree
537 */
538 spinlock_t lock;
539 struct radix_tree_root tree;
540 };
541
542 struct mlx5_mr_table {
543 /* protect radix tree
544 */
545 spinlock_t lock;
546 struct radix_tree_root tree;
547 };
548
549 #ifdef RATELIMIT
550 struct mlx5_rl_entry {
551 u32 rate;
552 u16 burst;
553 u16 index;
554 u32 qos_handle; /* schedule queue handle */
555 u32 refcount;
556 };
557
558 struct mlx5_rl_table {
559 struct mutex rl_lock;
560 u16 max_size;
561 u32 max_rate;
562 u32 min_rate;
563 struct mlx5_rl_entry *rl_entry;
564 };
565 #endif
566
567 struct mlx5_pme_stats {
568 u64 status_counters[MLX5_MODULE_STATUS_NUM];
569 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
570 };
571
572 struct mlx5_priv {
573 char name[MLX5_MAX_NAME_LEN];
574 struct mlx5_eq_table eq_table;
575 struct msix_entry *msix_arr;
576 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
577 int disable_irqs;
578
579 /* pages stuff */
580 struct workqueue_struct *pg_wq;
581 struct rb_root page_root;
582 s64 fw_pages;
583 atomic_t reg_pages;
584 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
585 struct mlx5_core_health health;
586
587 struct mlx5_srq_table srq_table;
588
589 /* start: qp staff */
590 struct mlx5_qp_table qp_table;
591 struct dentry *qp_debugfs;
592 struct dentry *eq_debugfs;
593 struct dentry *cq_debugfs;
594 struct dentry *cmdif_debugfs;
595 /* end: qp staff */
596
597 /* start: cq staff */
598 struct mlx5_cq_table cq_table;
599 /* end: cq staff */
600
601 /* start: mr staff */
602 struct mlx5_mr_table mr_table;
603 /* end: mr staff */
604
605 /* start: alloc staff */
606 int numa_node;
607
608 struct mutex pgdir_mutex;
609 struct list_head pgdir_list;
610 /* end: alloc staff */
611 struct dentry *dbg_root;
612
613 /* protect mkey key part */
614 spinlock_t mkey_lock;
615 u8 mkey_key;
616
617 struct list_head dev_list;
618 struct list_head ctx_list;
619 spinlock_t ctx_lock;
620 unsigned long pci_dev_data;
621 #ifdef RATELIMIT
622 struct mlx5_rl_table rl_table;
623 #endif
624 struct mlx5_pme_stats pme_stats;
625
626 struct mlx5_eswitch *eswitch;
627
628 struct mlx5_bfreg_data bfregs;
629 struct mlx5_uars_page *uar;
630 };
631
632 enum mlx5_device_state {
633 MLX5_DEVICE_STATE_UP,
634 MLX5_DEVICE_STATE_INTERNAL_ERROR,
635 };
636
637 enum mlx5_interface_state {
638 MLX5_INTERFACE_STATE_UP = 0x1,
639 MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
640 };
641
642 enum mlx5_pci_status {
643 MLX5_PCI_STATUS_DISABLED,
644 MLX5_PCI_STATUS_ENABLED,
645 };
646
647 #define MLX5_MAX_RESERVED_GIDS 8
648
649 struct mlx5_rsvd_gids {
650 unsigned int start;
651 unsigned int count;
652 struct ida ida;
653 };
654
655 struct mlx5_special_contexts {
656 int resd_lkey;
657 };
658
659 struct mlx5_flow_root_namespace;
660 struct mlx5_core_dev {
661 struct pci_dev *pdev;
662 /* sync pci state */
663 struct mutex pci_status_mutex;
664 enum mlx5_pci_status pci_status;
665 char board_id[MLX5_BOARD_ID_LEN];
666 struct mlx5_cmd cmd;
667 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
668 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
669 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
670 struct {
671 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
672 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
673 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
674 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
675 } caps;
676 phys_addr_t iseg_base;
677 struct mlx5_init_seg __iomem *iseg;
678 enum mlx5_device_state state;
679 /* sync interface state */
680 struct mutex intf_state_mutex;
681 unsigned long intf_state;
682 void (*event) (struct mlx5_core_dev *dev,
683 enum mlx5_dev_event event,
684 unsigned long param);
685 struct mlx5_priv priv;
686 struct mlx5_profile *profile;
687 atomic_t num_qps;
688 u32 vsc_addr;
689 u32 issi;
690 struct mlx5_special_contexts special_contexts;
691 unsigned int module_status[MLX5_MAX_PORTS];
692 struct mlx5_flow_root_namespace *root_ns;
693 struct mlx5_flow_root_namespace *fdb_root_ns;
694 struct mlx5_flow_root_namespace *esw_egress_root_ns;
695 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
696 struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
697 struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
698 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
699 struct mlx5_crspace_regmap *dump_rege;
700 uint32_t *dump_data;
701 unsigned dump_size;
702 bool dump_valid;
703 bool dump_copyout;
704 struct mtx dump_lock;
705
706 struct sysctl_ctx_list sysctl_ctx;
707 int msix_eqvec;
708 int pwr_status;
709 int pwr_value;
710
711 struct {
712 struct mlx5_rsvd_gids reserved_gids;
713 atomic_t roce_en;
714 } roce;
715
716 struct {
717 spinlock_t spinlock;
718 #define MLX5_MPFS_TABLE_MAX 32
719 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
720 } mpfs;
721 #ifdef CONFIG_MLX5_FPGA
722 struct mlx5_fpga_device *fpga;
723 #endif
724 };
725
726 enum {
727 MLX5_WOL_DISABLE = 0,
728 MLX5_WOL_SECURED_MAGIC = 1 << 1,
729 MLX5_WOL_MAGIC = 1 << 2,
730 MLX5_WOL_ARP = 1 << 3,
731 MLX5_WOL_BROADCAST = 1 << 4,
732 MLX5_WOL_MULTICAST = 1 << 5,
733 MLX5_WOL_UNICAST = 1 << 6,
734 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
735 };
736
737 struct mlx5_db {
738 __be32 *db;
739 union {
740 struct mlx5_db_pgdir *pgdir;
741 struct mlx5_ib_user_db_page *user_page;
742 } u;
743 dma_addr_t dma;
744 int index;
745 };
746
747 struct mlx5_net_counters {
748 u64 packets;
749 u64 octets;
750 };
751
752 struct mlx5_ptys_reg {
753 u8 an_dis_admin;
754 u8 an_dis_ap;
755 u8 local_port;
756 u8 proto_mask;
757 u32 eth_proto_cap;
758 u16 ib_link_width_cap;
759 u16 ib_proto_cap;
760 u32 eth_proto_admin;
761 u16 ib_link_width_admin;
762 u16 ib_proto_admin;
763 u32 eth_proto_oper;
764 u16 ib_link_width_oper;
765 u16 ib_proto_oper;
766 u32 eth_proto_lp_advertise;
767 };
768
769 struct mlx5_pvlc_reg {
770 u8 local_port;
771 u8 vl_hw_cap;
772 u8 vl_admin;
773 u8 vl_operational;
774 };
775
776 struct mlx5_pmtu_reg {
777 u8 local_port;
778 u16 max_mtu;
779 u16 admin_mtu;
780 u16 oper_mtu;
781 };
782
783 struct mlx5_vport_counters {
784 struct mlx5_net_counters received_errors;
785 struct mlx5_net_counters transmit_errors;
786 struct mlx5_net_counters received_ib_unicast;
787 struct mlx5_net_counters transmitted_ib_unicast;
788 struct mlx5_net_counters received_ib_multicast;
789 struct mlx5_net_counters transmitted_ib_multicast;
790 struct mlx5_net_counters received_eth_broadcast;
791 struct mlx5_net_counters transmitted_eth_broadcast;
792 struct mlx5_net_counters received_eth_unicast;
793 struct mlx5_net_counters transmitted_eth_unicast;
794 struct mlx5_net_counters received_eth_multicast;
795 struct mlx5_net_counters transmitted_eth_multicast;
796 };
797
798 enum {
799 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
800 };
801
802 struct mlx5_core_dct {
803 struct mlx5_core_rsc_common common; /* must be first */
804 void (*event)(struct mlx5_core_dct *, int);
805 int dctn;
806 struct completion drained;
807 struct mlx5_rsc_debug *dbg;
808 int pid;
809 u16 uid;
810 };
811
812 enum {
813 MLX5_COMP_EQ_SIZE = 1024,
814 };
815
816 enum {
817 MLX5_PTYS_IB = 1 << 0,
818 MLX5_PTYS_EN = 1 << 2,
819 };
820
821 struct mlx5_db_pgdir {
822 struct list_head list;
823 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
824 struct mlx5_fw_page *fw_page;
825 __be32 *db_page;
826 dma_addr_t db_dma;
827 };
828
829 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
830
831 struct mlx5_cmd_work_ent {
832 struct mlx5_cmd_msg *in;
833 struct mlx5_cmd_msg *out;
834 int uin_size;
835 void *uout;
836 int uout_size;
837 mlx5_cmd_cbk_t callback;
838 struct delayed_work cb_timeout_work;
839 void *context;
840 int idx;
841 struct completion done;
842 struct mlx5_cmd *cmd;
843 struct work_struct work;
844 struct mlx5_cmd_layout *lay;
845 int ret;
846 int page_queue;
847 u8 status;
848 u8 token;
849 u64 ts1;
850 u64 ts2;
851 u16 op;
852 u8 busy;
853 bool polling;
854 };
855
856 struct mlx5_pas {
857 u64 pa;
858 u8 log_sz;
859 };
860
861 enum port_state_policy {
862 MLX5_POLICY_DOWN = 0,
863 MLX5_POLICY_UP = 1,
864 MLX5_POLICY_FOLLOW = 2,
865 MLX5_POLICY_INVALID = 0xffffffff
866 };
867
868 static inline void *
mlx5_buf_offset(struct mlx5_buf * buf,int offset)869 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
870 {
871 return ((char *)buf->direct.buf + offset);
872 }
873
874
875 extern struct workqueue_struct *mlx5_core_wq;
876
877 #define STRUCT_FIELD(header, field) \
878 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
879 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
880
pci2mlx5_core_dev(struct pci_dev * pdev)881 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
882 {
883 return pci_get_drvdata(pdev);
884 }
885
886 extern struct dentry *mlx5_debugfs_root;
887
fw_rev_maj(struct mlx5_core_dev * dev)888 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
889 {
890 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
891 }
892
fw_rev_min(struct mlx5_core_dev * dev)893 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
894 {
895 return ioread32be(&dev->iseg->fw_rev) >> 16;
896 }
897
fw_rev_sub(struct mlx5_core_dev * dev)898 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
899 {
900 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
901 }
902
cmdif_rev_get(struct mlx5_core_dev * dev)903 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
904 {
905 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
906 }
907
mlx5_get_gid_table_len(u16 param)908 static inline int mlx5_get_gid_table_len(u16 param)
909 {
910 if (param > 4) {
911 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
912 return 0;
913 }
914
915 return 8 * (1 << param);
916 }
917
mlx5_vzalloc(unsigned long size)918 static inline void *mlx5_vzalloc(unsigned long size)
919 {
920 void *rtn;
921
922 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
923 return rtn;
924 }
925
mlx5_vmalloc(unsigned long size)926 static inline void *mlx5_vmalloc(unsigned long size)
927 {
928 void *rtn;
929
930 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
931 if (!rtn)
932 rtn = vmalloc(size);
933 return rtn;
934 }
935
mlx5_base_mkey(const u32 key)936 static inline u32 mlx5_base_mkey(const u32 key)
937 {
938 return key & 0xffffff00u;
939 }
940
941 int mlx5_cmd_init(struct mlx5_core_dev *dev);
942 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
943 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
944 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
945 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
946 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
947
948 struct mlx5_async_ctx {
949 struct mlx5_core_dev *dev;
950 atomic_t num_inflight;
951 struct wait_queue_head wait;
952 };
953
954 struct mlx5_async_work;
955
956 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
957
958 struct mlx5_async_work {
959 struct mlx5_async_ctx *ctx;
960 mlx5_async_cbk_t user_callback;
961 };
962
963 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
964 struct mlx5_async_ctx *ctx);
965 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
966 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
967 void *out, int out_size, mlx5_async_cbk_t callback,
968 struct mlx5_async_work *work);
969 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
970 int out_size);
971 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
972 void *out, int out_size);
973 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
974 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
975 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
976 bool map_wc, bool fast_path);
977 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
978 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
979 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
980 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
981 int mlx5_health_init(struct mlx5_core_dev *dev);
982 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
983 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
984 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
985 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
986 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
987 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
988
989 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
990 struct mlx5_buf *buf);
991 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
992 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
993 struct mlx5_srq_attr *in);
994 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
995 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
996 struct mlx5_srq_attr *out);
997 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
998 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
999 u16 lwm, int is_srq);
1000 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
1001 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
1002 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1003 struct mlx5_core_mr *mkey,
1004 struct mlx5_async_ctx *async_ctx, u32 *in,
1005 int inlen, u32 *out, int outlen,
1006 mlx5_async_cbk_t callback,
1007 struct mlx5_async_work *context);
1008 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1009 struct mlx5_core_mr *mr,
1010 u32 *in, int inlen);
1011 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1012 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1013 u32 *out, int outlen);
1014 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1015 u32 *mkey);
1016 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1017 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1018 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1019 u16 opmod, u8 port);
1020 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1021 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1022 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1023 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1024 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1025 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1026 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1027 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1028 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1029 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1030 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1031 s32 npages);
1032 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1033 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1034 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1035 void mlx5_register_debugfs(void);
1036 void mlx5_unregister_debugfs(void);
1037 int mlx5_eq_init(struct mlx5_core_dev *dev);
1038 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1039 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1040 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1041 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1042 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1043 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1044 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1045 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1046 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1047 int nent, u64 mask);
1048 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1049 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1050 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1051 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1052 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1053 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1054 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1055 u64 addr);
1056
1057 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1058 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1059 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1060 int size_in, void *data_out, int size_out,
1061 u16 reg_num, int arg, int write);
1062
1063 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1064
1065 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1066 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1067 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1068 u32 *out, int outlen);
1069 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1070 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1071 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1072 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1073 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1074 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1075
1076 static inline struct domainset *
mlx5_dev_domainset(struct mlx5_core_dev * mdev)1077 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1078 {
1079 return (linux_get_vm_domain_set(mdev->priv.numa_node));
1080 }
1081
1082 const char *mlx5_command_str(int command);
1083 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1084 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1085 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1086 int npsvs, u32 *sig_index);
1087 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1088 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1089 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1090 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1091 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1092 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1093 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1094 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1095 struct mlx5_pvlc_reg *pvlc, int write);
1096 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1097 struct mlx5_ptys_reg *ptys, int write);
1098 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1099 struct mlx5_pmtu_reg *pmtu, int write);
1100 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1101 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1102 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1103 int priority, int *is_enable);
1104 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1105 int priority, int enable);
1106 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1107 void *out, int out_size);
1108 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1109 void *in, int in_size);
1110 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1111 void *out, int out_size);
1112 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1113 int in_size);
1114 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1115 u8 num_of_samples, u16 sample_index,
1116 void *out, int out_size);
1117 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1118 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1119 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1120 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1121 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1122 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1123 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1124 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1125 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1126 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1127 u16 *p_power, u8 *p_status);
1128
mlx5_mkey_to_idx(u32 mkey)1129 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1130 {
1131 return mkey >> 8;
1132 }
1133
mlx5_idx_to_mkey(u32 mkey_idx)1134 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1135 {
1136 return mkey_idx << 8;
1137 }
1138
mlx5_mkey_variant(u32 mkey)1139 static inline u8 mlx5_mkey_variant(u32 mkey)
1140 {
1141 return mkey & 0xff;
1142 }
1143
1144 enum {
1145 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1146 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1147 };
1148
1149 enum {
1150 MAX_MR_CACHE_ENTRIES = 15,
1151 };
1152
1153 struct mlx5_interface {
1154 void * (*add)(struct mlx5_core_dev *dev);
1155 void (*remove)(struct mlx5_core_dev *dev, void *context);
1156 void (*event)(struct mlx5_core_dev *dev, void *context,
1157 enum mlx5_dev_event event, unsigned long param);
1158 void * (*get_dev)(void *context);
1159 int protocol;
1160 struct list_head list;
1161 };
1162
1163 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1164 int mlx5_register_interface(struct mlx5_interface *intf);
1165 void mlx5_unregister_interface(struct mlx5_interface *intf);
1166
1167 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1168 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1169 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1170 const u8 *mac, bool vlan, u16 vlan_id);
1171
1172 struct mlx5_profile {
1173 u64 mask;
1174 u8 log_max_qp;
1175 struct {
1176 int size;
1177 int limit;
1178 } mr_cache[MAX_MR_CACHE_ENTRIES];
1179 };
1180
1181 enum {
1182 MLX5_PCI_DEV_IS_VF = 1 << 0,
1183 };
1184
1185 enum {
1186 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1187 };
1188
mlx5_core_is_pf(struct mlx5_core_dev * dev)1189 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1190 {
1191 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1192 }
1193 #ifdef RATELIMIT
1194 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1195 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1196 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1197 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1198 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1199 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle);
1200
mlx5_rl_get_scq_handle(struct mlx5_core_dev * dev,uint16_t index)1201 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index)
1202 {
1203 KASSERT(index > 0,
1204 ("invalid rate index for sq remap, failed retrieving SCQ handle"));
1205
1206 return (dev->priv.rl_table.rl_entry[index - 1].qos_handle);
1207 }
1208
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1209 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1210 {
1211 return !!(dev->priv.rl_table.max_size);
1212 }
1213 #endif
1214
1215 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1216 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1217
mlx5_get_qp_default_ts(struct mlx5_core_dev * dev)1218 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1219 {
1220 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1221 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1222 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1223 }
1224
mlx5_get_rq_default_ts(struct mlx5_core_dev * dev)1225 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1226 {
1227 return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1228 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1229 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1230 }
1231
mlx5_get_sq_default_ts(struct mlx5_core_dev * dev)1232 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1233 {
1234 return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1235 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1236 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1237 }
1238
1239 #endif /* MLX5_DRIVER_H */
1240