1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #ifndef MLX5_DEVICE_H
29 #define MLX5_DEVICE_H
30
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
34
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
37 #define FW_PRE_INIT_TIMEOUT_MILI 120000
38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72 /* insert a value to a struct */
73 #define MLX5_SET(typ, p, fld, v) do { \
74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80 } while (0)
81
82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
88 << __mlx5_dw_bit_off(typ, fld))); \
89 } while (0)
90
91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
93 __mlx5_mask(typ, fld))
94
95 #define MLX5_GET_PR(typ, p, fld) ({ \
96 u32 ___t = MLX5_GET(typ, p, fld); \
97 pr_debug(#fld " = 0x%x\n", ___t); \
98 ___t; \
99 })
100
101 #define __MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
104 } while (0)
105
106 #define MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld, v); \
109 } while (0)
110
111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld[idx], v); \
114 } while (0)
115
116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
117
118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
120 __mlx5_mask16(typ, fld))
121
122 #define MLX5_SET16(typ, p, fld, v) do { \
123 u16 _v = v; \
124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
128 << __mlx5_16_bit_off(typ, fld))); \
129 } while (0)
130
131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
132 __mlx5_64_off(typ, fld)))
133
134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
135 type_t tmp; \
136 switch (sizeof(tmp)) { \
137 case sizeof(u8): \
138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
139 break; \
140 case sizeof(u16): \
141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
142 break; \
143 case sizeof(u32): \
144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
145 break; \
146 case sizeof(u64): \
147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
148 break; \
149 } \
150 tmp; \
151 })
152
153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
159
160 /* insert a value to a struct */
161 #define MLX5_VSC_SET(typ, p, fld, v) do { \
162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
167 << __mlx5_dw_bit_off(typ, fld))); \
168 } while (0)
169
170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
172 __mlx5_mask(typ, fld))
173
174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
176 pr_debug(#fld " = 0x%x\n", ___t); \
177 ___t; \
178 })
179
180 enum {
181 MLX5_MAX_COMMANDS = 32,
182 MLX5_CMD_DATA_BLOCK_SIZE = 512,
183 MLX5_CMD_MBOX_SIZE = 1024,
184 MLX5_PCI_CMD_XPORT = 7,
185 MLX5_MKEY_BSF_OCTO_SIZE = 4,
186 MLX5_MAX_PSVS = 4,
187 };
188
189 enum {
190 MLX5_EXTENDED_UD_AV = 0x80000000,
191 };
192
193 enum {
194 MLX5_CQ_FLAGS_OI = 2,
195 };
196
197 enum {
198 MLX5_STAT_RATE_OFFSET = 5,
199 };
200
201 enum {
202 MLX5_INLINE_SEG = 0x80000000,
203 };
204
205 enum {
206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
207 };
208
209 enum {
210 MLX5_MIN_PKEY_TABLE_SIZE = 128,
211 MLX5_MAX_LOG_PKEY_TABLE = 5,
212 };
213
214 enum {
215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
216 };
217
218 enum {
219 MLX5_PERM_LOCAL_READ = 1 << 2,
220 MLX5_PERM_LOCAL_WRITE = 1 << 3,
221 MLX5_PERM_REMOTE_READ = 1 << 4,
222 MLX5_PERM_REMOTE_WRITE = 1 << 5,
223 MLX5_PERM_ATOMIC = 1 << 6,
224 MLX5_PERM_UMR_EN = 1 << 7,
225 };
226
227 enum {
228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
233 };
234
235 enum {
236 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
238 MLX5_MKEY_BSF_EN = 1 << 30,
239 MLX5_MKEY_LEN64 = 1U << 31,
240 };
241
242 enum {
243 MLX5_EN_RD = (u64)1,
244 MLX5_EN_WR = (u64)2
245 };
246
247 enum {
248 MLX5_ADAPTER_PAGE_SHIFT = 12,
249 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
250 };
251
252 enum {
253 MLX5_BFREGS_PER_UAR = 4,
254 MLX5_MAX_UARS = 1 << 8,
255 MLX5_NON_FP_BFREGS_PER_UAR = 2,
256 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
257 MLX5_NON_FP_BFREGS_PER_UAR,
258 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
259 MLX5_NON_FP_BFREGS_PER_UAR,
260 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
261 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
262 MLX5_MIN_DYN_BFREGS = 512,
263 MLX5_MAX_DYN_BFREGS = 1024,
264 };
265
266 enum {
267 MLX5_MKEY_MASK_LEN = 1ull << 0,
268 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
269 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
270 MLX5_MKEY_MASK_PD = 1ull << 7,
271 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
272 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
273 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
274 MLX5_MKEY_MASK_KEY = 1ull << 13,
275 MLX5_MKEY_MASK_QPN = 1ull << 14,
276 MLX5_MKEY_MASK_LR = 1ull << 17,
277 MLX5_MKEY_MASK_LW = 1ull << 18,
278 MLX5_MKEY_MASK_RR = 1ull << 19,
279 MLX5_MKEY_MASK_RW = 1ull << 20,
280 MLX5_MKEY_MASK_A = 1ull << 21,
281 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
282 MLX5_MKEY_MASK_FREE = 1ull << 29,
283 };
284
285 enum {
286 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
287
288 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
289 MLX5_UMR_CHECK_FREE = (2 << 5),
290
291 MLX5_UMR_INLINE = (1 << 7),
292 };
293
294 #define MLX5_UMR_MTT_ALIGNMENT 0x40
295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
296 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
297
298 enum {
299 MLX5_EVENT_QUEUE_TYPE_QP = 0,
300 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
301 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
302 };
303
304 enum {
305 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
306 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
307 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
308 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
309 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
310 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
311 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
312 };
313
314 enum {
315 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
316 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
317 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
318 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
319 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
320 };
321
322 enum {
323 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
324 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
325 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
326 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
327 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
328 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
329 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
330 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
331 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
332 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
333 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
334 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
335 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
336 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
337 };
338
339 enum {
340 MLX5_ROCE_VERSION_1 = 0,
341 MLX5_ROCE_VERSION_1_5 = 1,
342 MLX5_ROCE_VERSION_2 = 2,
343 };
344
345 enum {
346 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
347 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
348 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
349 };
350
351 enum {
352 MLX5_ROCE_L3_TYPE_IPV4 = 0,
353 MLX5_ROCE_L3_TYPE_IPV6 = 1,
354 };
355
356 enum {
357 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
358 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
359 };
360
361 enum {
362 MLX5_OPCODE_NOP = 0x00,
363 MLX5_OPCODE_SEND_INVAL = 0x01,
364 MLX5_OPCODE_RDMA_WRITE = 0x08,
365 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
366 MLX5_OPCODE_SEND = 0x0a,
367 MLX5_OPCODE_SEND_IMM = 0x0b,
368 MLX5_OPCODE_LSO = 0x0e,
369 MLX5_OPCODE_RDMA_READ = 0x10,
370 MLX5_OPCODE_ATOMIC_CS = 0x11,
371 MLX5_OPCODE_ATOMIC_FA = 0x12,
372 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
373 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
374 MLX5_OPCODE_BIND_MW = 0x18,
375 MLX5_OPCODE_CONFIG_CMD = 0x1f,
376 MLX5_OPCODE_DUMP = 0x23,
377
378 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
379 MLX5_RECV_OPCODE_SEND = 0x01,
380 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
381 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
382
383 MLX5_CQE_OPCODE_ERROR = 0x1e,
384 MLX5_CQE_OPCODE_RESIZE = 0x16,
385
386 MLX5_OPCODE_SET_PSV = 0x20,
387 MLX5_OPCODE_GET_PSV = 0x21,
388 MLX5_OPCODE_CHECK_PSV = 0x22,
389 MLX5_OPCODE_RGET_PSV = 0x26,
390 MLX5_OPCODE_RCHECK_PSV = 0x27,
391
392 MLX5_OPCODE_UMR = 0x25,
393 MLX5_OPCODE_QOS_REMAP = 0x2a,
394
395 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
396 };
397
398 enum {
399 MLX5_OPCODE_MOD_UMR_UMR = 0x0,
400 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1,
401 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2,
402 };
403
404 enum {
405 MLX5_OPCODE_MOD_PSV_PSV = 0x0,
406 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1,
407 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2,
408 };
409
410 enum {
411 MLX5_SET_PORT_RESET_QKEY = 0,
412 MLX5_SET_PORT_GUID0 = 16,
413 MLX5_SET_PORT_NODE_GUID = 17,
414 MLX5_SET_PORT_SYS_GUID = 18,
415 MLX5_SET_PORT_GID_TABLE = 19,
416 MLX5_SET_PORT_PKEY_TABLE = 20,
417 };
418
419 enum {
420 MLX5_MAX_PAGE_SHIFT = 31
421 };
422
423 enum {
424 MLX5_CAP_OFF_CMDIF_CSUM = 46,
425 };
426
427 enum {
428 /*
429 * Max wqe size for rdma read is 512 bytes, so this
430 * limits our max_sge_rd as the wqe needs to fit:
431 * - ctrl segment (16 bytes)
432 * - rdma segment (16 bytes)
433 * - scatter elements (16 bytes each)
434 */
435 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
436 };
437
438 struct mlx5_cmd_layout {
439 u8 type;
440 u8 rsvd0[3];
441 __be32 inlen;
442 __be64 in_ptr;
443 __be32 in[4];
444 __be32 out[4];
445 __be64 out_ptr;
446 __be32 outlen;
447 u8 token;
448 u8 sig;
449 u8 rsvd1;
450 u8 status_own;
451 };
452
453 enum mlx5_fatal_assert_bit_offsets {
454 MLX5_RFR_OFFSET = 31,
455 };
456
457 struct mlx5_health_buffer {
458 __be32 assert_var[5];
459 __be32 rsvd0[3];
460 __be32 assert_exit_ptr;
461 __be32 assert_callra;
462 __be32 rsvd1[2];
463 __be32 fw_ver;
464 __be32 hw_id;
465 __be32 rfr;
466 u8 irisc_index;
467 u8 synd;
468 __be16 ext_synd;
469 };
470
471 enum mlx5_initializing_bit_offsets {
472 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
473 };
474
475 enum mlx5_cmd_addr_l_sz_offset {
476 MLX5_NIC_IFC_OFFSET = 8,
477 };
478
479 struct mlx5_init_seg {
480 __be32 fw_rev;
481 __be32 cmdif_rev_fw_sub;
482 __be32 rsvd0[2];
483 __be32 cmdq_addr_h;
484 __be32 cmdq_addr_l_sz;
485 __be32 cmd_dbell;
486 __be32 rsvd1[120];
487 __be32 initializing;
488 struct mlx5_health_buffer health;
489 __be32 rsvd2[880];
490 __be32 internal_timer_h;
491 __be32 internal_timer_l;
492 __be32 rsvd3[2];
493 __be32 health_counter;
494 __be32 rsvd4[1019];
495 __be64 ieee1588_clk;
496 __be32 ieee1588_clk_type;
497 __be32 clr_intx;
498 };
499
500 struct mlx5_eqe_comp {
501 __be32 reserved[6];
502 __be32 cqn;
503 };
504
505 struct mlx5_eqe_qp_srq {
506 __be32 reserved[6];
507 __be32 qp_srq_n;
508 };
509
510 struct mlx5_eqe_cq_err {
511 __be32 cqn;
512 u8 reserved1[7];
513 u8 syndrome;
514 };
515
516 struct mlx5_eqe_port_state {
517 u8 reserved0[8];
518 u8 port;
519 };
520
521 struct mlx5_eqe_gpio {
522 __be32 reserved0[2];
523 __be64 gpio_event;
524 };
525
526 struct mlx5_eqe_congestion {
527 u8 type;
528 u8 rsvd0;
529 u8 congestion_level;
530 };
531
532 struct mlx5_eqe_stall_vl {
533 u8 rsvd0[3];
534 u8 port_vl;
535 };
536
537 struct mlx5_eqe_cmd {
538 __be32 vector;
539 __be32 rsvd[6];
540 };
541
542 struct mlx5_eqe_page_req {
543 u8 rsvd0[2];
544 __be16 func_id;
545 __be32 num_pages;
546 __be32 rsvd1[5];
547 };
548
549 struct mlx5_eqe_vport_change {
550 u8 rsvd0[2];
551 __be16 vport_num;
552 __be32 rsvd1[6];
553 };
554
555
556 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
557 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
558
559 enum {
560 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
561 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
562 MLX5_MODULE_STATUS_ERROR = 0x3,
563 MLX5_MODULE_STATUS_NUM ,
564 };
565
566 enum {
567 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
568 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
569 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
570 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
571 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
572 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
573 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
574 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
575 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8,
576 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9,
577 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa,
578 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb,
579 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc,
580 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd,
581 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe,
582 MLX5_MODULE_EVENT_ERROR_NUM ,
583 };
584
585 struct mlx5_eqe_port_module_event {
586 u8 rsvd0;
587 u8 module;
588 u8 rsvd1;
589 u8 module_status;
590 u8 rsvd2[2];
591 u8 error_type;
592 };
593
594 struct mlx5_eqe_general_notification_event {
595 u32 rq_user_index_delay_drop;
596 u32 rsvd0[6];
597 };
598
599 struct mlx5_eqe_temp_warning {
600 __be64 sensor_warning_msb;
601 __be64 sensor_warning_lsb;
602 } __packed;
603
604 union ev_data {
605 __be32 raw[7];
606 struct mlx5_eqe_cmd cmd;
607 struct mlx5_eqe_comp comp;
608 struct mlx5_eqe_qp_srq qp_srq;
609 struct mlx5_eqe_cq_err cq_err;
610 struct mlx5_eqe_port_state port;
611 struct mlx5_eqe_gpio gpio;
612 struct mlx5_eqe_congestion cong;
613 struct mlx5_eqe_stall_vl stall_vl;
614 struct mlx5_eqe_page_req req_pages;
615 struct mlx5_eqe_port_module_event port_module_event;
616 struct mlx5_eqe_vport_change vport_change;
617 struct mlx5_eqe_general_notification_event general_notifications;
618 struct mlx5_eqe_temp_warning temp_warning;
619 } __packed;
620
621 struct mlx5_eqe {
622 u8 rsvd0;
623 u8 type;
624 u8 rsvd1;
625 u8 sub_type;
626 __be32 rsvd2[7];
627 union ev_data data;
628 __be16 rsvd3;
629 u8 signature;
630 u8 owner;
631 } __packed;
632
633 struct mlx5_cmd_prot_block {
634 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
635 u8 rsvd0[48];
636 __be64 next;
637 __be32 block_num;
638 u8 rsvd1;
639 u8 token;
640 u8 ctrl_sig;
641 u8 sig;
642 };
643
644 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
645 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
646 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
647 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
648
649 enum {
650 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
651 };
652
653 struct mlx5_err_cqe {
654 u8 rsvd0[32];
655 __be32 srqn;
656 u8 rsvd1[18];
657 u8 vendor_err_synd;
658 u8 syndrome;
659 __be32 s_wqe_opcode_qpn;
660 __be16 wqe_counter;
661 u8 signature;
662 u8 op_own;
663 };
664
665 struct mlx5_cqe64 {
666 u8 tls_outer_l3_tunneled;
667 u8 rsvd0;
668 __be16 wqe_id;
669 u8 lro_tcppsh_abort_dupack;
670 u8 lro_min_ttl;
671 __be16 lro_tcp_win;
672 __be32 lro_ack_seq_num;
673 __be32 rss_hash_result;
674 u8 rss_hash_type;
675 u8 ml_path;
676 u8 rsvd20[2];
677 __be16 check_sum;
678 __be16 slid;
679 __be32 flags_rqpn;
680 u8 hds_ip_ext;
681 u8 l4_hdr_type_etc;
682 __be16 vlan_info;
683 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
684 __be32 imm_inval_pkey;
685 u8 rsvd40[4];
686 __be32 byte_cnt;
687 __be64 timestamp;
688 __be32 sop_drop_qpn;
689 __be16 wqe_counter;
690 u8 signature;
691 u8 op_own;
692 };
693
694 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
695
get_cqe_opcode(struct mlx5_cqe64 * cqe)696 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
697 {
698 return (cqe->op_own >> 4);
699 }
700
get_cqe_lro_timestamp_valid(struct mlx5_cqe64 * cqe)701 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
702 {
703 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
704 }
705
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)706 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
707 {
708 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
709 }
710
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)711 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
712 {
713 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
714 }
715
get_cqe_vlan(struct mlx5_cqe64 * cqe)716 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
717 {
718 return be16_to_cpu(cqe->vlan_info) & 0xfff;
719 }
720
get_cqe_smac(struct mlx5_cqe64 * cqe,u8 * smac)721 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
722 {
723 memcpy(smac, &cqe->rss_hash_type , 4);
724 memcpy(smac + 4, &cqe->slid , 2);
725 }
726
cqe_has_vlan(struct mlx5_cqe64 * cqe)727 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
728 {
729 return cqe->l4_hdr_type_etc & 0x1;
730 }
731
cqe_is_tunneled(struct mlx5_cqe64 * cqe)732 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
733 {
734 return cqe->tls_outer_l3_tunneled & 0x1;
735 }
736
737 enum {
738 CQE_L4_HDR_TYPE_NONE = 0x0,
739 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
740 CQE_L4_HDR_TYPE_UDP = 0x2,
741 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
742 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
743 };
744
745 enum {
746 /* source L3 hash types */
747 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
748 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
749 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
750
751 /* destination L3 hash types */
752 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
753 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
754 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
755
756 /* source L4 hash types */
757 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
758 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
759 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
760 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
761
762 /* destination L4 hash types */
763 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
764 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
765 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
766 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
767 };
768
769 enum {
770 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
771 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
772 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
773 };
774
775 enum {
776 CQE_L2_OK = 1 << 0,
777 CQE_L3_OK = 1 << 1,
778 CQE_L4_OK = 1 << 2,
779 };
780
781 struct mlx5_sig_err_cqe {
782 u8 rsvd0[16];
783 __be32 expected_trans_sig;
784 __be32 actual_trans_sig;
785 __be32 expected_reftag;
786 __be32 actual_reftag;
787 __be16 syndrome;
788 u8 rsvd22[2];
789 __be32 mkey;
790 __be64 err_offset;
791 u8 rsvd30[8];
792 __be32 qpn;
793 u8 rsvd38[2];
794 u8 signature;
795 u8 op_own;
796 };
797
798 struct mlx5_wqe_srq_next_seg {
799 u8 rsvd0[2];
800 __be16 next_wqe_index;
801 u8 signature;
802 u8 rsvd1[11];
803 };
804
805 union mlx5_ext_cqe {
806 struct ib_grh grh;
807 u8 inl[64];
808 };
809
810 struct mlx5_cqe128 {
811 union mlx5_ext_cqe inl_grh;
812 struct mlx5_cqe64 cqe64;
813 };
814
815 enum {
816 MLX5_MKEY_STATUS_FREE = 1 << 6,
817 };
818
819 struct mlx5_mkey_seg {
820 /* This is a two bit field occupying bits 31-30.
821 * bit 31 is always 0,
822 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
823 */
824 u8 status;
825 u8 pcie_control;
826 u8 flags;
827 u8 version;
828 __be32 qpn_mkey7_0;
829 u8 rsvd1[4];
830 __be32 flags_pd;
831 __be64 start_addr;
832 __be64 len;
833 __be32 bsfs_octo_size;
834 u8 rsvd2[16];
835 __be32 xlt_oct_size;
836 u8 rsvd3[3];
837 u8 log2_page_size;
838 u8 rsvd4[4];
839 };
840
841 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
842
843 enum {
844 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
845 };
846
mlx5_host_is_le(void)847 static inline int mlx5_host_is_le(void)
848 {
849 #if defined(__LITTLE_ENDIAN)
850 return 1;
851 #elif defined(__BIG_ENDIAN)
852 return 0;
853 #else
854 #error Host endianness not defined
855 #endif
856 }
857
858 #define MLX5_CMD_OP_MAX 0x939
859
860 enum {
861 VPORT_STATE_DOWN = 0x0,
862 VPORT_STATE_UP = 0x1,
863 VPORT_STATE_FOLLOW = 0x2,
864 };
865
866 enum {
867 MLX5_L3_PROT_TYPE_IPV4 = 0,
868 MLX5_L3_PROT_TYPE_IPV6 = 1,
869 };
870
871 enum {
872 MLX5_L4_PROT_TYPE_TCP = 0,
873 MLX5_L4_PROT_TYPE_UDP = 1,
874 };
875
876 enum {
877 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
878 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
879 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
880 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
881 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
882 };
883
884 enum {
885 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
886 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
887 MLX5_MATCH_INNER_HEADERS = 1 << 2,
888
889 };
890
891 enum {
892 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
893 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
894 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
895 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
896 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
897 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
898 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
899 };
900
901 enum {
902 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
903 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
904 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
905 };
906
907 enum {
908 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
909 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
910 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
911 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
912 };
913
914 enum {
915 MLX5_UC_ADDR_CHANGE = (1 << 0),
916 MLX5_MC_ADDR_CHANGE = (1 << 1),
917 MLX5_VLAN_CHANGE = (1 << 2),
918 MLX5_PROMISC_CHANGE = (1 << 3),
919 MLX5_MTU_CHANGE = (1 << 4),
920 };
921
922 enum mlx5_list_type {
923 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
924 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
925 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
926 };
927
928 enum {
929 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
930 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
931 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
932 };
933
934 /* MLX5 DEV CAPs */
935
936 /* TODO: EAT.ME */
937 enum mlx5_cap_mode {
938 HCA_CAP_OPMOD_GET_MAX = 0,
939 HCA_CAP_OPMOD_GET_CUR = 1,
940 };
941
942 enum mlx5_cap_type {
943 MLX5_CAP_GENERAL = 0,
944 MLX5_CAP_ETHERNET_OFFLOADS,
945 MLX5_CAP_ODP,
946 MLX5_CAP_ATOMIC,
947 MLX5_CAP_ROCE,
948 MLX5_CAP_IPOIB_OFFLOADS,
949 MLX5_CAP_EOIB_OFFLOADS,
950 MLX5_CAP_FLOW_TABLE,
951 MLX5_CAP_ESWITCH_FLOW_TABLE,
952 MLX5_CAP_ESWITCH,
953 MLX5_CAP_SNAPSHOT,
954 MLX5_CAP_VECTOR_CALC,
955 MLX5_CAP_QOS,
956 MLX5_CAP_DEBUG,
957 MLX5_CAP_NVME,
958 MLX5_CAP_DMC,
959 MLX5_CAP_DEC,
960 MLX5_CAP_TLS,
961 /* NUM OF CAP Types */
962 MLX5_CAP_NUM
963 };
964
965 enum mlx5_qcam_reg_groups {
966 MLX5_QCAM_REGS_FIRST_128 = 0x0,
967 };
968
969 enum mlx5_qcam_feature_groups {
970 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
971 };
972
973 enum mlx5_pcam_reg_groups {
974 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
975 };
976
977 enum mlx5_pcam_feature_groups {
978 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
979 };
980
981 enum mlx5_mcam_reg_groups {
982 MLX5_MCAM_REGS_FIRST_128 = 0x0,
983 };
984
985 enum mlx5_mcam_feature_groups {
986 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
987 };
988
989 /* GET Dev Caps macros */
990 #define MLX5_CAP_GEN(mdev, cap) \
991 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
992
993 #define MLX5_CAP_GEN_64(mdev, cap) \
994 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
995
996 #define MLX5_CAP_GEN_MAX(mdev, cap) \
997 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
998
999 #define MLX5_CAP_ETH(mdev, cap) \
1000 MLX5_GET(per_protocol_networking_offload_caps,\
1001 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1002
1003 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1004 MLX5_GET(per_protocol_networking_offload_caps,\
1005 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1006
1007 #define MLX5_CAP_ROCE(mdev, cap) \
1008 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1009
1010 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1011 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1012
1013 #define MLX5_CAP_ATOMIC(mdev, cap) \
1014 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1015
1016 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1017 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1018
1019 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1020 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1021
1022 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1023 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1024
1025 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1026 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1027
1028 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1029 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1030
1031 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1032 MLX5_GET(flow_table_eswitch_cap, \
1033 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1034
1035 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1036 MLX5_GET(flow_table_eswitch_cap, \
1037 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1038
1039 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1040 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1041
1042 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1043 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1044
1045 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1046 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1047
1048 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1049 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1050
1051 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1052 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1053
1054 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1055 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1056
1057 #define MLX5_CAP_ESW(mdev, cap) \
1058 MLX5_GET(e_switch_cap, \
1059 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1060
1061 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1062 MLX5_GET(e_switch_cap, \
1063 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1064
1065 #define MLX5_CAP_ODP(mdev, cap)\
1066 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1067
1068 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1069 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1070
1071 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1072 MLX5_GET(snapshot_cap, \
1073 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1074
1075 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1076 MLX5_GET(snapshot_cap, \
1077 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1078
1079 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1080 MLX5_GET(per_protocol_networking_offload_caps,\
1081 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1082
1083 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1084 MLX5_GET(per_protocol_networking_offload_caps,\
1085 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1086
1087 #define MLX5_CAP_DEBUG(mdev, cap) \
1088 MLX5_GET(debug_cap, \
1089 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1090
1091 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1092 MLX5_GET(debug_cap, \
1093 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1094
1095 #define MLX5_CAP_QOS(mdev, cap) \
1096 MLX5_GET(qos_cap,\
1097 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1098
1099 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1100 MLX5_GET(qos_cap,\
1101 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1102
1103 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1104 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1105
1106 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1107 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1108
1109 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1110 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1111
1112 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1113 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1114
1115 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1116 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1117
1118 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1119 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1120
1121 #define MLX5_CAP_FPGA(mdev, cap) \
1122 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1123
1124 #define MLX5_CAP64_FPGA(mdev, cap) \
1125 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1126
1127 #define MLX5_CAP_TLS(mdev, cap) \
1128 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1129
1130 enum {
1131 MLX5_CMD_STAT_OK = 0x0,
1132 MLX5_CMD_STAT_INT_ERR = 0x1,
1133 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1134 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1135 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1136 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1137 MLX5_CMD_STAT_RES_BUSY = 0x6,
1138 MLX5_CMD_STAT_LIM_ERR = 0x8,
1139 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1140 MLX5_CMD_STAT_IX_ERR = 0xa,
1141 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1142 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1143 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1144 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1145 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1146 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1147 };
1148
1149 enum {
1150 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1151 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1152 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1153 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1154 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1155 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1156 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1157 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1158 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1159 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1160 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1161 };
1162
1163 enum {
1164 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1165 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1166 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1167 };
1168
1169 enum {
1170 MLX5_CAP_PORT_TYPE_IB = 0x0,
1171 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1172 };
1173
1174 enum {
1175 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1176 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1177 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1178 };
1179
1180 enum mlx5_inline_modes {
1181 MLX5_INLINE_MODE_NONE,
1182 MLX5_INLINE_MODE_L2,
1183 MLX5_INLINE_MODE_IP,
1184 MLX5_INLINE_MODE_TCP_UDP,
1185 };
1186
1187 enum {
1188 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1189 };
1190
mlx5_to_sw_pkey_sz(int pkey_sz)1191 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1192 {
1193 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1194 return 0;
1195 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1196 }
1197
1198 struct mlx5_ifc_mcia_reg_bits {
1199 u8 l[0x1];
1200 u8 reserved_0[0x7];
1201 u8 module[0x8];
1202 u8 reserved_1[0x8];
1203 u8 status[0x8];
1204
1205 u8 i2c_device_address[0x8];
1206 u8 page_number[0x8];
1207 u8 device_address[0x10];
1208
1209 u8 reserved_2[0x10];
1210 u8 size[0x10];
1211
1212 u8 reserved_3[0x20];
1213
1214 u8 dword_0[0x20];
1215 u8 dword_1[0x20];
1216 u8 dword_2[0x20];
1217 u8 dword_3[0x20];
1218 u8 dword_4[0x20];
1219 u8 dword_5[0x20];
1220 u8 dword_6[0x20];
1221 u8 dword_7[0x20];
1222 u8 dword_8[0x20];
1223 u8 dword_9[0x20];
1224 u8 dword_10[0x20];
1225 u8 dword_11[0x20];
1226 };
1227
1228 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1229
1230 struct mlx5_mini_cqe8 {
1231 union {
1232 __be32 rx_hash_result;
1233 __be16 checksum;
1234 __be16 rsvd;
1235 struct {
1236 __be16 wqe_counter;
1237 u8 s_wqe_opcode;
1238 u8 reserved;
1239 } s_wqe_info;
1240 };
1241 __be32 byte_cnt;
1242 };
1243
1244 enum {
1245 MLX5_NO_INLINE_DATA,
1246 MLX5_INLINE_DATA32_SEG,
1247 MLX5_INLINE_DATA64_SEG,
1248 MLX5_COMPRESSED,
1249 };
1250
1251 enum mlx5_exp_cqe_zip_recv_type {
1252 MLX5_CQE_FORMAT_HASH,
1253 MLX5_CQE_FORMAT_CSUM,
1254 };
1255
1256 #define MLX5E_CQE_FORMAT_MASK 0xc
mlx5_get_cqe_format(const struct mlx5_cqe64 * cqe)1257 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1258 {
1259 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1260 }
1261
1262 enum {
1263 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1264 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
1265 };
1266
1267 enum {
1268 MLX5_FRL_LEVEL3 = 0x8,
1269 MLX5_FRL_LEVEL6 = 0x40,
1270 };
1271
1272 /* 8 regular priorities + 1 for multicast */
1273 #define MLX5_NUM_BYPASS_FTS 9
1274
1275 #endif /* MLX5_DEVICE_H */
1276