1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2021, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*$FreeBSD$*/
32
33 #ifndef _ICE_TYPE_H_
34 #define _ICE_TYPE_H_
35
36 #define ETH_ALEN 6
37
38 #define ETH_HEADER_LEN 14
39
40 #define BIT(a) (1UL << (a))
41 #ifndef BIT_ULL
42 #define BIT_ULL(a) (1ULL << (a))
43 #endif /* BIT_ULL */
44
45 #define BITS_PER_BYTE 8
46
47 #define _FORCE_
48
49 #define ICE_BYTES_PER_WORD 2
50 #define ICE_BYTES_PER_DWORD 4
51 #define ICE_MAX_TRAFFIC_CLASS 8
52
53 #ifndef MIN_T
54 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
55 #endif
56
57 #define IS_ASCII(_ch) ((_ch) < 0x80)
58
59 #define STRUCT_HACK_VAR_LEN
60 /**
61 * ice_struct_size - size of struct with C99 flexible array member
62 * @ptr: pointer to structure
63 * @field: flexible array member (last member of the structure)
64 * @num: number of elements of that flexible array member
65 */
66 #define ice_struct_size(ptr, field, num) \
67 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
68
69 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
70
71 #include "ice_status.h"
72 #include "ice_hw_autogen.h"
73 #include "ice_devids.h"
74 #include "ice_osdep.h"
75 #include "ice_bitops.h" /* Must come before ice_controlq.h */
76 #include "ice_controlq.h"
77 #include "ice_lan_tx_rx.h"
78 #include "ice_flex_type.h"
79 #include "ice_protocol_type.h"
80 #include "ice_vlan_mode.h"
81 #include "ice_fwlog.h"
82
ice_is_tc_ena(ice_bitmap_t bitmap,u8 tc)83 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
84 {
85 return !!(bitmap & BIT(tc));
86 }
87
88 /**
89 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor
90 * @dividend: value to divide
91 * @divisor: value to divide by
92 *
93 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends.
94 * Do not use this for unsigned 64-bit dividends as it will not produce
95 * correct results if the dividend is larger than S64_MAX.
96 */
DIV_S64(s64 dividend,s64 divisor)97 static inline s64 DIV_S64(s64 dividend, s64 divisor)
98 {
99 return dividend / divisor;
100 }
101
102 /**
103 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor
104 * @dividend: value to divide
105 * @divisor: value to divide by
106 *
107 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit
108 * dividends. Do not use this for signed 64-bit dividends as it will not
109 * handle negative values correctly.
110 */
DIV_U64(u64 dividend,u64 divisor)111 static inline u64 DIV_U64(u64 dividend, u64 divisor)
112 {
113 return dividend / divisor;
114 }
115
round_up_64bit(u64 a,u32 b)116 static inline u64 round_up_64bit(u64 a, u32 b)
117 {
118 return DIV_U64(((a) + (b) / 2), (b));
119 }
120
ice_round_to_num(u32 N,u32 R)121 static inline u32 ice_round_to_num(u32 N, u32 R)
122 {
123 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
124 ((((N) + (R) - 1) / (R)) * (R)));
125 }
126
127 /* Driver always calls main vsi_handle first */
128 #define ICE_MAIN_VSI_HANDLE 0
129
130 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
131 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
132
133 /* Data type manipulation macros. */
134 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
135 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
136 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
137 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
138
139 /* debug masks - set these bits in hw->debug_mask to control output */
140 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
141 #define ICE_DBG_INIT BIT_ULL(1)
142 #define ICE_DBG_RELEASE BIT_ULL(2)
143 #define ICE_DBG_FW_LOG BIT_ULL(3)
144 #define ICE_DBG_LINK BIT_ULL(4)
145 #define ICE_DBG_PHY BIT_ULL(5)
146 #define ICE_DBG_QCTX BIT_ULL(6)
147 #define ICE_DBG_NVM BIT_ULL(7)
148 #define ICE_DBG_LAN BIT_ULL(8)
149 #define ICE_DBG_FLOW BIT_ULL(9)
150 #define ICE_DBG_DCB BIT_ULL(10)
151 #define ICE_DBG_DIAG BIT_ULL(11)
152 #define ICE_DBG_FD BIT_ULL(12)
153 #define ICE_DBG_SW BIT_ULL(13)
154 #define ICE_DBG_SCHED BIT_ULL(14)
155
156 #define ICE_DBG_PKG BIT_ULL(16)
157 #define ICE_DBG_RES BIT_ULL(17)
158 #define ICE_DBG_AQ_MSG BIT_ULL(24)
159 #define ICE_DBG_AQ_DESC BIT_ULL(25)
160 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
161 #define ICE_DBG_AQ_CMD BIT_ULL(27)
162 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
163 ICE_DBG_AQ_DESC | \
164 ICE_DBG_AQ_DESC_BUF | \
165 ICE_DBG_AQ_CMD)
166 #define ICE_DBG_PARSER BIT_ULL(28)
167
168 #define ICE_DBG_USER BIT_ULL(31)
169 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
170
171 #define IS_UNICAST_ETHER_ADDR(addr) \
172 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
173
174 #define IS_MULTICAST_ETHER_ADDR(addr) \
175 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
176
177 /* Check whether an address is broadcast. */
178 #define IS_BROADCAST_ETHER_ADDR(addr) \
179 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
180
181 #define IS_ZERO_ETHER_ADDR(addr) \
182 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \
183 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \
184 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
185
186 #ifndef IS_ETHER_ADDR_EQUAL
187 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
188 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
189 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
190 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
191 #endif
192
193 enum ice_aq_res_ids {
194 ICE_NVM_RES_ID = 1,
195 ICE_SPD_RES_ID,
196 ICE_CHANGE_LOCK_RES_ID,
197 ICE_GLOBAL_CFG_LOCK_RES_ID
198 };
199
200 /* FW update timeout definitions are in milliseconds */
201 #define ICE_NVM_TIMEOUT 180000
202 #define ICE_CHANGE_LOCK_TIMEOUT 1000
203 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
204
205 enum ice_aq_res_access_type {
206 ICE_RES_READ = 1,
207 ICE_RES_WRITE
208 };
209
210 struct ice_driver_ver {
211 u8 major_ver;
212 u8 minor_ver;
213 u8 build_ver;
214 u8 subbuild_ver;
215 u8 driver_string[32];
216 };
217
218 enum ice_fc_mode {
219 ICE_FC_NONE = 0,
220 ICE_FC_RX_PAUSE,
221 ICE_FC_TX_PAUSE,
222 ICE_FC_FULL,
223 ICE_FC_AUTO,
224 ICE_FC_PFC,
225 ICE_FC_DFLT
226 };
227
228 enum ice_phy_cache_mode {
229 ICE_FC_MODE = 0,
230 ICE_SPEED_MODE,
231 ICE_FEC_MODE
232 };
233
234 enum ice_fec_mode {
235 ICE_FEC_NONE = 0,
236 ICE_FEC_RS,
237 ICE_FEC_BASER,
238 ICE_FEC_AUTO
239 };
240
241 struct ice_phy_cache_mode_data {
242 union {
243 enum ice_fec_mode curr_user_fec_req;
244 enum ice_fc_mode curr_user_fc_req;
245 u16 curr_user_speed_req;
246 } data;
247 };
248
249 enum ice_set_fc_aq_failures {
250 ICE_SET_FC_AQ_FAIL_NONE = 0,
251 ICE_SET_FC_AQ_FAIL_GET,
252 ICE_SET_FC_AQ_FAIL_SET,
253 ICE_SET_FC_AQ_FAIL_UPDATE
254 };
255
256 /* These are structs for managing the hardware information and the operations */
257 /* MAC types */
258 enum ice_mac_type {
259 ICE_MAC_UNKNOWN = 0,
260 ICE_MAC_VF,
261 ICE_MAC_E810,
262 ICE_MAC_GENERIC,
263 };
264
265 /* Media Types */
266 enum ice_media_type {
267 ICE_MEDIA_UNKNOWN = 0,
268 ICE_MEDIA_FIBER,
269 ICE_MEDIA_BASET,
270 ICE_MEDIA_BACKPLANE,
271 ICE_MEDIA_DA,
272 ICE_MEDIA_AUI,
273 };
274
275 /* Software VSI types. */
276 enum ice_vsi_type {
277 ICE_VSI_PF = 0,
278 ICE_VSI_VF = 1,
279 ICE_VSI_LB = 6,
280 };
281
282 struct ice_link_status {
283 /* Refer to ice_aq_phy_type for bits definition */
284 u64 phy_type_low;
285 u64 phy_type_high;
286 u8 topo_media_conflict;
287 u16 max_frame_size;
288 u16 link_speed;
289 u16 req_speeds;
290 u8 link_cfg_err;
291 u8 lse_ena; /* Link Status Event notification */
292 u8 link_info;
293 u8 an_info;
294 u8 ext_info;
295 u8 fec_info;
296 u8 pacing;
297 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
298 * ice_aqc_get_phy_caps structure
299 */
300 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
301 };
302
303 /* Different data queue types: These are mainly for SW consumption. */
304 enum ice_q {
305 ICE_DATA_Q_DOORBELL,
306 ICE_DATA_Q_CMPL,
307 ICE_DATA_Q_QUANTA,
308 ICE_DATA_Q_RX,
309 ICE_DATA_Q_TX,
310 };
311
312 /* Different reset sources for which a disable queue AQ call has to be made in
313 * order to clean the Tx scheduler as a part of the reset
314 */
315 enum ice_disq_rst_src {
316 ICE_NO_RESET = 0,
317 ICE_VM_RESET,
318 ICE_VF_RESET,
319 };
320
321 /* PHY info such as phy_type, etc... */
322 struct ice_phy_info {
323 struct ice_link_status link_info;
324 struct ice_link_status link_info_old;
325 u64 phy_type_low;
326 u64 phy_type_high;
327 enum ice_media_type media_type;
328 u8 get_link_info;
329 /* Please refer to struct ice_aqc_get_link_status_data to get
330 * detail of enable bit in curr_user_speed_req
331 */
332 u16 curr_user_speed_req;
333 enum ice_fec_mode curr_user_fec_req;
334 enum ice_fc_mode curr_user_fc_req;
335 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
336 };
337
338 #define ICE_MAX_NUM_MIRROR_RULES 64
339
340 /* Common HW capabilities for SW use */
341 struct ice_hw_common_caps {
342 /* Write CSR protection */
343 u64 wr_csr_prot;
344 u32 switching_mode;
345 /* switching mode supported - EVB switching (including cloud) */
346 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
347
348 /* Manageablity mode & supported protocols over MCTP */
349 u32 mgmt_mode;
350 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
351 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
352 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
353
354 u32 mgmt_protocols_mctp;
355 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
356 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
357 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
358 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
359
360 u32 os2bmc;
361 u32 valid_functions;
362 /* DCB capabilities */
363 u32 active_tc_bitmap;
364 u32 maxtc;
365
366 /* RSS related capabilities */
367 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
368 u32 rss_table_entry_width; /* RSS Entry width in bits */
369
370 /* Tx/Rx queues */
371 u32 num_rxq; /* Number/Total Rx queues */
372 u32 rxq_first_id; /* First queue ID for Rx queues */
373 u32 num_txq; /* Number/Total Tx queues */
374 u32 txq_first_id; /* First queue ID for Tx queues */
375
376 /* MSI-X vectors */
377 u32 num_msix_vectors;
378 u32 msix_vector_first_id;
379
380 /* Max MTU for function or device */
381 u32 max_mtu;
382
383 /* WOL related */
384 u32 num_wol_proxy_fltr;
385 u32 wol_proxy_vsi_seid;
386
387 /* LED/SDP pin count */
388 u32 led_pin_num;
389 u32 sdp_pin_num;
390
391 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
392 #define ICE_MAX_SUPPORTED_GPIO_LED 12
393 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
394 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
395 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
396
397 /* SR-IOV virtualization */
398 u8 sr_iov_1_1; /* SR-IOV enabled */
399
400 /* EVB capabilities */
401 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
402 u8 evb_802_1_qbh; /* Bridge Port Extension */
403
404 u8 dcb;
405 u8 iscsi;
406 u8 mgmt_cem;
407
408 /* WoL and APM support */
409 #define ICE_WOL_SUPPORT_M BIT(0)
410 #define ICE_ACPI_PROG_MTHD_M BIT(1)
411 #define ICE_PROXY_SUPPORT_M BIT(2)
412 u8 apm_wol_support;
413 u8 acpi_prog_mthd;
414 u8 proxy_support;
415 bool sec_rev_disabled;
416 bool update_disabled;
417 bool nvm_unified_update;
418 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
419 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
420 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
421 /* PCIe reset avoidance */
422 bool pcie_reset_avoidance; /* false: not supported, true: supported */
423 /* Post update reset restriction */
424 bool reset_restrict_support; /* false: not supported, true: supported */
425
426 /* External topology device images within the NVM */
427 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
428 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
429 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
430 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
431 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
432 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
433 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
434 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
435 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
436 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
437 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
438 };
439
440 /* Function specific capabilities */
441 struct ice_hw_func_caps {
442 struct ice_hw_common_caps common_cap;
443 u32 num_allocd_vfs; /* Number of allocated VFs */
444 u32 vf_base_id; /* Logical ID of the first VF */
445 u32 guar_num_vsi;
446 };
447
448 /* Device wide capabilities */
449 struct ice_hw_dev_caps {
450 struct ice_hw_common_caps common_cap;
451 u32 num_vfs_exposed; /* Total number of VFs exposed */
452 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
453 u32 num_funcs;
454 };
455
456 /* Information about MAC such as address, etc... */
457 struct ice_mac_info {
458 u8 lan_addr[ETH_ALEN];
459 u8 perm_addr[ETH_ALEN];
460 u8 port_addr[ETH_ALEN];
461 u8 wol_addr[ETH_ALEN];
462 };
463
464 /* PCI bus types */
465 enum ice_bus_type {
466 ice_bus_unknown = 0,
467 ice_bus_pci_express,
468 ice_bus_embedded, /* Is device Embedded versus card */
469 ice_bus_reserved
470 };
471
472 /* PCI bus speeds */
473 enum ice_pcie_bus_speed {
474 ice_pcie_speed_unknown = 0xff,
475 ice_pcie_speed_2_5GT = 0x14,
476 ice_pcie_speed_5_0GT = 0x15,
477 ice_pcie_speed_8_0GT = 0x16,
478 ice_pcie_speed_16_0GT = 0x17
479 };
480
481 /* PCI bus widths */
482 enum ice_pcie_link_width {
483 ice_pcie_lnk_width_resrv = 0x00,
484 ice_pcie_lnk_x1 = 0x01,
485 ice_pcie_lnk_x2 = 0x02,
486 ice_pcie_lnk_x4 = 0x04,
487 ice_pcie_lnk_x8 = 0x08,
488 ice_pcie_lnk_x12 = 0x0C,
489 ice_pcie_lnk_x16 = 0x10,
490 ice_pcie_lnk_x32 = 0x20,
491 ice_pcie_lnk_width_unknown = 0xff,
492 };
493
494 /* Reset types used to determine which kind of reset was requested. These
495 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
496 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
497 * because its reset source is different than the other types listed.
498 */
499 enum ice_reset_req {
500 ICE_RESET_POR = 0,
501 ICE_RESET_INVAL = 0,
502 ICE_RESET_CORER = 1,
503 ICE_RESET_GLOBR = 2,
504 ICE_RESET_EMPR = 3,
505 ICE_RESET_PFR = 4,
506 };
507
508 /* Bus parameters */
509 struct ice_bus_info {
510 enum ice_pcie_bus_speed speed;
511 enum ice_pcie_link_width width;
512 enum ice_bus_type type;
513 u16 domain_num;
514 u16 device;
515 u8 func;
516 u8 bus_num;
517 };
518
519 /* Flow control (FC) parameters */
520 struct ice_fc_info {
521 enum ice_fc_mode current_mode; /* FC mode in effect */
522 enum ice_fc_mode req_mode; /* FC mode requested by caller */
523 };
524
525 /* Option ROM version information */
526 struct ice_orom_info {
527 u8 major; /* Major version of OROM */
528 u8 patch; /* Patch version of OROM */
529 u16 build; /* Build version of OROM */
530 u32 srev; /* Security revision */
531 };
532
533 /* NVM version information */
534 struct ice_nvm_info {
535 u32 eetrack;
536 u32 srev;
537 u8 major;
538 u8 minor;
539 };
540
541 /* Minimum Security Revision information */
542 struct ice_minsrev_info {
543 u32 nvm;
544 u32 orom;
545 u8 nvm_valid : 1;
546 u8 orom_valid : 1;
547 };
548
549 /* netlist version information */
550 struct ice_netlist_info {
551 u32 major; /* major high/low */
552 u32 minor; /* minor high/low */
553 u32 type; /* type high/low */
554 u32 rev; /* revision high/low */
555 u32 hash; /* SHA-1 hash word */
556 u16 cust_ver; /* customer version */
557 };
558
559 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
560 * of the flash image.
561 */
562 enum ice_flash_bank {
563 ICE_INVALID_FLASH_BANK,
564 ICE_1ST_FLASH_BANK,
565 ICE_2ND_FLASH_BANK,
566 };
567
568 /* Enumeration of which flash bank is desired to read from, either the active
569 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
570 * code which just wants to read the active or inactive flash bank.
571 */
572 enum ice_bank_select {
573 ICE_ACTIVE_FLASH_BANK,
574 ICE_INACTIVE_FLASH_BANK,
575 };
576
577 /* information for accessing NVM, OROM, and Netlist flash banks */
578 struct ice_bank_info {
579 u32 nvm_ptr; /* Pointer to 1st NVM bank */
580 u32 nvm_size; /* Size of NVM bank */
581 u32 orom_ptr; /* Pointer to 1st OROM bank */
582 u32 orom_size; /* Size of OROM bank */
583 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
584 u32 netlist_size; /* Size of Netlist bank */
585 enum ice_flash_bank nvm_bank; /* Active NVM bank */
586 enum ice_flash_bank orom_bank; /* Active OROM bank */
587 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
588 };
589
590 /* Flash Chip Information */
591 struct ice_flash_info {
592 struct ice_orom_info orom; /* Option ROM version info */
593 struct ice_nvm_info nvm; /* NVM version information */
594 struct ice_netlist_info netlist;/* Netlist version info */
595 struct ice_bank_info banks; /* Flash Bank information */
596 u16 sr_words; /* Shadow RAM size in words */
597 u32 flash_size; /* Size of available flash in bytes */
598 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
599 };
600
601 struct ice_link_default_override_tlv {
602 u8 options;
603 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
604 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
605 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
606 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
607 #define ICE_LINK_OVERRIDE_EN BIT(3)
608 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
609 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
610 u8 phy_config;
611 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
612 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
613 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
614 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
615 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
616 u8 fec_options;
617 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
618 u8 rsvd1;
619 u64 phy_type_low;
620 u64 phy_type_high;
621 };
622
623 #define ICE_NVM_VER_LEN 32
624
625 /* Max number of port to queue branches w.r.t topology */
626 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
627
628 #define ice_for_each_traffic_class(_i) \
629 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
630
631 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
632 * to driver defined policy for default aggregator
633 */
634 #define ICE_INVAL_TEID 0xFFFFFFFF
635 #define ICE_DFLT_AGG_ID 0
636
637 struct ice_sched_node {
638 struct ice_sched_node *parent;
639 struct ice_sched_node *sibling; /* next sibling in the same layer */
640 struct ice_sched_node **children;
641 struct ice_aqc_txsched_elem_data info;
642 u32 agg_id; /* aggregator group ID */
643 u16 vsi_handle;
644 u8 in_use; /* suspended or in use */
645 u8 tx_sched_layer; /* Logical Layer (1-9) */
646 u8 num_children;
647 u8 tc_num;
648 u8 owner;
649 #define ICE_SCHED_NODE_OWNER_LAN 0
650 #define ICE_SCHED_NODE_OWNER_AE 1
651 #define ICE_SCHED_NODE_OWNER_RDMA 2
652 };
653
654 /* Access Macros for Tx Sched Elements data */
655 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
656 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
657 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
658 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
659 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
660 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
661 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
662 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
663 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
664 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
665 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
666
667 struct ice_sched_rl_profile {
668 u32 rate; /* In Kbps */
669 struct ice_aqc_rl_profile_elem info;
670 };
671
672 /* The aggregator type determines if identifier is for a VSI group,
673 * aggregator group, aggregator of queues, or queue group.
674 */
675 enum ice_agg_type {
676 ICE_AGG_TYPE_UNKNOWN = 0,
677 ICE_AGG_TYPE_TC,
678 ICE_AGG_TYPE_AGG, /* aggregator */
679 ICE_AGG_TYPE_VSI,
680 ICE_AGG_TYPE_QG,
681 ICE_AGG_TYPE_Q
682 };
683
684 /* Rate limit types */
685 enum ice_rl_type {
686 ICE_UNKNOWN_BW = 0,
687 ICE_MIN_BW, /* for CIR profile */
688 ICE_MAX_BW, /* for EIR profile */
689 ICE_SHARED_BW /* for shared profile */
690 };
691
692 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
693 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
694 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
695 #define ICE_SCHED_NO_PRIORITY 0
696 #define ICE_SCHED_NO_BW_WT 0
697 #define ICE_SCHED_DFLT_RL_PROF_ID 0
698 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
699 #define ICE_SCHED_DFLT_BW_WT 4
700 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
701 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
702
703 /* Access Macros for Tx Sched RL Profile data */
704 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
705 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
706 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
707 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
708 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
709
710 #define ICE_MAX_PORT_PER_PCI_DEV 8
711
712 /* The following tree example shows the naming conventions followed under
713 * ice_port_info struct for default scheduler tree topology.
714 *
715 * A tree on a port
716 * * ---> root node
717 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
718 * * * * * * * * * |
719 * / |
720 * * |
721 * / |-> num_elements (range:1 - 9)
722 * * | implies num_of_layers
723 * / |
724 * (a)* |
725 *
726 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
727 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
728 * need TEID of (a) to add queues.
729 *
730 * This tree
731 * -> has 8 branches (one for each TC)
732 * -> First branch (TC0) has 4 elements
733 * -> has 4 layers
734 * -> (a) is the topmost layer node created by firmware on branch 0
735 *
736 * Note: Above asterisk tree covers only basic terminology and scenario.
737 * Refer to the documentation for more info.
738 */
739
740 /* Data structure for saving BW information */
741 enum ice_bw_type {
742 ICE_BW_TYPE_PRIO,
743 ICE_BW_TYPE_CIR,
744 ICE_BW_TYPE_CIR_WT,
745 ICE_BW_TYPE_EIR,
746 ICE_BW_TYPE_EIR_WT,
747 ICE_BW_TYPE_SHARED,
748 ICE_BW_TYPE_CNT /* This must be last */
749 };
750
751 struct ice_bw {
752 u32 bw;
753 u16 bw_alloc;
754 };
755
756 struct ice_bw_type_info {
757 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
758 u8 generic;
759 struct ice_bw cir_bw;
760 struct ice_bw eir_bw;
761 u32 shared_bw;
762 };
763
764 /* VSI queue context structure for given TC */
765 struct ice_q_ctx {
766 u16 q_handle;
767 u32 q_teid;
768 /* bw_t_info saves queue BW information */
769 struct ice_bw_type_info bw_t_info;
770 };
771
772 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
773 struct ice_sched_vsi_info {
774 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
775 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
776 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
777 /* bw_t_info saves VSI BW information */
778 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
779 };
780
781 /* CEE or IEEE 802.1Qaz ETS Configuration data */
782 struct ice_dcb_ets_cfg {
783 u8 willing;
784 u8 cbs;
785 u8 maxtcs;
786 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
787 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
788 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
789 };
790
791 /* CEE or IEEE 802.1Qaz PFC Configuration data */
792 struct ice_dcb_pfc_cfg {
793 u8 willing;
794 u8 mbc;
795 u8 pfccap;
796 u8 pfcena;
797 };
798
799 /* CEE or IEEE 802.1Qaz Application Priority data */
800 struct ice_dcb_app_priority_table {
801 u16 prot_id;
802 u8 priority;
803 u8 selector;
804 };
805
806 #define ICE_MAX_USER_PRIORITY 8
807 #define ICE_DCBX_MAX_APPS 64
808 #define ICE_DSCP_NUM_VAL 64
809 #define ICE_LLDPDU_SIZE 1500
810 #define ICE_TLV_STATUS_OPER 0x1
811 #define ICE_TLV_STATUS_SYNC 0x2
812 #define ICE_TLV_STATUS_ERR 0x4
813 #define ICE_APP_PROT_ID_FCOE 0x8906
814 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
815 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
816 #define ICE_APP_PROT_ID_FIP 0x8914
817 #define ICE_APP_SEL_ETHTYPE 0x1
818 #define ICE_APP_SEL_TCPIP 0x2
819 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
820 #define ICE_CEE_APP_SEL_TCPIP 0x1
821
822 struct ice_dcbx_cfg {
823 u32 numapps;
824 u32 tlv_status; /* CEE mode TLV status */
825 struct ice_dcb_ets_cfg etscfg;
826 struct ice_dcb_ets_cfg etsrec;
827 struct ice_dcb_pfc_cfg pfc;
828 #define ICE_QOS_MODE_VLAN 0x0
829 #define ICE_QOS_MODE_DSCP 0x1
830 u8 pfc_mode;
831 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
832 /* when DSCP mapping defined by user set its bit to 1 */
833 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
834 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
835 u8 dscp_map[ICE_DSCP_NUM_VAL];
836 u8 dcbx_mode;
837 #define ICE_DCBX_MODE_CEE 0x1
838 #define ICE_DCBX_MODE_IEEE 0x2
839 u8 app_mode;
840 #define ICE_DCBX_APPS_NON_WILLING 0x1
841 };
842
843 struct ice_qos_cfg {
844 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
845 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
846 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
847 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
848 u8 is_sw_lldp : 1;
849 };
850
851 struct ice_port_info {
852 struct ice_sched_node *root; /* Root Node per Port */
853 struct ice_hw *hw; /* back pointer to HW instance */
854 u32 last_node_teid; /* scheduler last node info */
855 u16 sw_id; /* Initial switch ID belongs to port */
856 u16 pf_vf_num;
857 u8 port_state;
858 #define ICE_SCHED_PORT_STATE_INIT 0x0
859 #define ICE_SCHED_PORT_STATE_READY 0x1
860 u8 lport;
861 #define ICE_LPORT_MASK 0xff
862 u16 dflt_tx_vsi_rule_id;
863 u16 dflt_tx_vsi_num;
864 u16 dflt_rx_vsi_rule_id;
865 u16 dflt_rx_vsi_num;
866 struct ice_fc_info fc;
867 struct ice_mac_info mac;
868 struct ice_phy_info phy;
869 struct ice_lock sched_lock; /* protect access to TXSched tree */
870 struct ice_sched_node *
871 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
872 struct ice_bw_type_info root_node_bw_t_info;
873 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
874 struct ice_qos_cfg qos_cfg;
875 u8 is_vf:1;
876 };
877
878 struct ice_switch_info {
879 struct LIST_HEAD_TYPE vsi_list_map_head;
880 struct ice_sw_recipe *recp_list;
881 u16 prof_res_bm_init;
882 u16 max_used_prof_index;
883
884 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
885 };
886
887
888 /* Enum defining the different states of the mailbox snapshot in the
889 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
890 * states:
891 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
892 * within the mailbox buffer.
893 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
894 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
895 * mailbox and mark any VFs sending more messages than the threshold limit set.
896 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
897 */
898 enum ice_mbx_snapshot_state {
899 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
900 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
901 ICE_MAL_VF_DETECT_STATE_DETECT,
902 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
903 };
904
905 /* Structure to hold information of the static snapshot and the mailbox
906 * buffer data used to generate and track the snapshot.
907 * 1. state: the state of the mailbox snapshot in the malicious VF
908 * detection state handler ice_mbx_vf_state_handler()
909 * 2. head : head of the mailbox snapshot in a circular mailbox buffer
910 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer
911 * 4. num_iterations: number of messages traversed in circular mailbox buffer
912 * 5. num_msg_proc: number of messages processed in mailbox
913 * 6. num_pending_arq: number of pending asynchronous messages
914 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
915 * serviced work item or interrupt.
916 */
917 struct ice_mbx_snap_buffer_data {
918 enum ice_mbx_snapshot_state state;
919 u32 head;
920 u32 tail;
921 u32 num_iterations;
922 u16 num_msg_proc;
923 u16 num_pending_arq;
924 u16 max_num_msgs_mbx;
925 };
926
927 /* Structure to track messages sent by VFs on mailbox:
928 * 1. vf_cntr : a counter array of VFs to track the number of
929 * asynchronous messages sent by each VF
930 * 2. vfcntr_len : number of entries in VF counter array
931 */
932 struct ice_mbx_vf_counter {
933 u32 *vf_cntr;
934 u32 vfcntr_len;
935 };
936
937 /* Structure to hold data relevant to the captured static snapshot
938 * of the PF-VF mailbox.
939 */
940 struct ice_mbx_snapshot {
941 struct ice_mbx_snap_buffer_data mbx_buf;
942 struct ice_mbx_vf_counter mbx_vf;
943 };
944
945 /* Structure to hold data to be used for capturing or updating a
946 * static snapshot.
947 * 1. num_msg_proc: number of messages processed in mailbox
948 * 2. num_pending_arq: number of pending asynchronous messages
949 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
950 * serviced work item or interrupt.
951 * 4. async_watermark_val: An upper threshold set by caller to determine
952 * if the pending arq count is large enough to assume that there is
953 * the possibility of a mailicious VF.
954 */
955 struct ice_mbx_data {
956 u16 num_msg_proc;
957 u16 num_pending_arq;
958 u16 max_num_msgs_mbx;
959 u16 async_watermark_val;
960 };
961
962 /* Port hardware description */
963 struct ice_hw {
964 u8 *hw_addr;
965 void *back;
966 struct ice_aqc_layer_props *layer_info;
967 struct ice_port_info *port_info;
968 /* 2D Array for each Tx Sched RL Profile type */
969 struct ice_sched_rl_profile **cir_profiles;
970 struct ice_sched_rl_profile **eir_profiles;
971 struct ice_sched_rl_profile **srl_profiles;
972 /* PSM clock frequency for calculating RL profile params */
973 u32 psm_clk_freq;
974 u64 debug_mask; /* BITMAP for debug mask */
975 enum ice_mac_type mac_type;
976
977 /* pci info */
978 u16 device_id;
979 u16 vendor_id;
980 u16 subsystem_device_id;
981 u16 subsystem_vendor_id;
982 u8 revision_id;
983
984 u8 pf_id; /* device profile info */
985
986 u16 max_burst_size; /* driver sets this value */
987
988 /* Tx Scheduler values */
989 u8 num_tx_sched_layers;
990 u8 num_tx_sched_phys_layers;
991 u8 flattened_layers;
992 u8 max_cgds;
993 u8 sw_entry_point_layer;
994 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
995 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
996 /* List contain profile ID(s) and other params per layer */
997 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
998 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
999 u8 evb_veb; /* true for VEB, false for VEPA */
1000 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
1001 struct ice_bus_info bus;
1002 struct ice_flash_info flash;
1003 struct ice_hw_dev_caps dev_caps; /* device capabilities */
1004 struct ice_hw_func_caps func_caps; /* function capabilities */
1005
1006 struct ice_switch_info *switch_info; /* switch filter lists */
1007
1008 /* Control Queue info */
1009 struct ice_ctl_q_info adminq;
1010 struct ice_ctl_q_info mailboxq;
1011 u8 api_branch; /* API branch version */
1012 u8 api_maj_ver; /* API major version */
1013 u8 api_min_ver; /* API minor version */
1014 u8 api_patch; /* API patch version */
1015 u8 fw_branch; /* firmware branch version */
1016 u8 fw_maj_ver; /* firmware major version */
1017 u8 fw_min_ver; /* firmware minor version */
1018 u8 fw_patch; /* firmware patch version */
1019 u32 fw_build; /* firmware build number */
1020
1021 struct ice_fwlog_cfg fwlog_cfg;
1022 bool fwlog_support_ena; /* does hardware support FW logging? */
1023
1024 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
1025 * register. Used for determining the ITR/INTRL granularity during
1026 * initialization.
1027 */
1028 #define ICE_MAX_AGG_BW_200G 0x0
1029 #define ICE_MAX_AGG_BW_100G 0X1
1030 #define ICE_MAX_AGG_BW_50G 0x2
1031 #define ICE_MAX_AGG_BW_25G 0x3
1032 /* ITR granularity for different speeds */
1033 #define ICE_ITR_GRAN_ABOVE_25 2
1034 #define ICE_ITR_GRAN_MAX_25 4
1035 /* ITR granularity in 1 us */
1036 u8 itr_gran;
1037 /* INTRL granularity for different speeds */
1038 #define ICE_INTRL_GRAN_ABOVE_25 4
1039 #define ICE_INTRL_GRAN_MAX_25 8
1040 /* INTRL granularity in 1 us */
1041 u8 intrl_gran;
1042
1043 /* true if VSIs can share unicast MAC addr */
1044 u8 umac_shared;
1045
1046 #define ICE_PHY_PER_NAC 1
1047 #define ICE_MAX_QUAD 2
1048 #define ICE_NUM_QUAD_TYPE 2
1049 #define ICE_PORTS_PER_QUAD 4
1050 #define ICE_PHY_0_LAST_QUAD 1
1051 #define ICE_PORTS_PER_PHY 8
1052 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
1053
1054 /* Active package version (currently active) */
1055 struct ice_pkg_ver active_pkg_ver;
1056 u32 pkg_seg_id;
1057 u32 active_track_id;
1058 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
1059 u8 active_pkg_in_nvm;
1060
1061 enum ice_aq_err pkg_dwnld_status;
1062
1063 /* Driver's package ver - (from the Ice Metadata section) */
1064 struct ice_pkg_ver pkg_ver;
1065 u8 pkg_name[ICE_PKG_NAME_SIZE];
1066
1067 /* Driver's Ice segment format version and id (from the Ice seg) */
1068 struct ice_pkg_ver ice_seg_fmt_ver;
1069 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1070
1071 /* Pointer to the ice segment */
1072 struct ice_seg *seg;
1073
1074 /* Pointer to allocated copy of pkg memory */
1075 u8 *pkg_copy;
1076 u32 pkg_size;
1077
1078 /* tunneling info */
1079 struct ice_lock tnl_lock;
1080 struct ice_tunnel_table tnl;
1081
1082 /* HW block tables */
1083 struct ice_blk_info blk[ICE_BLK_COUNT];
1084 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1085 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1086 struct ice_lock rss_locks; /* protect RSS configuration */
1087 struct LIST_HEAD_TYPE rss_list_head;
1088 struct ice_mbx_snapshot mbx_snapshot;
1089 u8 dvm_ena;
1090 };
1091
1092 /* Statistics collected by each port, VSI, VEB, and S-channel */
1093 struct ice_eth_stats {
1094 u64 rx_bytes; /* gorc */
1095 u64 rx_unicast; /* uprc */
1096 u64 rx_multicast; /* mprc */
1097 u64 rx_broadcast; /* bprc */
1098 u64 rx_discards; /* rdpc */
1099 u64 rx_unknown_protocol; /* rupp */
1100 u64 tx_bytes; /* gotc */
1101 u64 tx_unicast; /* uptc */
1102 u64 tx_multicast; /* mptc */
1103 u64 tx_broadcast; /* bptc */
1104 u64 tx_discards; /* tdpc */
1105 u64 tx_errors; /* tepc */
1106 u64 rx_no_desc; /* repc */
1107 u64 rx_errors; /* repc */
1108 };
1109
1110 #define ICE_MAX_UP 8
1111
1112 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1113 struct ice_veb_up_stats {
1114 u64 up_rx_pkts[ICE_MAX_UP];
1115 u64 up_rx_bytes[ICE_MAX_UP];
1116 u64 up_tx_pkts[ICE_MAX_UP];
1117 u64 up_tx_bytes[ICE_MAX_UP];
1118 };
1119
1120 /* Statistics collected by the MAC */
1121 struct ice_hw_port_stats {
1122 /* eth stats collected by the port */
1123 struct ice_eth_stats eth;
1124 /* additional port specific stats */
1125 u64 tx_dropped_link_down; /* tdold */
1126 u64 crc_errors; /* crcerrs */
1127 u64 illegal_bytes; /* illerrc */
1128 u64 error_bytes; /* errbc */
1129 u64 mac_local_faults; /* mlfc */
1130 u64 mac_remote_faults; /* mrfc */
1131 u64 rx_len_errors; /* rlec */
1132 u64 link_xon_rx; /* lxonrxc */
1133 u64 link_xoff_rx; /* lxoffrxc */
1134 u64 link_xon_tx; /* lxontxc */
1135 u64 link_xoff_tx; /* lxofftxc */
1136 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1137 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1138 u64 priority_xon_tx[8]; /* pxontxc[8] */
1139 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1140 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1141 u64 rx_size_64; /* prc64 */
1142 u64 rx_size_127; /* prc127 */
1143 u64 rx_size_255; /* prc255 */
1144 u64 rx_size_511; /* prc511 */
1145 u64 rx_size_1023; /* prc1023 */
1146 u64 rx_size_1522; /* prc1522 */
1147 u64 rx_size_big; /* prc9522 */
1148 u64 rx_undersize; /* ruc */
1149 u64 rx_fragments; /* rfc */
1150 u64 rx_oversize; /* roc */
1151 u64 rx_jabber; /* rjc */
1152 u64 tx_size_64; /* ptc64 */
1153 u64 tx_size_127; /* ptc127 */
1154 u64 tx_size_255; /* ptc255 */
1155 u64 tx_size_511; /* ptc511 */
1156 u64 tx_size_1023; /* ptc1023 */
1157 u64 tx_size_1522; /* ptc1522 */
1158 u64 tx_size_big; /* ptc9522 */
1159 u64 mac_short_pkt_dropped; /* mspdc */
1160 /* EEE LPI */
1161 u32 tx_lpi_status;
1162 u32 rx_lpi_status;
1163 u64 tx_lpi_count; /* etlpic */
1164 u64 rx_lpi_count; /* erlpic */
1165 };
1166
1167 enum ice_sw_fwd_act_type {
1168 ICE_FWD_TO_VSI = 0,
1169 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1170 ICE_FWD_TO_Q,
1171 ICE_FWD_TO_QGRP,
1172 ICE_DROP_PACKET,
1173 ICE_INVAL_ACT
1174 };
1175
1176 struct ice_aq_get_set_rss_lut_params {
1177 u16 vsi_handle; /* software VSI handle */
1178 u16 lut_size; /* size of the LUT buffer */
1179 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1180 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1181 u8 global_lut_id; /* only valid when lut_type is global */
1182 };
1183
1184 /* Checksum and Shadow RAM pointers */
1185 #define ICE_SR_NVM_CTRL_WORD 0x00
1186 #define ICE_SR_PHY_ANALOG_PTR 0x04
1187 #define ICE_SR_OPTION_ROM_PTR 0x05
1188 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1189 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1190 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1191 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1192 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1193 #define ICE_SR_PE_IMAGE_PTR 0x0C
1194 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1195 #define ICE_SR_MNG_CFG_PTR 0x0E
1196 #define ICE_SR_EMP_MODULE_PTR 0x0F
1197 #define ICE_SR_PBA_BLOCK_PTR 0x16
1198 #define ICE_SR_BOOT_CFG_PTR 0x132
1199 #define ICE_SR_NVM_WOL_CFG 0x19
1200 #define ICE_NVM_OROM_VER_OFF 0x02
1201 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1202 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1203 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1204 #define ICE_SR_NVM_MAP_VER 0x29
1205 #define ICE_SR_NVM_IMAGE_VER 0x2A
1206 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1207 #define ICE_SR_NVM_EETRACK_LO 0x2D
1208 #define ICE_SR_NVM_EETRACK_HI 0x2E
1209 #define ICE_NVM_VER_LO_SHIFT 0
1210 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1211 #define ICE_NVM_VER_HI_SHIFT 12
1212 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1213 #define ICE_OEM_EETRACK_ID 0xffffffff
1214 #define ICE_OROM_VER_PATCH_SHIFT 0
1215 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1216 #define ICE_OROM_VER_BUILD_SHIFT 8
1217 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1218 #define ICE_OROM_VER_SHIFT 24
1219 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1220 #define ICE_SR_VPD_PTR 0x2F
1221 #define ICE_SR_PXE_SETUP_PTR 0x30
1222 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1223 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1224 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1225 #define ICE_SR_VLAN_CFG_PTR 0x37
1226 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1227 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1228 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1229 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1230 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1231 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1232 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1233 #define ICE_SR_PFA_PTR 0x40
1234 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1235 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1236 #define ICE_SR_NVM_BANK_SIZE 0x43
1237 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1238 #define ICE_SR_OROM_BANK_SIZE 0x45
1239 #define ICE_SR_NETLIST_BANK_PTR 0x46
1240 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1241 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1242 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1243 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1244 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1245 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1246
1247 /* CSS Header words */
1248 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1249 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1250 #define ICE_NVM_CSS_SREV_L 0x14
1251 #define ICE_NVM_CSS_SREV_H 0x15
1252
1253 /* Length of Authentication header section in words */
1254 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1255
1256 /* The Link Topology Netlist section is stored as a series of words. It is
1257 * stored in the NVM as a TLV, with the first two words containing the type
1258 * and length.
1259 */
1260 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1261 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1262 #define ICE_NETLIST_LEN_OFFSET 0x0001
1263
1264 /* The Link Topology section follows the TLV header. When reading the netlist
1265 * using ice_read_netlist_module, we need to account for the 2-word TLV
1266 * header.
1267 */
1268 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1269
1270 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1271 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1272
1273 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1274
1275 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1276 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1277 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1278
1279 /* netlist ID block field offsets (word offsets) */
1280 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1281 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1282 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1283 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1284 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1285 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1286 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1287 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1288 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1289 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1290
1291 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1292 #define ICE_SR_VPD_SIZE_WORDS 512
1293 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1294 #define ICE_SR_CTRL_WORD_1_S 0x06
1295 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1296 #define ICE_SR_CTRL_WORD_VALID 0x1
1297 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1298 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1299 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1300
1301 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1302
1303 /* Shadow RAM related */
1304 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1305 #define ICE_SR_BUF_ALIGNMENT 4096
1306 #define ICE_SR_WORDS_IN_1KB 512
1307 /* Checksum should be calculated such that after adding all the words,
1308 * including the checksum word itself, the sum should be 0xBABA.
1309 */
1310 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1311
1312 /* Link override related */
1313 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1314 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1315 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1316 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1317 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1318 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1319 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1320 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1321
1322 #define ICE_PBA_FLAG_DFLT 0xFAFA
1323 /* Hash redirection LUT for VSI - maximum array size */
1324 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1325
1326 /*
1327 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1328 * This is needed to determine the BAR0 space for the VFs
1329 */
1330 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1331 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1332 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1333
1334 /* AQ API version for LLDP_FILTER_CONTROL */
1335 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1336 #define ICE_FW_API_LLDP_FLTR_MIN 7
1337 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1338
1339 /* AQ API version for report default configuration */
1340 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1341 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1342 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1343
1344 /* AQ API version for FW health reports */
1345 #define ICE_FW_API_HEALTH_REPORT_MAJ 1
1346 #define ICE_FW_API_HEALTH_REPORT_MIN 7
1347 #define ICE_FW_API_HEALTH_REPORT_PATCH 6
1348
1349 /* AQ API version for FW auto drop reports */
1350 #define ICE_FW_API_AUTO_DROP_MAJ 1
1351 #define ICE_FW_API_AUTO_DROP_MIN 4
1352 #endif /* _ICE_TYPE_H_ */
1353