1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <[email protected]> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_media.h> 57 #include <net/pfil.h> 58 #include <netinet/in.h> 59 #include <netinet/tcp_lro.h> 60 61 #include "offload.h" 62 #include "t4_ioctl.h" 63 #include "common/t4_msg.h" 64 #include "firmware/t4fw_interface.h" 65 66 #define KTR_CXGBE KTR_SPARE3 67 MALLOC_DECLARE(M_CXGBE); 68 #define CXGBE_UNIMPLEMENTED(s) \ 69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 70 71 #ifndef SYSCTL_ADD_UQUAD 72 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 73 #define sysctl_handle_64 sysctl_handle_quad 74 #define CTLTYPE_U64 CTLTYPE_QUAD 75 #endif 76 77 SYSCTL_DECL(_hw_cxgbe); 78 79 struct adapter; 80 typedef struct adapter adapter_t; 81 82 enum { 83 /* 84 * All ingress queues use this entry size. Note that the firmware event 85 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 86 * be at least 64. 87 */ 88 IQ_ESIZE = 64, 89 90 /* Default queue sizes for all kinds of ingress queues */ 91 FW_IQ_QSIZE = 256, 92 RX_IQ_QSIZE = 1024, 93 94 /* All egress queues use this entry size */ 95 EQ_ESIZE = 64, 96 97 /* Default queue sizes for all kinds of egress queues */ 98 CTRL_EQ_QSIZE = 1024, 99 TX_EQ_QSIZE = 1024, 100 101 #if MJUMPAGESIZE != MCLBYTES 102 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 103 #else 104 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 105 #endif 106 CL_METADATA_SIZE = CACHE_LINE_SIZE, 107 108 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 109 TX_SGL_SEGS = 39, 110 TX_SGL_SEGS_TSO = 38, 111 TX_SGL_SEGS_VM = 38, 112 TX_SGL_SEGS_VM_TSO = 37, 113 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 114 TX_SGL_SEGS_VXLAN_TSO = 37, 115 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 116 }; 117 118 enum { 119 /* adapter intr_type */ 120 INTR_INTX = (1 << 0), 121 INTR_MSI = (1 << 1), 122 INTR_MSIX = (1 << 2) 123 }; 124 125 enum { 126 XGMAC_MTU = (1 << 0), 127 XGMAC_PROMISC = (1 << 1), 128 XGMAC_ALLMULTI = (1 << 2), 129 XGMAC_VLANEX = (1 << 3), 130 XGMAC_UCADDR = (1 << 4), 131 XGMAC_MCADDRS = (1 << 5), 132 133 XGMAC_ALL = 0xffff 134 }; 135 136 enum { 137 /* flags understood by begin_synchronized_op */ 138 HOLD_LOCK = (1 << 0), 139 SLEEP_OK = (1 << 1), 140 INTR_OK = (1 << 2), 141 142 /* flags understood by end_synchronized_op */ 143 LOCK_HELD = HOLD_LOCK, 144 }; 145 146 enum { 147 /* adapter flags */ 148 FULL_INIT_DONE = (1 << 0), 149 FW_OK = (1 << 1), 150 CHK_MBOX_ACCESS = (1 << 2), 151 MASTER_PF = (1 << 3), 152 ADAP_SYSCTL_CTX = (1 << 4), 153 ADAP_ERR = (1 << 5), 154 BUF_PACKING_OK = (1 << 6), 155 IS_VF = (1 << 7), 156 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 157 CXGBE_BUSY = (1 << 9), 158 159 /* port flags */ 160 HAS_TRACEQ = (1 << 3), 161 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 162 163 /* VI flags */ 164 DOOMED = (1 << 0), 165 VI_INIT_DONE = (1 << 1), 166 VI_SYSCTL_CTX = (1 << 2), 167 TX_USES_VM_WR = (1 << 3), 168 VI_SKIP_STATS = (1 << 4), 169 170 /* adapter debug_flags */ 171 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 172 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 173 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 174 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 175 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 176 }; 177 178 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 179 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184 struct vi_info { 185 device_t dev; 186 struct port_info *pi; 187 struct adapter *adapter; 188 189 struct ifnet *ifp; 190 struct pfil_head *pfil; 191 192 unsigned long flags; 193 int if_flags; 194 195 uint16_t *rss, *nm_rss; 196 uint16_t viid; /* opaque VI identifier */ 197 uint16_t smt_idx; 198 uint16_t vin; 199 uint8_t vfvld; 200 int16_t xact_addr_filt;/* index of exact MAC address filter */ 201 uint16_t rss_size; /* size of VI's RSS table slice */ 202 uint16_t rss_base; /* start of VI's RSS table slice */ 203 int hashen; 204 205 int nintr; 206 int first_intr; 207 208 /* These need to be int as they are used in sysctl */ 209 int ntxq; /* # of tx queues */ 210 int first_txq; /* index of first tx queue */ 211 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 212 int nrxq; /* # of rx queues */ 213 int first_rxq; /* index of first rx queue */ 214 int nofldtxq; /* # of offload tx queues */ 215 int first_ofld_txq; /* index of first offload tx queue */ 216 int nofldrxq; /* # of offload rx queues */ 217 int first_ofld_rxq; /* index of first offload rx queue */ 218 int nnmtxq; 219 int first_nm_txq; 220 int nnmrxq; 221 int first_nm_rxq; 222 int tmr_idx; 223 int ofld_tmr_idx; 224 int pktc_idx; 225 int ofld_pktc_idx; 226 int qsize_rxq; 227 int qsize_txq; 228 229 struct timeval last_refreshed; 230 struct fw_vi_stats_vf stats; 231 struct mtx tick_mtx; 232 struct callout tick; 233 234 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 235 236 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 237 }; 238 239 struct tx_ch_rl_params { 240 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 241 uint32_t maxrate; 242 }; 243 244 enum { 245 CLRL_USER = (1 << 0), /* allocated manually. */ 246 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 247 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 248 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 249 }; 250 251 struct tx_cl_rl_params { 252 int refcount; 253 uint8_t flags; 254 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 255 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 256 enum fw_sched_params_mode mode; /* aggr or per-flow */ 257 uint32_t maxrate; 258 uint16_t pktsize; 259 uint16_t burstsize; 260 }; 261 262 /* Tx scheduler parameters for a channel/port */ 263 struct tx_sched_params { 264 /* Channel Rate Limiter */ 265 struct tx_ch_rl_params ch_rl; 266 267 /* Class WRR */ 268 /* XXX */ 269 270 /* Class Rate Limiter (including the default pktsize and burstsize). */ 271 int pktsize; 272 int burstsize; 273 struct tx_cl_rl_params cl_rl[]; 274 }; 275 276 struct port_info { 277 device_t dev; 278 struct adapter *adapter; 279 280 struct vi_info *vi; 281 int nvi; 282 int up_vis; 283 int uld_vis; 284 bool vxlan_tcam_entry; 285 286 struct tx_sched_params *sched_params; 287 288 struct mtx pi_lock; 289 char lockname[16]; 290 unsigned long flags; 291 292 uint8_t lport; /* associated offload logical port */ 293 int8_t mdio_addr; 294 uint8_t port_type; 295 uint8_t mod_type; 296 uint8_t port_id; 297 uint8_t tx_chan; 298 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 299 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 300 uint8_t rx_c_chan; /* rx TP c-channel */ 301 302 struct link_config link_cfg; 303 struct ifmedia media; 304 305 struct port_stats stats; 306 u_int tnl_cong_drops; 307 u_int tx_parse_error; 308 int fcs_reg; 309 uint64_t fcs_base; 310 }; 311 312 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 313 314 struct cluster_metadata { 315 uma_zone_t zone; 316 caddr_t cl; 317 u_int refcount; 318 }; 319 320 struct fl_sdesc { 321 caddr_t cl; 322 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 323 int16_t moff; /* offset of metadata from cl */ 324 uint8_t zidx; 325 }; 326 327 struct tx_desc { 328 __be64 flit[8]; 329 }; 330 331 struct tx_sdesc { 332 struct mbuf *m; /* m_nextpkt linked chain of frames */ 333 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 334 }; 335 336 337 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 338 struct iq_desc { 339 struct rss_header rss; 340 uint8_t cpl[IQ_PAD]; 341 struct rsp_ctrl rsp; 342 }; 343 #undef IQ_PAD 344 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 345 346 enum { 347 /* iq flags */ 348 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 349 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 350 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 351 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 352 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 353 354 /* iq state */ 355 IQS_DISABLED = 0, 356 IQS_BUSY = 1, 357 IQS_IDLE = 2, 358 359 /* netmap related flags */ 360 NM_OFF = 0, 361 NM_ON = 1, 362 NM_BUSY = 2, 363 }; 364 365 enum { 366 CPL_COOKIE_RESERVED = 0, 367 CPL_COOKIE_FILTER, 368 CPL_COOKIE_DDP0, 369 CPL_COOKIE_DDP1, 370 CPL_COOKIE_TOM, 371 CPL_COOKIE_HASHFILTER, 372 CPL_COOKIE_ETHOFLD, 373 CPL_COOKIE_KERN_TLS, 374 375 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 376 }; 377 378 struct sge_iq; 379 struct rss_header; 380 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 381 struct mbuf *); 382 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 383 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 384 385 /* 386 * Ingress Queue: T4 is producer, driver is consumer. 387 */ 388 struct sge_iq { 389 uint32_t flags; 390 volatile int state; 391 struct adapter *adapter; 392 struct iq_desc *desc; /* KVA of descriptor ring */ 393 int8_t intr_pktc_idx; /* packet count threshold index */ 394 uint8_t gen; /* generation bit */ 395 uint8_t intr_params; /* interrupt holdoff parameters */ 396 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 397 uint16_t qsize; /* size (# of entries) of the queue */ 398 uint16_t sidx; /* index of the entry with the status page */ 399 uint16_t cidx; /* consumer index */ 400 uint16_t cntxt_id; /* SGE context id for the iq */ 401 uint16_t abs_id; /* absolute SGE id for the iq */ 402 403 STAILQ_ENTRY(sge_iq) link; 404 405 bus_dma_tag_t desc_tag; 406 bus_dmamap_t desc_map; 407 bus_addr_t ba; /* bus address of descriptor ring */ 408 }; 409 410 enum { 411 EQ_CTRL = 1, 412 EQ_ETH = 2, 413 EQ_OFLD = 3, 414 415 /* eq flags */ 416 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 417 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 418 EQ_ENABLED = (1 << 3), /* open for business */ 419 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 420 }; 421 422 /* Listed in order of preference. Update t4_sysctls too if you change these */ 423 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 424 425 /* 426 * Egress Queue: driver is producer, T4 is consumer. 427 * 428 * Note: A free list is an egress queue (driver produces the buffers and T4 429 * consumes them) but it's special enough to have its own struct (see sge_fl). 430 */ 431 struct sge_eq { 432 unsigned int flags; /* MUST be first */ 433 unsigned int cntxt_id; /* SGE context id for the eq */ 434 unsigned int abs_id; /* absolute SGE id for the eq */ 435 struct mtx eq_lock; 436 437 struct tx_desc *desc; /* KVA of descriptor ring */ 438 uint8_t doorbells; 439 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 440 u_int udb_qid; /* relative qid within the doorbell page */ 441 uint16_t sidx; /* index of the entry with the status page */ 442 uint16_t cidx; /* consumer idx (desc idx) */ 443 uint16_t pidx; /* producer idx (desc idx) */ 444 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 445 uint16_t dbidx; /* pidx of the most recent doorbell */ 446 uint16_t iqid; /* iq that gets egr_update for the eq */ 447 uint8_t tx_chan; /* tx channel used by the eq */ 448 volatile u_int equiq; /* EQUIQ outstanding */ 449 450 bus_dma_tag_t desc_tag; 451 bus_dmamap_t desc_map; 452 bus_addr_t ba; /* bus address of descriptor ring */ 453 char lockname[16]; 454 }; 455 456 struct rx_buf_info { 457 uma_zone_t zone; /* zone that this cluster comes from */ 458 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 459 * hwsize[hwidx1] = size1. No spare. */ 460 uint16_t size2; /* hwsize[hwidx2] = size2. 461 * spare in cluster = size1 - size2. */ 462 int8_t hwidx1; /* SGE bufsize idx for size1 */ 463 int8_t hwidx2; /* SGE bufsize idx for size2 */ 464 uint8_t type; /* EXT_xxx type of the cluster */ 465 }; 466 467 enum { 468 NUM_MEMWIN = 3, 469 470 MEMWIN0_APERTURE = 2048, 471 MEMWIN0_BASE = 0x1b800, 472 473 MEMWIN1_APERTURE = 32768, 474 MEMWIN1_BASE = 0x28000, 475 476 MEMWIN2_APERTURE_T4 = 65536, 477 MEMWIN2_BASE_T4 = 0x30000, 478 479 MEMWIN2_APERTURE_T5 = 128 * 1024, 480 MEMWIN2_BASE_T5 = 0x60000, 481 }; 482 483 struct memwin { 484 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 485 uint32_t mw_base; /* constant after setup_memwin */ 486 uint32_t mw_aperture; /* ditto */ 487 uint32_t mw_curpos; /* protected by mw_lock */ 488 }; 489 490 enum { 491 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 492 FL_DOOMED = (1 << 1), /* about to be destroyed */ 493 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 494 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 495 }; 496 497 #define FL_RUNNING_LOW(fl) \ 498 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 499 #define FL_NOT_RUNNING_LOW(fl) \ 500 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 501 502 struct sge_fl { 503 struct mtx fl_lock; 504 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 505 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 506 uint16_t zidx; /* refill zone idx */ 507 uint16_t safe_zidx; 508 uint16_t lowat; /* # of buffers <= this means fl needs help */ 509 int flags; 510 uint16_t buf_boundary; 511 512 /* The 16b idx all deal with hw descriptors */ 513 uint16_t dbidx; /* hw pidx after last doorbell */ 514 uint16_t sidx; /* index of status page */ 515 volatile uint16_t hw_cidx; 516 517 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 518 uint32_t cidx; /* consumer index */ 519 uint32_t pidx; /* producer index */ 520 521 uint32_t dbval; 522 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 523 volatile uint32_t *udb; 524 525 uint64_t cl_allocated; /* # of clusters allocated */ 526 uint64_t cl_recycled; /* # of clusters recycled */ 527 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 528 529 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 530 struct mbuf *m0; 531 struct mbuf **pnext; 532 u_int remaining; 533 534 uint16_t qsize; /* # of hw descriptors (status page included) */ 535 uint16_t cntxt_id; /* SGE context id for the freelist */ 536 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 537 bus_dma_tag_t desc_tag; 538 bus_dmamap_t desc_map; 539 char lockname[16]; 540 bus_addr_t ba; /* bus address of descriptor ring */ 541 }; 542 543 struct mp_ring; 544 545 struct txpkts { 546 uint8_t wr_type; /* type 0 or type 1 */ 547 uint8_t npkt; /* # of packets in this work request */ 548 uint8_t len16; /* # of 16B pieces used by this work request */ 549 uint8_t score; 550 uint8_t max_npkt; /* maximum number of packets allowed */ 551 uint16_t plen; /* total payload (sum of all packets) */ 552 553 /* straight from fw_eth_tx_pkts_vm_wr. */ 554 __u8 ethmacdst[6]; 555 __u8 ethmacsrc[6]; 556 __be16 ethtype; 557 __be16 vlantci; 558 559 struct mbuf *mb[15]; 560 }; 561 562 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 563 struct sge_txq { 564 struct sge_eq eq; /* MUST be first */ 565 566 struct ifnet *ifp; /* the interface this txq belongs to */ 567 struct mp_ring *r; /* tx software ring */ 568 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 569 struct sglist *gl; 570 __be32 cpl_ctrl0; /* for convenience */ 571 int tc_idx; /* traffic class */ 572 uint64_t last_tx; /* cycle count when eth_tx was last called */ 573 struct txpkts txp; 574 575 struct task tx_reclaim_task; 576 /* stats for common events first */ 577 578 uint64_t txcsum; /* # of times hardware assisted with checksum */ 579 uint64_t tso_wrs; /* # of TSO work requests */ 580 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 581 uint64_t imm_wrs; /* # of work requests with immediate data */ 582 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 583 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 584 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 585 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 586 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 587 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 588 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 589 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 590 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 591 uint64_t vxlan_txcsum; 592 593 uint64_t kern_tls_records; 594 uint64_t kern_tls_short; 595 uint64_t kern_tls_partial; 596 uint64_t kern_tls_full; 597 uint64_t kern_tls_octets; 598 uint64_t kern_tls_waste; 599 uint64_t kern_tls_options; 600 uint64_t kern_tls_header; 601 uint64_t kern_tls_fin; 602 uint64_t kern_tls_fin_short; 603 uint64_t kern_tls_cbc; 604 uint64_t kern_tls_gcm; 605 606 /* stats for not-that-common events */ 607 608 /* Optional scratch space for constructing work requests. */ 609 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 610 } __aligned(CACHE_LINE_SIZE); 611 612 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 613 struct sge_rxq { 614 struct sge_iq iq; /* MUST be first */ 615 struct sge_fl fl; /* MUST follow iq */ 616 617 struct ifnet *ifp; /* the interface this rxq belongs to */ 618 struct lro_ctrl lro; /* LRO state */ 619 620 /* stats for common events first */ 621 622 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 623 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 624 uint64_t vxlan_rxcsum; 625 626 /* stats for not-that-common events */ 627 628 } __aligned(CACHE_LINE_SIZE); 629 630 static inline struct sge_rxq * 631 iq_to_rxq(struct sge_iq *iq) 632 { 633 634 return (__containerof(iq, struct sge_rxq, iq)); 635 } 636 637 638 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 639 struct sge_ofld_rxq { 640 struct sge_iq iq; /* MUST be first */ 641 struct sge_fl fl; /* MUST follow iq */ 642 u_long rx_toe_tls_records; 643 u_long rx_toe_tls_octets; 644 } __aligned(CACHE_LINE_SIZE); 645 646 static inline struct sge_ofld_rxq * 647 iq_to_ofld_rxq(struct sge_iq *iq) 648 { 649 650 return (__containerof(iq, struct sge_ofld_rxq, iq)); 651 } 652 653 struct wrqe { 654 STAILQ_ENTRY(wrqe) link; 655 struct sge_wrq *wrq; 656 int wr_len; 657 char wr[] __aligned(16); 658 }; 659 660 struct wrq_cookie { 661 TAILQ_ENTRY(wrq_cookie) link; 662 int ndesc; 663 int pidx; 664 }; 665 666 /* 667 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 668 * are of this type. 669 */ 670 struct sge_wrq { 671 struct sge_eq eq; /* MUST be first */ 672 673 struct adapter *adapter; 674 struct task wrq_tx_task; 675 676 /* Tx desc reserved but WR not "committed" yet. */ 677 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 678 679 /* List of WRs ready to go out as soon as descriptors are available. */ 680 STAILQ_HEAD(, wrqe) wr_list; 681 u_int nwr_pending; 682 u_int ndesc_needed; 683 684 /* stats for common events first */ 685 686 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 687 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 688 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 689 690 /* stats for not-that-common events */ 691 692 /* 693 * Scratch space for work requests that wrap around after reaching the 694 * status page, and some information about the last WR that used it. 695 */ 696 uint16_t ss_pidx; 697 uint16_t ss_len; 698 uint8_t ss[SGE_MAX_WR_LEN]; 699 700 } __aligned(CACHE_LINE_SIZE); 701 702 /* ofld_txq: SGE egress queue + miscellaneous items */ 703 struct sge_ofld_txq { 704 struct sge_wrq wrq; 705 counter_u64_t tx_iscsi_pdus; 706 counter_u64_t tx_iscsi_octets; 707 counter_u64_t tx_toe_tls_records; 708 counter_u64_t tx_toe_tls_octets; 709 } __aligned(CACHE_LINE_SIZE); 710 711 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 712 struct sge_nm_rxq { 713 /* Items used by the driver rx ithread are in this cacheline. */ 714 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 715 u_int nid; /* netmap ring # for this queue */ 716 struct vi_info *vi; 717 718 struct iq_desc *iq_desc; 719 uint16_t iq_abs_id; 720 uint16_t iq_cntxt_id; 721 uint16_t iq_cidx; 722 uint16_t iq_sidx; 723 uint8_t iq_gen; 724 uint32_t fl_sidx; 725 726 /* Items used by netmap rxsync are in this cacheline. */ 727 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 728 uint16_t fl_cntxt_id; 729 uint32_t fl_pidx; 730 uint32_t fl_sidx2; /* copy of fl_sidx */ 731 uint32_t fl_db_val; 732 u_int fl_db_saved; 733 u_int fl_db_threshold; /* in descriptors */ 734 u_int fl_hwidx:4; 735 736 /* 737 * fl_cidx is used by both the ithread and rxsync, the rest are not used 738 * in the rx fast path. 739 */ 740 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 741 742 bus_dma_tag_t iq_desc_tag; 743 bus_dmamap_t iq_desc_map; 744 bus_addr_t iq_ba; 745 int intr_idx; 746 747 bus_dma_tag_t fl_desc_tag; 748 bus_dmamap_t fl_desc_map; 749 bus_addr_t fl_ba; 750 }; 751 752 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 753 struct sge_nm_txq { 754 struct tx_desc *desc; 755 uint16_t cidx; 756 uint16_t pidx; 757 uint16_t sidx; 758 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 759 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 760 uint16_t dbidx; /* pidx of the most recent doorbell */ 761 uint8_t doorbells; 762 volatile uint32_t *udb; 763 u_int udb_qid; 764 u_int cntxt_id; 765 __be32 cpl_ctrl0; /* for convenience */ 766 __be32 op_pkd; /* ditto */ 767 u_int nid; /* netmap ring # for this queue */ 768 769 /* infrequently used items after this */ 770 771 bus_dma_tag_t desc_tag; 772 bus_dmamap_t desc_map; 773 bus_addr_t ba; 774 int iqidx; 775 } __aligned(CACHE_LINE_SIZE); 776 777 struct sge { 778 int nrxq; /* total # of Ethernet rx queues */ 779 int ntxq; /* total # of Ethernet tx queues */ 780 int nofldrxq; /* total # of TOE rx queues */ 781 int nofldtxq; /* total # of TOE tx queues */ 782 int nnmrxq; /* total # of netmap rx queues */ 783 int nnmtxq; /* total # of netmap tx queues */ 784 int niq; /* total # of ingress queues */ 785 int neq; /* total # of egress queues */ 786 787 struct sge_iq fwq; /* Firmware event queue */ 788 struct sge_wrq *ctrlq; /* Control queues */ 789 struct sge_txq *txq; /* NIC tx queues */ 790 struct sge_rxq *rxq; /* NIC rx queues */ 791 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 792 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 793 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 794 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 795 796 uint16_t iq_start; /* first cntxt_id */ 797 uint16_t iq_base; /* first abs_id */ 798 int eq_start; /* first cntxt_id */ 799 int eq_base; /* first abs_id */ 800 int iqmap_sz; 801 int eqmap_sz; 802 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 803 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 804 805 int8_t safe_zidx; 806 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 807 }; 808 809 struct devnames { 810 const char *nexus_name; 811 const char *ifnet_name; 812 const char *vi_ifnet_name; 813 const char *pf03_drv_name; 814 const char *vf_nexus_name; 815 const char *vf_ifnet_name; 816 }; 817 818 struct clip_entry; 819 820 struct adapter { 821 SLIST_ENTRY(adapter) link; 822 device_t dev; 823 struct cdev *cdev; 824 const struct devnames *names; 825 826 /* PCIe register resources */ 827 int regs_rid; 828 struct resource *regs_res; 829 int msix_rid; 830 struct resource *msix_res; 831 bus_space_handle_t bh; 832 bus_space_tag_t bt; 833 bus_size_t mmio_len; 834 int udbs_rid; 835 struct resource *udbs_res; 836 volatile uint8_t *udbs_base; 837 838 unsigned int pf; 839 unsigned int mbox; 840 unsigned int vpd_busy; 841 unsigned int vpd_flag; 842 843 /* Interrupt information */ 844 int intr_type; 845 int intr_count; 846 struct irq { 847 struct resource *res; 848 int rid; 849 void *tag; 850 struct sge_rxq *rxq; 851 struct sge_nm_rxq *nm_rxq; 852 } __aligned(CACHE_LINE_SIZE) *irq; 853 int sge_gts_reg; 854 int sge_kdoorbell_reg; 855 856 bus_dma_tag_t dmat; /* Parent DMA tag */ 857 858 struct sge sge; 859 int lro_timeout; 860 int sc_do_rxcopy; 861 862 int vxlan_port; 863 u_int vxlan_refcount; 864 int rawf_base; 865 int nrawf; 866 867 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 868 struct task async_event_task; 869 struct port_info *port[MAX_NPORTS]; 870 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 871 872 struct mtx clip_table_lock; 873 TAILQ_HEAD(, clip_entry) clip_table; 874 int clip_gen; 875 876 void *tom_softc; /* (struct tom_data *) */ 877 struct tom_tunables tt; 878 struct t4_offload_policy *policy; 879 struct rwlock policy_lock; 880 881 void *iwarp_softc; /* (struct c4iw_dev *) */ 882 struct iw_tunables iwt; 883 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 884 void *ccr_softc; /* (struct ccr_softc *) */ 885 struct l2t_data *l2t; /* L2 table */ 886 struct smt_data *smt; /* Source MAC Table */ 887 struct tid_info tids; 888 vmem_t *key_map; 889 struct tls_tunables tlst; 890 891 uint8_t doorbells; 892 int offload_map; /* ports with IFCAP_TOE enabled */ 893 int active_ulds; /* ULDs activated on this adapter */ 894 int flags; 895 int debug_flags; 896 897 char ifp_lockname[16]; 898 struct mtx ifp_lock; 899 struct ifnet *ifp; /* tracer ifp */ 900 struct ifmedia media; 901 int traceq; /* iq used by all tracers, -1 if none */ 902 int tracer_valid; /* bitmap of valid tracers */ 903 int tracer_enabled; /* bitmap of enabled tracers */ 904 905 char fw_version[16]; 906 char tp_version[16]; 907 char er_version[16]; 908 char bs_version[16]; 909 char cfg_file[32]; 910 u_int cfcsum; 911 struct adapter_params params; 912 const struct chip_params *chip_params; 913 struct t4_virt_res vres; 914 915 uint16_t nbmcaps; 916 uint16_t linkcaps; 917 uint16_t switchcaps; 918 uint16_t niccaps; 919 uint16_t toecaps; 920 uint16_t rdmacaps; 921 uint16_t cryptocaps; 922 uint16_t iscsicaps; 923 uint16_t fcoecaps; 924 925 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 926 927 struct mtx sc_lock; 928 char lockname[16]; 929 930 /* Starving free lists */ 931 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 932 TAILQ_HEAD(, sge_fl) sfl; 933 struct callout sfl_callout; 934 935 struct mtx reg_lock; /* for indirect register access */ 936 937 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 938 939 struct mtx tc_lock; 940 struct task tc_task; 941 942 const char *last_op; 943 const void *last_op_thr; 944 int last_op_flags; 945 946 int swintr; 947 int sensor_resets; 948 949 struct callout ktls_tick; 950 }; 951 952 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 953 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 954 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 955 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 956 957 #define ASSERT_SYNCHRONIZED_OP(sc) \ 958 KASSERT(IS_BUSY(sc) && \ 959 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 960 ("%s: operation not synchronized.", __func__)) 961 962 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 963 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 964 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 965 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 966 967 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 968 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 969 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 970 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 971 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 972 973 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 974 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 975 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 976 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 977 978 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 979 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 980 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 981 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 982 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 983 984 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 985 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 986 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 987 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 988 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 989 990 #define for_each_txq(vi, iter, q) \ 991 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 992 iter < vi->ntxq; ++iter, ++q) 993 #define for_each_rxq(vi, iter, q) \ 994 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 995 iter < vi->nrxq; ++iter, ++q) 996 #define for_each_ofld_txq(vi, iter, q) \ 997 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 998 iter < vi->nofldtxq; ++iter, ++q) 999 #define for_each_ofld_rxq(vi, iter, q) \ 1000 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1001 iter < vi->nofldrxq; ++iter, ++q) 1002 #define for_each_nm_txq(vi, iter, q) \ 1003 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1004 iter < vi->nnmtxq; ++iter, ++q) 1005 #define for_each_nm_rxq(vi, iter, q) \ 1006 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1007 iter < vi->nnmrxq; ++iter, ++q) 1008 #define for_each_vi(_pi, _iter, _vi) \ 1009 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1010 ++(_iter), ++(_vi)) 1011 1012 #define IDXINCR(idx, incr, wrap) do { \ 1013 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1014 } while (0) 1015 #define IDXDIFF(head, tail, wrap) \ 1016 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1017 1018 /* One for errors, one for firmware events */ 1019 #define T4_EXTRA_INTR 2 1020 1021 /* One for firmware events */ 1022 #define T4VF_EXTRA_INTR 1 1023 1024 static inline int 1025 forwarding_intr_to_fwq(struct adapter *sc) 1026 { 1027 1028 return (sc->intr_count == 1); 1029 } 1030 1031 static inline uint32_t 1032 t4_read_reg(struct adapter *sc, uint32_t reg) 1033 { 1034 1035 return bus_space_read_4(sc->bt, sc->bh, reg); 1036 } 1037 1038 static inline void 1039 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1040 { 1041 1042 bus_space_write_4(sc->bt, sc->bh, reg, val); 1043 } 1044 1045 static inline uint64_t 1046 t4_read_reg64(struct adapter *sc, uint32_t reg) 1047 { 1048 1049 #ifdef __LP64__ 1050 return bus_space_read_8(sc->bt, sc->bh, reg); 1051 #else 1052 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1053 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1054 1055 #endif 1056 } 1057 1058 static inline void 1059 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1060 { 1061 1062 #ifdef __LP64__ 1063 bus_space_write_8(sc->bt, sc->bh, reg, val); 1064 #else 1065 bus_space_write_4(sc->bt, sc->bh, reg, val); 1066 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1067 #endif 1068 } 1069 1070 static inline void 1071 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1072 { 1073 1074 *val = pci_read_config(sc->dev, reg, 1); 1075 } 1076 1077 static inline void 1078 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1079 { 1080 1081 pci_write_config(sc->dev, reg, val, 1); 1082 } 1083 1084 static inline void 1085 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1086 { 1087 1088 *val = pci_read_config(sc->dev, reg, 2); 1089 } 1090 1091 static inline void 1092 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1093 { 1094 1095 pci_write_config(sc->dev, reg, val, 2); 1096 } 1097 1098 static inline void 1099 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1100 { 1101 1102 *val = pci_read_config(sc->dev, reg, 4); 1103 } 1104 1105 static inline void 1106 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1107 { 1108 1109 pci_write_config(sc->dev, reg, val, 4); 1110 } 1111 1112 static inline struct port_info * 1113 adap2pinfo(struct adapter *sc, int idx) 1114 { 1115 1116 return (sc->port[idx]); 1117 } 1118 1119 static inline void 1120 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1121 { 1122 1123 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1124 } 1125 1126 static inline int 1127 tx_resume_threshold(struct sge_eq *eq) 1128 { 1129 1130 /* not quite the same as qsize / 4, but this will do. */ 1131 return (eq->sidx / 4); 1132 } 1133 1134 static inline int 1135 t4_use_ldst(struct adapter *sc) 1136 { 1137 1138 #ifdef notyet 1139 return (sc->flags & FW_OK || !sc->use_bd); 1140 #else 1141 return (0); 1142 #endif 1143 } 1144 1145 static inline void 1146 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1147 const char *msg, const __be64 *const p, const bool err) 1148 { 1149 1150 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1151 return; 1152 if (p != NULL) { 1153 log(err ? LOG_ERR : LOG_DEBUG, 1154 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1155 "%016llx %016llx %016llx %016llx\n", 1156 device_get_nameunit(sc->dev), mbox, msg, 1157 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1158 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1159 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1160 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1161 } else { 1162 log(err ? LOG_ERR : LOG_DEBUG, 1163 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1164 "%016llx %016llx %016llx %016llx\n", 1165 device_get_nameunit(sc->dev), mbox, msg, 1166 (long long)t4_read_reg64(sc, reg), 1167 (long long)t4_read_reg64(sc, reg + 8), 1168 (long long)t4_read_reg64(sc, reg + 16), 1169 (long long)t4_read_reg64(sc, reg + 24), 1170 (long long)t4_read_reg64(sc, reg + 32), 1171 (long long)t4_read_reg64(sc, reg + 40), 1172 (long long)t4_read_reg64(sc, reg + 48), 1173 (long long)t4_read_reg64(sc, reg + 56)); 1174 } 1175 } 1176 1177 /* t4_main.c */ 1178 extern int t4_ntxq; 1179 extern int t4_nrxq; 1180 extern int t4_intr_types; 1181 extern int t4_tmr_idx; 1182 extern int t4_pktc_idx; 1183 extern unsigned int t4_qsize_rxq; 1184 extern unsigned int t4_qsize_txq; 1185 extern device_method_t cxgbe_methods[]; 1186 1187 int t4_os_find_pci_capability(struct adapter *, int); 1188 int t4_os_pci_save_state(struct adapter *); 1189 int t4_os_pci_restore_state(struct adapter *); 1190 void t4_os_portmod_changed(struct port_info *); 1191 void t4_os_link_changed(struct port_info *); 1192 void t4_iterate(void (*)(struct adapter *, void *), void *); 1193 void t4_init_devnames(struct adapter *); 1194 void t4_add_adapter(struct adapter *); 1195 int t4_detach_common(device_t); 1196 int t4_map_bars_0_and_4(struct adapter *); 1197 int t4_map_bar_2(struct adapter *); 1198 int t4_setup_intr_handlers(struct adapter *); 1199 void t4_sysctls(struct adapter *); 1200 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1201 void doom_vi(struct adapter *, struct vi_info *); 1202 void end_synchronized_op(struct adapter *, int); 1203 int update_mac_settings(struct ifnet *, int); 1204 int adapter_full_init(struct adapter *); 1205 int adapter_full_uninit(struct adapter *); 1206 int vi_full_init(struct vi_info *); 1207 int vi_full_uninit(struct vi_info *); 1208 void vi_sysctls(struct vi_info *); 1209 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1210 int alloc_atid(struct adapter *, void *); 1211 void *lookup_atid(struct adapter *, int); 1212 void free_atid(struct adapter *, int); 1213 void release_tid(struct adapter *, int, struct sge_wrq *); 1214 int cxgbe_media_change(struct ifnet *); 1215 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1216 bool t4_os_dump_cimla(struct adapter *, int, bool); 1217 void t4_os_dump_devlog(struct adapter *); 1218 1219 #ifdef KERN_TLS 1220 /* t4_kern_tls.c */ 1221 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1222 struct m_snd_tag **); 1223 void cxgbe_tls_tag_free(struct m_snd_tag *); 1224 void t6_ktls_modload(void); 1225 void t6_ktls_modunload(void); 1226 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1227 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1228 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1229 #endif 1230 1231 /* t4_keyctx.c */ 1232 struct auth_hash; 1233 union authctx; 1234 1235 void t4_aes_getdeckey(void *, const void *, unsigned int); 1236 void t4_copy_partial_hash(int, union authctx *, void *); 1237 void t4_init_gmac_hash(const char *, int, char *); 1238 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *); 1239 1240 #ifdef DEV_NETMAP 1241 /* t4_netmap.c */ 1242 struct sge_nm_rxq; 1243 void cxgbe_nm_attach(struct vi_info *); 1244 void cxgbe_nm_detach(struct vi_info *); 1245 void service_nm_rxq(struct sge_nm_rxq *); 1246 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 1247 struct sysctl_oid *); 1248 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1249 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 1250 struct sysctl_oid *); 1251 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1252 #endif 1253 1254 /* t4_sge.c */ 1255 void t4_sge_modload(void); 1256 void t4_sge_modunload(void); 1257 uint64_t t4_sge_extfree_refs(void); 1258 void t4_tweak_chip_settings(struct adapter *); 1259 int t4_verify_chip_settings(struct adapter *); 1260 void t4_init_rx_buf_info(struct adapter *); 1261 int t4_create_dma_tag(struct adapter *); 1262 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1263 struct sysctl_oid_list *); 1264 int t4_destroy_dma_tag(struct adapter *); 1265 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1266 bus_addr_t *, void **); 1267 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1268 void *); 1269 int t4_setup_adapter_queues(struct adapter *); 1270 int t4_teardown_adapter_queues(struct adapter *); 1271 int t4_setup_vi_queues(struct vi_info *); 1272 int t4_teardown_vi_queues(struct vi_info *); 1273 void t4_intr_all(void *); 1274 void t4_intr(void *); 1275 #ifdef DEV_NETMAP 1276 void t4_nm_intr(void *); 1277 void t4_vi_intr(void *); 1278 #endif 1279 void t4_intr_err(void *); 1280 void t4_intr_evt(void *); 1281 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1282 void t4_update_fl_bufsize(struct ifnet *); 1283 struct mbuf *alloc_wr_mbuf(int, int); 1284 int parse_pkt(struct mbuf **, bool); 1285 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1286 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1287 int tnl_cong(struct port_info *, int); 1288 void t4_register_an_handler(an_handler_t); 1289 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1290 void t4_register_cpl_handler(int, cpl_handler_t); 1291 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1292 #ifdef RATELIMIT 1293 int ethofld_transmit(struct ifnet *, struct mbuf *); 1294 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1295 #endif 1296 1297 /* t4_tracer.c */ 1298 struct t4_tracer; 1299 void t4_tracer_modload(void); 1300 void t4_tracer_modunload(void); 1301 void t4_tracer_port_detach(struct adapter *); 1302 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1303 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1304 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1305 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1306 1307 /* t4_sched.c */ 1308 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1309 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1310 int t4_init_tx_sched(struct adapter *); 1311 int t4_free_tx_sched(struct adapter *); 1312 void t4_update_tx_sched(struct adapter *); 1313 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1314 void t4_release_cl_rl(struct adapter *, int, int); 1315 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1316 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1317 #ifdef RATELIMIT 1318 void t4_init_etid_table(struct adapter *); 1319 void t4_free_etid_table(struct adapter *); 1320 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1321 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1322 struct m_snd_tag **); 1323 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1324 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1325 void cxgbe_rate_tag_free(struct m_snd_tag *); 1326 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1327 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1328 #endif 1329 1330 /* t4_filter.c */ 1331 int get_filter_mode(struct adapter *, uint32_t *); 1332 int set_filter_mode(struct adapter *, uint32_t); 1333 int set_filter_mask(struct adapter *, uint32_t); 1334 int get_filter(struct adapter *, struct t4_filter *); 1335 int set_filter(struct adapter *, struct t4_filter *); 1336 int del_filter(struct adapter *, struct t4_filter *); 1337 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1338 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1339 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1340 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1341 void free_hftid_hash(struct tid_info *); 1342 1343 static inline struct wrqe * 1344 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1345 { 1346 int len = offsetof(struct wrqe, wr) + wr_len; 1347 struct wrqe *wr; 1348 1349 wr = malloc(len, M_CXGBE, M_NOWAIT); 1350 if (__predict_false(wr == NULL)) 1351 return (NULL); 1352 wr->wr_len = wr_len; 1353 wr->wrq = wrq; 1354 return (wr); 1355 } 1356 1357 static inline void * 1358 wrtod(struct wrqe *wr) 1359 { 1360 return (&wr->wr[0]); 1361 } 1362 1363 static inline void 1364 free_wrqe(struct wrqe *wr) 1365 { 1366 free(wr, M_CXGBE); 1367 } 1368 1369 static inline void 1370 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1371 { 1372 struct sge_wrq *wrq = wr->wrq; 1373 1374 TXQ_LOCK(wrq); 1375 t4_wrq_tx_locked(sc, wrq, wr); 1376 TXQ_UNLOCK(wrq); 1377 } 1378 1379 static inline int 1380 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1381 int len) 1382 { 1383 1384 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1385 } 1386 1387 static inline int 1388 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1389 const uint32_t *val, int len) 1390 { 1391 1392 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1393 } 1394 1395 /* Number of len16 -> number of descriptors */ 1396 static inline int 1397 tx_len16_to_desc(int len16) 1398 { 1399 1400 return (howmany(len16, EQ_ESIZE / 16)); 1401 } 1402 #endif 1403