1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 * Written by: Navdeep Parhar <[email protected]>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 *
31 */
32
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
35
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/counter.h>
39 #include <sys/rman.h>
40 #include <sys/types.h>
41 #include <sys/lock.h>
42 #include <sys/malloc.h>
43 #include <sys/rwlock.h>
44 #include <sys/sx.h>
45 #include <sys/vmem.h>
46 #include <vm/uma.h>
47
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <machine/bus.h>
51 #include <sys/socket.h>
52 #include <sys/sysctl.h>
53 #include <sys/taskqueue.h>
54 #include <net/ethernet.h>
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_media.h>
58 #include <net/pfil.h>
59 #include <netinet/in.h>
60 #include <netinet/tcp_lro.h>
61
62 #include "offload.h"
63 #include "t4_ioctl.h"
64 #include "common/t4_msg.h"
65 #include "firmware/t4fw_interface.h"
66
67 #define KTR_CXGBE KTR_SPARE3
68 MALLOC_DECLARE(M_CXGBE);
69 #define CXGBE_UNIMPLEMENTED(s) \
70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
71
72 /*
73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's
74 * LIST_HEAD when building iw_cxgbe.
75 */
76 #define CXGBE_LIST_HEAD(name, type) \
77 struct name { \
78 struct type *lh_first; /* first element */ \
79 }
80
81 #ifndef SYSCTL_ADD_UQUAD
82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
83 #define sysctl_handle_64 sysctl_handle_quad
84 #define CTLTYPE_U64 CTLTYPE_QUAD
85 #endif
86
87 SYSCTL_DECL(_hw_cxgbe);
88
89 struct adapter;
90 typedef struct adapter adapter_t;
91
92 enum {
93 /*
94 * All ingress queues use this entry size. Note that the firmware event
95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
96 * be at least 64.
97 */
98 IQ_ESIZE = 64,
99
100 /* Default queue sizes for all kinds of ingress queues */
101 FW_IQ_QSIZE = 256,
102 RX_IQ_QSIZE = 1024,
103
104 /* All egress queues use this entry size */
105 EQ_ESIZE = 64,
106
107 /* Default queue sizes for all kinds of egress queues */
108 CTRL_EQ_QSIZE = 1024,
109 TX_EQ_QSIZE = 1024,
110
111 #if MJUMPAGESIZE != MCLBYTES
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
113 #else
114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
115 #endif
116 CL_METADATA_SIZE = CACHE_LINE_SIZE,
117
118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
119 TX_SGL_SEGS = 39,
120 TX_SGL_SEGS_TSO = 38,
121 TX_SGL_SEGS_VM = 38,
122 TX_SGL_SEGS_VM_TSO = 37,
123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
124 TX_SGL_SEGS_VXLAN_TSO = 37,
125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
126 };
127
128 enum {
129 /* adapter intr_type */
130 INTR_INTX = (1 << 0),
131 INTR_MSI = (1 << 1),
132 INTR_MSIX = (1 << 2)
133 };
134
135 enum {
136 XGMAC_MTU = (1 << 0),
137 XGMAC_PROMISC = (1 << 1),
138 XGMAC_ALLMULTI = (1 << 2),
139 XGMAC_VLANEX = (1 << 3),
140 XGMAC_UCADDR = (1 << 4),
141 XGMAC_MCADDRS = (1 << 5),
142
143 XGMAC_ALL = 0xffff
144 };
145
146 enum {
147 /* flags understood by begin_synchronized_op */
148 HOLD_LOCK = (1 << 0),
149 SLEEP_OK = (1 << 1),
150 INTR_OK = (1 << 2),
151
152 /* flags understood by end_synchronized_op */
153 LOCK_HELD = HOLD_LOCK,
154 };
155
156 enum {
157 /* adapter flags. synch_op or adapter_lock. */
158 FULL_INIT_DONE = (1 << 0),
159 FW_OK = (1 << 1),
160 CHK_MBOX_ACCESS = (1 << 2),
161 MASTER_PF = (1 << 3),
162 BUF_PACKING_OK = (1 << 6),
163 IS_VF = (1 << 7),
164 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */
165 CXGBE_BUSY = (1 << 9),
166
167 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */
168 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */
169 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */
170 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */
171 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */
172
173 /* port flags */
174 HAS_TRACEQ = (1 << 3),
175 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
176
177 /* VI flags */
178 DOOMED = (1 << 0),
179 VI_INIT_DONE = (1 << 1),
180 /* 1 << 2 is unused, was VI_SYSCTL_CTX */
181 TX_USES_VM_WR = (1 << 3),
182 VI_SKIP_STATS = (1 << 4),
183
184 /* adapter debug_flags */
185 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
186 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
187 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
188 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
189 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
190 };
191
192 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
193 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
194 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
195 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
196 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
197
198 struct vi_info {
199 device_t dev;
200 struct port_info *pi;
201 struct adapter *adapter;
202
203 struct ifnet *ifp;
204 struct pfil_head *pfil;
205
206 unsigned long flags;
207 int if_flags;
208
209 uint16_t *rss, *nm_rss;
210 uint16_t viid; /* opaque VI identifier */
211 uint16_t smt_idx;
212 uint16_t vin;
213 uint8_t vfvld;
214 int16_t xact_addr_filt;/* index of exact MAC address filter */
215 uint16_t rss_size; /* size of VI's RSS table slice */
216 uint16_t rss_base; /* start of VI's RSS table slice */
217 int hashen;
218
219 int nintr;
220 int first_intr;
221
222 /* These need to be int as they are used in sysctl */
223 int ntxq; /* # of tx queues */
224 int first_txq; /* index of first tx queue */
225 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
226 int nrxq; /* # of rx queues */
227 int first_rxq; /* index of first rx queue */
228 int nofldtxq; /* # of offload tx queues */
229 int first_ofld_txq; /* index of first offload tx queue */
230 int nofldrxq; /* # of offload rx queues */
231 int first_ofld_rxq; /* index of first offload rx queue */
232 int nnmtxq;
233 int first_nm_txq;
234 int nnmrxq;
235 int first_nm_rxq;
236 int tmr_idx;
237 int ofld_tmr_idx;
238 int pktc_idx;
239 int ofld_pktc_idx;
240 int qsize_rxq;
241 int qsize_txq;
242
243 struct timeval last_refreshed;
244 struct fw_vi_stats_vf stats;
245 struct mtx tick_mtx;
246 struct callout tick;
247
248 struct sysctl_ctx_list ctx;
249 struct sysctl_oid *rxq_oid;
250 struct sysctl_oid *txq_oid;
251 struct sysctl_oid *nm_rxq_oid;
252 struct sysctl_oid *nm_txq_oid;
253 struct sysctl_oid *ofld_rxq_oid;
254 struct sysctl_oid *ofld_txq_oid;
255
256 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
257 };
258
259 struct tx_ch_rl_params {
260 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
261 uint32_t maxrate;
262 };
263
264 /* CLRL state */
265 enum clrl_state {
266 CS_UNINITIALIZED = 0,
267 CS_PARAMS_SET, /* sw parameters have been set. */
268 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */
269 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */
270 CS_HW_CONFIGURED /* configured in the hardware. */
271 };
272
273 /* CLRL flags */
274 enum {
275 CF_USER = (1 << 0), /* was configured by driver ioctl. */
276 };
277
278 struct tx_cl_rl_params {
279 enum clrl_state state;
280 int refcount;
281 uint8_t flags;
282 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
283 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
284 enum fw_sched_params_mode mode; /* aggr or per-flow */
285 uint32_t maxrate;
286 uint16_t pktsize;
287 uint16_t burstsize;
288 };
289
290 /* Tx scheduler parameters for a channel/port */
291 struct tx_sched_params {
292 /* Channel Rate Limiter */
293 struct tx_ch_rl_params ch_rl;
294
295 /* Class WRR */
296 /* XXX */
297
298 /* Class Rate Limiter (including the default pktsize and burstsize). */
299 int pktsize;
300 int burstsize;
301 struct tx_cl_rl_params cl_rl[];
302 };
303
304 struct port_info {
305 device_t dev;
306 struct adapter *adapter;
307
308 struct vi_info *vi;
309 int nvi;
310 int up_vis;
311 int uld_vis;
312 bool vxlan_tcam_entry;
313
314 struct tx_sched_params *sched_params;
315
316 struct mtx pi_lock;
317 char lockname[16];
318 unsigned long flags;
319
320 uint8_t lport; /* associated offload logical port */
321 int8_t mdio_addr;
322 uint8_t port_type;
323 uint8_t mod_type;
324 uint8_t port_id;
325 uint8_t tx_chan;
326 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
327 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
328 uint8_t rx_c_chan; /* rx TP c-channel */
329
330 struct link_config link_cfg;
331 struct ifmedia media;
332
333 struct port_stats stats;
334 u_int tnl_cong_drops;
335 u_int tx_parse_error;
336 int fcs_reg;
337 uint64_t fcs_base;
338
339 struct sysctl_ctx_list ctx;
340 };
341
342 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
343
344 struct cluster_metadata {
345 uma_zone_t zone;
346 caddr_t cl;
347 u_int refcount;
348 };
349
350 struct fl_sdesc {
351 caddr_t cl;
352 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
353 int16_t moff; /* offset of metadata from cl */
354 uint8_t zidx;
355 };
356
357 struct tx_desc {
358 __be64 flit[8];
359 };
360
361 struct tx_sdesc {
362 struct mbuf *m; /* m_nextpkt linked chain of frames */
363 uint8_t desc_used; /* # of hardware descriptors used by the WR */
364 };
365
366
367 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
368 struct iq_desc {
369 struct rss_header rss;
370 uint8_t cpl[IQ_PAD];
371 struct rsp_ctrl rsp;
372 };
373 #undef IQ_PAD
374 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
375
376 enum {
377 /* iq flags */
378 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
379 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
380 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
381 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
382 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
383 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */
384
385 /* iq state */
386 IQS_DISABLED = 0,
387 IQS_BUSY = 1,
388 IQS_IDLE = 2,
389
390 /* netmap related flags */
391 NM_OFF = 0,
392 NM_ON = 1,
393 NM_BUSY = 2,
394 };
395
396 enum {
397 CPL_COOKIE_RESERVED = 0,
398 CPL_COOKIE_FILTER,
399 CPL_COOKIE_DDP0,
400 CPL_COOKIE_DDP1,
401 CPL_COOKIE_TOM,
402 CPL_COOKIE_HASHFILTER,
403 CPL_COOKIE_ETHOFLD,
404 CPL_COOKIE_KERN_TLS,
405
406 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
407 };
408
409 struct sge_iq;
410 struct rss_header;
411 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
412 struct mbuf *);
413 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
414 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
415
416 /*
417 * Ingress Queue: T4 is producer, driver is consumer.
418 */
419 struct sge_iq {
420 uint32_t flags;
421 volatile int state;
422 struct adapter *adapter;
423 struct iq_desc *desc; /* KVA of descriptor ring */
424 int8_t intr_pktc_idx; /* packet count threshold index */
425 uint8_t gen; /* generation bit */
426 uint8_t intr_params; /* interrupt holdoff parameters */
427 int8_t cong; /* congestion settings */
428 uint16_t qsize; /* size (# of entries) of the queue */
429 uint16_t sidx; /* index of the entry with the status page */
430 uint16_t cidx; /* consumer index */
431 uint16_t cntxt_id; /* SGE context id for the iq */
432 uint16_t abs_id; /* absolute SGE id for the iq */
433 int16_t intr_idx; /* interrupt used by the queue */
434
435 STAILQ_ENTRY(sge_iq) link;
436
437 bus_dma_tag_t desc_tag;
438 bus_dmamap_t desc_map;
439 bus_addr_t ba; /* bus address of descriptor ring */
440 };
441
442 enum {
443 /* eq type */
444 EQ_CTRL = 1,
445 EQ_ETH = 2,
446 EQ_OFLD = 3,
447
448 /* eq flags */
449 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
450 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */
451 EQ_ENABLED = (1 << 3), /* open for business */
452 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
453 };
454
455 /* Listed in order of preference. Update t4_sysctls too if you change these */
456 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
457
458 /*
459 * Egress Queue: driver is producer, T4 is consumer.
460 *
461 * Note: A free list is an egress queue (driver produces the buffers and T4
462 * consumes them) but it's special enough to have its own struct (see sge_fl).
463 */
464 struct sge_eq {
465 unsigned int flags; /* MUST be first */
466 unsigned int cntxt_id; /* SGE context id for the eq */
467 unsigned int abs_id; /* absolute SGE id for the eq */
468 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */
469 uint8_t doorbells;
470 uint8_t tx_chan; /* tx channel used by the eq */
471 struct mtx eq_lock;
472
473 struct tx_desc *desc; /* KVA of descriptor ring */
474 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
475 u_int udb_qid; /* relative qid within the doorbell page */
476 uint16_t sidx; /* index of the entry with the status page */
477 uint16_t cidx; /* consumer idx (desc idx) */
478 uint16_t pidx; /* producer idx (desc idx) */
479 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
480 uint16_t dbidx; /* pidx of the most recent doorbell */
481 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */
482 volatile u_int equiq; /* EQUIQ outstanding */
483 struct sge_iq *iq; /* iq that receives egr_update for the eq */
484
485 bus_dma_tag_t desc_tag;
486 bus_dmamap_t desc_map;
487 bus_addr_t ba; /* bus address of descriptor ring */
488 char lockname[16];
489 };
490
491 struct rx_buf_info {
492 uma_zone_t zone; /* zone that this cluster comes from */
493 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
494 * hwsize[hwidx1] = size1. No spare. */
495 uint16_t size2; /* hwsize[hwidx2] = size2.
496 * spare in cluster = size1 - size2. */
497 int8_t hwidx1; /* SGE bufsize idx for size1 */
498 int8_t hwidx2; /* SGE bufsize idx for size2 */
499 uint8_t type; /* EXT_xxx type of the cluster */
500 };
501
502 enum {
503 NUM_MEMWIN = 3,
504
505 MEMWIN0_APERTURE = 2048,
506 MEMWIN0_BASE = 0x1b800,
507
508 MEMWIN1_APERTURE = 32768,
509 MEMWIN1_BASE = 0x28000,
510
511 MEMWIN2_APERTURE_T4 = 65536,
512 MEMWIN2_BASE_T4 = 0x30000,
513
514 MEMWIN2_APERTURE_T5 = 128 * 1024,
515 MEMWIN2_BASE_T5 = 0x60000,
516 };
517
518 struct memwin {
519 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
520 uint32_t mw_base; /* constant after setup_memwin */
521 uint32_t mw_aperture; /* ditto */
522 uint32_t mw_curpos; /* protected by mw_lock */
523 };
524
525 enum {
526 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
527 FL_DOOMED = (1 << 1), /* about to be destroyed */
528 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
529 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
530 };
531
532 #define FL_RUNNING_LOW(fl) \
533 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
534 #define FL_NOT_RUNNING_LOW(fl) \
535 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
536
537 struct sge_fl {
538 struct mtx fl_lock;
539 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
540 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
541 uint16_t zidx; /* refill zone idx */
542 uint16_t safe_zidx;
543 uint16_t lowat; /* # of buffers <= this means fl needs help */
544 int flags;
545 uint16_t buf_boundary;
546
547 /* The 16b idx all deal with hw descriptors */
548 uint16_t dbidx; /* hw pidx after last doorbell */
549 uint16_t sidx; /* index of status page */
550 volatile uint16_t hw_cidx;
551
552 /* The 32b idx are all buffer idx, not hardware descriptor idx */
553 uint32_t cidx; /* consumer index */
554 uint32_t pidx; /* producer index */
555
556 uint32_t dbval;
557 u_int rx_offset; /* offset in fl buf (when buffer packing) */
558 volatile uint32_t *udb;
559
560 uint64_t cl_allocated; /* # of clusters allocated */
561 uint64_t cl_recycled; /* # of clusters recycled */
562 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
563
564 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
565 struct mbuf *m0;
566 struct mbuf **pnext;
567 u_int remaining;
568
569 uint16_t qsize; /* # of hw descriptors (status page included) */
570 uint16_t cntxt_id; /* SGE context id for the freelist */
571 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
572 bus_dma_tag_t desc_tag;
573 bus_dmamap_t desc_map;
574 char lockname[16];
575 bus_addr_t ba; /* bus address of descriptor ring */
576 };
577
578 struct mp_ring;
579
580 struct txpkts {
581 uint8_t wr_type; /* type 0 or type 1 */
582 uint8_t npkt; /* # of packets in this work request */
583 uint8_t len16; /* # of 16B pieces used by this work request */
584 uint8_t score;
585 uint8_t max_npkt; /* maximum number of packets allowed */
586 uint16_t plen; /* total payload (sum of all packets) */
587
588 /* straight from fw_eth_tx_pkts_vm_wr. */
589 __u8 ethmacdst[6];
590 __u8 ethmacsrc[6];
591 __be16 ethtype;
592 __be16 vlantci;
593
594 struct mbuf *mb[15];
595 };
596
597 /* txq: SGE egress queue + what's needed for Ethernet NIC */
598 struct sge_txq {
599 struct sge_eq eq; /* MUST be first */
600
601 struct ifnet *ifp; /* the interface this txq belongs to */
602 struct mp_ring *r; /* tx software ring */
603 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
604 struct sglist *gl;
605 __be32 cpl_ctrl0; /* for convenience */
606 int tc_idx; /* traffic class */
607 uint64_t last_tx; /* cycle count when eth_tx was last called */
608 struct txpkts txp;
609
610 struct task tx_reclaim_task;
611 /* stats for common events first */
612
613 uint64_t txcsum; /* # of times hardware assisted with checksum */
614 uint64_t tso_wrs; /* # of TSO work requests */
615 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
616 uint64_t imm_wrs; /* # of work requests with immediate data */
617 uint64_t sgl_wrs; /* # of work requests with direct SGL */
618 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
619 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
620 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
621 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
622 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
623 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */
624 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
625 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */
626 uint64_t vxlan_txcsum;
627
628 uint64_t kern_tls_records;
629 uint64_t kern_tls_short;
630 uint64_t kern_tls_partial;
631 uint64_t kern_tls_full;
632 uint64_t kern_tls_octets;
633 uint64_t kern_tls_waste;
634 uint64_t kern_tls_options;
635 uint64_t kern_tls_header;
636 uint64_t kern_tls_fin;
637 uint64_t kern_tls_fin_short;
638 uint64_t kern_tls_cbc;
639 uint64_t kern_tls_gcm;
640
641 /* stats for not-that-common events */
642
643 /* Optional scratch space for constructing work requests. */
644 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
645 } __aligned(CACHE_LINE_SIZE);
646
647 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
648 struct sge_rxq {
649 struct sge_iq iq; /* MUST be first */
650 struct sge_fl fl; /* MUST follow iq */
651
652 struct ifnet *ifp; /* the interface this rxq belongs to */
653 struct lro_ctrl lro; /* LRO state */
654
655 /* stats for common events first */
656
657 uint64_t rxcsum; /* # of times hardware assisted with checksum */
658 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
659 uint64_t vxlan_rxcsum;
660
661 /* stats for not-that-common events */
662
663 } __aligned(CACHE_LINE_SIZE);
664
665 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)666 iq_to_rxq(struct sge_iq *iq)
667 {
668
669 return (__containerof(iq, struct sge_rxq, iq));
670 }
671
672 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
673 struct sge_ofld_rxq {
674 struct sge_iq iq; /* MUST be first */
675 struct sge_fl fl; /* MUST follow iq */
676 counter_u64_t rx_iscsi_ddp_setup_ok;
677 counter_u64_t rx_iscsi_ddp_setup_error;
678 uint64_t rx_iscsi_ddp_pdus;
679 uint64_t rx_iscsi_ddp_octets;
680 uint64_t rx_iscsi_fl_pdus;
681 uint64_t rx_iscsi_fl_octets;
682 uint64_t rx_iscsi_padding_errors;
683 uint64_t rx_iscsi_header_digest_errors;
684 uint64_t rx_iscsi_data_digest_errors;
685 u_long rx_toe_tls_records;
686 u_long rx_toe_tls_octets;
687 } __aligned(CACHE_LINE_SIZE);
688
689 static inline struct sge_ofld_rxq *
iq_to_ofld_rxq(struct sge_iq * iq)690 iq_to_ofld_rxq(struct sge_iq *iq)
691 {
692
693 return (__containerof(iq, struct sge_ofld_rxq, iq));
694 }
695
696 struct wrqe {
697 STAILQ_ENTRY(wrqe) link;
698 struct sge_wrq *wrq;
699 int wr_len;
700 char wr[] __aligned(16);
701 };
702
703 struct wrq_cookie {
704 TAILQ_ENTRY(wrq_cookie) link;
705 int ndesc;
706 int pidx;
707 };
708
709 /*
710 * wrq: SGE egress queue that is given prebuilt work requests. Control queues
711 * are of this type.
712 */
713 struct sge_wrq {
714 struct sge_eq eq; /* MUST be first */
715
716 struct adapter *adapter;
717 struct task wrq_tx_task;
718
719 /* Tx desc reserved but WR not "committed" yet. */
720 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
721
722 /* List of WRs ready to go out as soon as descriptors are available. */
723 STAILQ_HEAD(, wrqe) wr_list;
724 u_int nwr_pending;
725 u_int ndesc_needed;
726
727 /* stats for common events first */
728
729 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
730 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
731 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
732
733 /* stats for not-that-common events */
734
735 /*
736 * Scratch space for work requests that wrap around after reaching the
737 * status page, and some information about the last WR that used it.
738 */
739 uint16_t ss_pidx;
740 uint16_t ss_len;
741 uint8_t ss[SGE_MAX_WR_LEN];
742
743 } __aligned(CACHE_LINE_SIZE);
744
745 /* ofld_txq: SGE egress queue + miscellaneous items */
746 struct sge_ofld_txq {
747 struct sge_wrq wrq;
748 counter_u64_t tx_iscsi_pdus;
749 counter_u64_t tx_iscsi_octets;
750 counter_u64_t tx_iscsi_iso_wrs;
751 counter_u64_t tx_toe_tls_records;
752 counter_u64_t tx_toe_tls_octets;
753 } __aligned(CACHE_LINE_SIZE);
754
755 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
756 struct sge_nm_rxq {
757 /* Items used by the driver rx ithread are in this cacheline. */
758 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
759 u_int nid; /* netmap ring # for this queue */
760 struct vi_info *vi;
761
762 struct iq_desc *iq_desc;
763 uint16_t iq_abs_id;
764 uint16_t iq_cntxt_id;
765 uint16_t iq_cidx;
766 uint16_t iq_sidx;
767 uint8_t iq_gen;
768 uint32_t fl_sidx;
769
770 /* Items used by netmap rxsync are in this cacheline. */
771 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
772 uint16_t fl_cntxt_id;
773 uint32_t fl_pidx;
774 uint32_t fl_sidx2; /* copy of fl_sidx */
775 uint32_t fl_db_val;
776 u_int fl_db_saved;
777 u_int fl_db_threshold; /* in descriptors */
778 u_int fl_hwidx:4;
779
780 /*
781 * fl_cidx is used by both the ithread and rxsync, the rest are not used
782 * in the rx fast path.
783 */
784 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
785
786 bus_dma_tag_t iq_desc_tag;
787 bus_dmamap_t iq_desc_map;
788 bus_addr_t iq_ba;
789 int intr_idx;
790
791 bus_dma_tag_t fl_desc_tag;
792 bus_dmamap_t fl_desc_map;
793 bus_addr_t fl_ba;
794 };
795
796 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
797 struct sge_nm_txq {
798 struct tx_desc *desc;
799 uint16_t cidx;
800 uint16_t pidx;
801 uint16_t sidx;
802 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
803 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
804 uint16_t dbidx; /* pidx of the most recent doorbell */
805 uint8_t doorbells;
806 volatile uint32_t *udb;
807 u_int udb_qid;
808 u_int cntxt_id;
809 __be32 cpl_ctrl0; /* for convenience */
810 __be32 op_pkd; /* ditto */
811 u_int nid; /* netmap ring # for this queue */
812
813 /* infrequently used items after this */
814
815 bus_dma_tag_t desc_tag;
816 bus_dmamap_t desc_map;
817 bus_addr_t ba;
818 int iqidx;
819 } __aligned(CACHE_LINE_SIZE);
820
821 struct sge {
822 int nrxq; /* total # of Ethernet rx queues */
823 int ntxq; /* total # of Ethernet tx queues */
824 int nofldrxq; /* total # of TOE rx queues */
825 int nofldtxq; /* total # of TOE tx queues */
826 int nnmrxq; /* total # of netmap rx queues */
827 int nnmtxq; /* total # of netmap tx queues */
828 int niq; /* total # of ingress queues */
829 int neq; /* total # of egress queues */
830
831 struct sge_iq fwq; /* Firmware event queue */
832 struct sge_wrq *ctrlq; /* Control queues */
833 struct sge_txq *txq; /* NIC tx queues */
834 struct sge_rxq *rxq; /* NIC rx queues */
835 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */
836 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
837 struct sge_nm_txq *nm_txq; /* netmap tx queues */
838 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
839
840 uint16_t iq_start; /* first cntxt_id */
841 uint16_t iq_base; /* first abs_id */
842 int eq_start; /* first cntxt_id */
843 int eq_base; /* first abs_id */
844 int iqmap_sz;
845 int eqmap_sz;
846 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
847 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
848
849 int8_t safe_zidx;
850 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
851 };
852
853 struct devnames {
854 const char *nexus_name;
855 const char *ifnet_name;
856 const char *vi_ifnet_name;
857 const char *pf03_drv_name;
858 const char *vf_nexus_name;
859 const char *vf_ifnet_name;
860 };
861
862 struct clip_entry;
863
864 struct adapter {
865 SLIST_ENTRY(adapter) link;
866 device_t dev;
867 struct cdev *cdev;
868 const struct devnames *names;
869
870 /* PCIe register resources */
871 int regs_rid;
872 struct resource *regs_res;
873 int msix_rid;
874 struct resource *msix_res;
875 bus_space_handle_t bh;
876 bus_space_tag_t bt;
877 bus_size_t mmio_len;
878 int udbs_rid;
879 struct resource *udbs_res;
880 volatile uint8_t *udbs_base;
881
882 unsigned int pf;
883 unsigned int mbox;
884 unsigned int vpd_busy;
885 unsigned int vpd_flag;
886
887 /* Interrupt information */
888 int intr_type;
889 int intr_count;
890 struct irq {
891 struct resource *res;
892 int rid;
893 void *tag;
894 struct sge_rxq *rxq;
895 struct sge_nm_rxq *nm_rxq;
896 } __aligned(CACHE_LINE_SIZE) *irq;
897 int sge_gts_reg;
898 int sge_kdoorbell_reg;
899
900 bus_dma_tag_t dmat; /* Parent DMA tag */
901
902 struct sge sge;
903 int lro_timeout;
904 int sc_do_rxcopy;
905
906 int vxlan_port;
907 u_int vxlan_refcount;
908 int rawf_base;
909 int nrawf;
910
911 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
912 struct port_info *port[MAX_NPORTS];
913 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
914
915 CXGBE_LIST_HEAD(, clip_entry) *clip_table;
916 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */
917 u_long clip_mask;
918 int clip_gen;
919 struct timeout_task clip_task;
920
921 void *tom_softc; /* (struct tom_data *) */
922 struct tom_tunables tt;
923 struct t4_offload_policy *policy;
924 struct rwlock policy_lock;
925
926 void *iwarp_softc; /* (struct c4iw_dev *) */
927 struct iw_tunables iwt;
928 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
929 void *ccr_softc; /* (struct ccr_softc *) */
930 struct l2t_data *l2t; /* L2 table */
931 struct smt_data *smt; /* Source MAC Table */
932 struct tid_info tids;
933 vmem_t *key_map;
934 struct tls_tunables tlst;
935
936 uint8_t doorbells;
937 int offload_map; /* port_id's with IFCAP_TOE enabled */
938 int bt_map; /* tx_chan's with BASE-T */
939 int active_ulds; /* ULDs activated on this adapter */
940 int flags;
941 int debug_flags;
942 int error_flags; /* Used by error handler and live reset. */
943
944 char ifp_lockname[16];
945 struct mtx ifp_lock;
946 struct ifnet *ifp; /* tracer ifp */
947 struct ifmedia media;
948 int traceq; /* iq used by all tracers, -1 if none */
949 int tracer_valid; /* bitmap of valid tracers */
950 int tracer_enabled; /* bitmap of enabled tracers */
951
952 char fw_version[16];
953 char tp_version[16];
954 char er_version[16];
955 char bs_version[16];
956 char cfg_file[32];
957 u_int cfcsum;
958 struct adapter_params params;
959 const struct chip_params *chip_params;
960 struct t4_virt_res vres;
961
962 uint16_t nbmcaps;
963 uint16_t linkcaps;
964 uint16_t switchcaps;
965 uint16_t niccaps;
966 uint16_t toecaps;
967 uint16_t rdmacaps;
968 uint16_t cryptocaps;
969 uint16_t iscsicaps;
970 uint16_t fcoecaps;
971
972 struct sysctl_ctx_list ctx;
973 struct sysctl_oid *ctrlq_oid;
974 struct sysctl_oid *fwq_oid;
975
976 struct mtx sc_lock;
977 char lockname[16];
978
979 /* Starving free lists */
980 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
981 TAILQ_HEAD(, sge_fl) sfl;
982 struct callout sfl_callout;
983
984 /*
985 * Driver code that can run when the adapter is suspended must use this
986 * lock or a synchronized_op and check for HW_OFF_LIMITS before
987 * accessing hardware.
988 *
989 * XXX: could be changed to rwlock. wlock in suspend/resume and for
990 * indirect register access, rlock everywhere else.
991 */
992 struct mtx reg_lock;
993
994 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
995
996 struct mtx tc_lock;
997 struct task tc_task;
998
999 struct task fatal_error_task;
1000 struct task reset_task;
1001 const void *reset_thread;
1002 int num_resets;
1003 int incarnation;
1004
1005 const char *last_op;
1006 const void *last_op_thr;
1007 int last_op_flags;
1008
1009 int swintr;
1010 int sensor_resets;
1011
1012 struct callout ktls_tick;
1013 };
1014
1015 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
1016 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
1017 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
1018 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
1019
1020 #define ASSERT_SYNCHRONIZED_OP(sc) \
1021 KASSERT(IS_BUSY(sc) && \
1022 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
1023 ("%s: operation not synchronized.", __func__))
1024
1025 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
1026 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
1027 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
1028 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
1029
1030 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
1031 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
1032 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
1033 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
1034 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
1035
1036 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
1037 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
1038 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
1039 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
1040
1041 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
1042 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
1043 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
1044 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
1045 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
1046
1047 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
1048 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
1049 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
1050 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
1051 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
1052
1053 #define for_each_txq(vi, iter, q) \
1054 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
1055 iter < vi->ntxq; ++iter, ++q)
1056 #define for_each_rxq(vi, iter, q) \
1057 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
1058 iter < vi->nrxq; ++iter, ++q)
1059 #define for_each_ofld_txq(vi, iter, q) \
1060 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
1061 iter < vi->nofldtxq; ++iter, ++q)
1062 #define for_each_ofld_rxq(vi, iter, q) \
1063 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
1064 iter < vi->nofldrxq; ++iter, ++q)
1065 #define for_each_nm_txq(vi, iter, q) \
1066 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
1067 iter < vi->nnmtxq; ++iter, ++q)
1068 #define for_each_nm_rxq(vi, iter, q) \
1069 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
1070 iter < vi->nnmrxq; ++iter, ++q)
1071 #define for_each_vi(_pi, _iter, _vi) \
1072 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
1073 ++(_iter), ++(_vi))
1074
1075 #define IDXINCR(idx, incr, wrap) do { \
1076 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1077 } while (0)
1078 #define IDXDIFF(head, tail, wrap) \
1079 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1080
1081 /* One for errors, one for firmware events */
1082 #define T4_EXTRA_INTR 2
1083
1084 /* One for firmware events */
1085 #define T4VF_EXTRA_INTR 1
1086
1087 static inline int
forwarding_intr_to_fwq(struct adapter * sc)1088 forwarding_intr_to_fwq(struct adapter *sc)
1089 {
1090
1091 return (sc->intr_count == 1);
1092 }
1093
1094 /* Works reliably inside a sync_op or with reg_lock held. */
1095 static inline bool
hw_off_limits(struct adapter * sc)1096 hw_off_limits(struct adapter *sc)
1097 {
1098 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS;
1099
1100 return (__predict_false(off_limits != 0));
1101 }
1102
1103 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)1104 t4_read_reg(struct adapter *sc, uint32_t reg)
1105 {
1106 if (hw_off_limits(sc))
1107 MPASS(curthread == sc->reset_thread);
1108 return bus_space_read_4(sc->bt, sc->bh, reg);
1109 }
1110
1111 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)1112 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1113 {
1114 if (hw_off_limits(sc))
1115 MPASS(curthread == sc->reset_thread);
1116 bus_space_write_4(sc->bt, sc->bh, reg, val);
1117 }
1118
1119 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)1120 t4_read_reg64(struct adapter *sc, uint32_t reg)
1121 {
1122 if (hw_off_limits(sc))
1123 MPASS(curthread == sc->reset_thread);
1124 #ifdef __LP64__
1125 return bus_space_read_8(sc->bt, sc->bh, reg);
1126 #else
1127 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1128 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1129
1130 #endif
1131 }
1132
1133 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)1134 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1135 {
1136 if (hw_off_limits(sc))
1137 MPASS(curthread == sc->reset_thread);
1138 #ifdef __LP64__
1139 bus_space_write_8(sc->bt, sc->bh, reg, val);
1140 #else
1141 bus_space_write_4(sc->bt, sc->bh, reg, val);
1142 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1143 #endif
1144 }
1145
1146 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)1147 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1148 {
1149 if (hw_off_limits(sc))
1150 MPASS(curthread == sc->reset_thread);
1151 *val = pci_read_config(sc->dev, reg, 1);
1152 }
1153
1154 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)1155 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1156 {
1157 if (hw_off_limits(sc))
1158 MPASS(curthread == sc->reset_thread);
1159 pci_write_config(sc->dev, reg, val, 1);
1160 }
1161
1162 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)1163 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1164 {
1165
1166 if (hw_off_limits(sc))
1167 MPASS(curthread == sc->reset_thread);
1168 *val = pci_read_config(sc->dev, reg, 2);
1169 }
1170
1171 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)1172 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1173 {
1174 if (hw_off_limits(sc))
1175 MPASS(curthread == sc->reset_thread);
1176 pci_write_config(sc->dev, reg, val, 2);
1177 }
1178
1179 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)1180 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1181 {
1182 if (hw_off_limits(sc))
1183 MPASS(curthread == sc->reset_thread);
1184 *val = pci_read_config(sc->dev, reg, 4);
1185 }
1186
1187 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)1188 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1189 {
1190 if (hw_off_limits(sc))
1191 MPASS(curthread == sc->reset_thread);
1192 pci_write_config(sc->dev, reg, val, 4);
1193 }
1194
1195 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)1196 adap2pinfo(struct adapter *sc, int idx)
1197 {
1198
1199 return (sc->port[idx]);
1200 }
1201
1202 static inline void
t4_os_set_hw_addr(struct port_info * pi,uint8_t hw_addr[])1203 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1204 {
1205
1206 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1207 }
1208
1209 static inline int
tx_resume_threshold(struct sge_eq * eq)1210 tx_resume_threshold(struct sge_eq *eq)
1211 {
1212
1213 /* not quite the same as qsize / 4, but this will do. */
1214 return (eq->sidx / 4);
1215 }
1216
1217 static inline int
t4_use_ldst(struct adapter * sc)1218 t4_use_ldst(struct adapter *sc)
1219 {
1220
1221 #ifdef notyet
1222 return (sc->flags & FW_OK || !sc->use_bd);
1223 #else
1224 return (0);
1225 #endif
1226 }
1227
1228 static inline void
CH_DUMP_MBOX(struct adapter * sc,int mbox,const int reg,const char * msg,const __be64 * const p,const bool err)1229 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1230 const char *msg, const __be64 *const p, const bool err)
1231 {
1232
1233 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1234 return;
1235 if (p != NULL) {
1236 log(err ? LOG_ERR : LOG_DEBUG,
1237 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1238 "%016llx %016llx %016llx %016llx\n",
1239 device_get_nameunit(sc->dev), mbox, msg,
1240 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1241 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1242 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1243 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1244 } else {
1245 log(err ? LOG_ERR : LOG_DEBUG,
1246 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1247 "%016llx %016llx %016llx %016llx\n",
1248 device_get_nameunit(sc->dev), mbox, msg,
1249 (long long)t4_read_reg64(sc, reg),
1250 (long long)t4_read_reg64(sc, reg + 8),
1251 (long long)t4_read_reg64(sc, reg + 16),
1252 (long long)t4_read_reg64(sc, reg + 24),
1253 (long long)t4_read_reg64(sc, reg + 32),
1254 (long long)t4_read_reg64(sc, reg + 40),
1255 (long long)t4_read_reg64(sc, reg + 48),
1256 (long long)t4_read_reg64(sc, reg + 56));
1257 }
1258 }
1259
1260 /* t4_main.c */
1261 extern int t4_ntxq;
1262 extern int t4_nrxq;
1263 extern int t4_intr_types;
1264 extern int t4_tmr_idx;
1265 extern int t4_pktc_idx;
1266 extern unsigned int t4_qsize_rxq;
1267 extern unsigned int t4_qsize_txq;
1268 extern device_method_t cxgbe_methods[];
1269
1270 int t4_os_find_pci_capability(struct adapter *, int);
1271 int t4_os_pci_save_state(struct adapter *);
1272 int t4_os_pci_restore_state(struct adapter *);
1273 void t4_os_portmod_changed(struct port_info *);
1274 void t4_os_link_changed(struct port_info *);
1275 void t4_iterate(void (*)(struct adapter *, void *), void *);
1276 void t4_init_devnames(struct adapter *);
1277 void t4_add_adapter(struct adapter *);
1278 int t4_detach_common(device_t);
1279 int t4_map_bars_0_and_4(struct adapter *);
1280 int t4_map_bar_2(struct adapter *);
1281 int t4_setup_intr_handlers(struct adapter *);
1282 void t4_sysctls(struct adapter *);
1283 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1284 void doom_vi(struct adapter *, struct vi_info *);
1285 void end_synchronized_op(struct adapter *, int);
1286 int update_mac_settings(struct ifnet *, int);
1287 int adapter_init(struct adapter *);
1288 int vi_init(struct vi_info *);
1289 void vi_sysctls(struct vi_info *);
1290 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1291 int alloc_atid(struct adapter *, void *);
1292 void *lookup_atid(struct adapter *, int);
1293 void free_atid(struct adapter *, int);
1294 void release_tid(struct adapter *, int, struct sge_wrq *);
1295 int cxgbe_media_change(struct ifnet *);
1296 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1297 void t4_os_cim_err(struct adapter *);
1298
1299 #ifdef KERN_TLS
1300 /* t4_kern_tls.c */
1301 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1302 struct m_snd_tag **);
1303 void cxgbe_tls_tag_free(struct m_snd_tag *);
1304 void t6_ktls_modload(void);
1305 void t6_ktls_modunload(void);
1306 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *);
1307 int t6_ktls_parse_pkt(struct mbuf *, int *, int *);
1308 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int);
1309 #endif
1310
1311 /* t4_keyctx.c */
1312 struct auth_hash;
1313 union authctx;
1314
1315 void t4_aes_getdeckey(void *, const void *, unsigned int);
1316 void t4_copy_partial_hash(int, union authctx *, void *);
1317 void t4_init_gmac_hash(const char *, int, char *);
1318 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *);
1319
1320 #ifdef DEV_NETMAP
1321 /* t4_netmap.c */
1322 struct sge_nm_rxq;
1323 void cxgbe_nm_attach(struct vi_info *);
1324 void cxgbe_nm_detach(struct vi_info *);
1325 void service_nm_rxq(struct sge_nm_rxq *);
1326 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int);
1327 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1328 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int);
1329 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1330 #endif
1331
1332 /* t4_sge.c */
1333 void t4_sge_modload(void);
1334 void t4_sge_modunload(void);
1335 uint64_t t4_sge_extfree_refs(void);
1336 void t4_tweak_chip_settings(struct adapter *);
1337 int t4_verify_chip_settings(struct adapter *);
1338 void t4_init_rx_buf_info(struct adapter *);
1339 int t4_create_dma_tag(struct adapter *);
1340 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1341 struct sysctl_oid_list *);
1342 int t4_destroy_dma_tag(struct adapter *);
1343 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1344 bus_addr_t *, void **);
1345 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1346 void *);
1347 void free_fl_buffers(struct adapter *, struct sge_fl *);
1348 int t4_setup_adapter_queues(struct adapter *);
1349 int t4_teardown_adapter_queues(struct adapter *);
1350 int t4_setup_vi_queues(struct vi_info *);
1351 int t4_teardown_vi_queues(struct vi_info *);
1352 void t4_intr_all(void *);
1353 void t4_intr(void *);
1354 #ifdef DEV_NETMAP
1355 void t4_nm_intr(void *);
1356 void t4_vi_intr(void *);
1357 #endif
1358 void t4_intr_err(void *);
1359 void t4_intr_evt(void *);
1360 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1361 void t4_update_fl_bufsize(struct ifnet *);
1362 struct mbuf *alloc_wr_mbuf(int, int);
1363 int parse_pkt(struct mbuf **, bool);
1364 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1365 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1366 int tnl_cong(struct port_info *, int);
1367 void t4_register_an_handler(an_handler_t);
1368 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1369 void t4_register_cpl_handler(int, cpl_handler_t);
1370 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1371 #ifdef RATELIMIT
1372 int ethofld_transmit(struct ifnet *, struct mbuf *);
1373 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1374 #endif
1375
1376 /* t4_tracer.c */
1377 struct t4_tracer;
1378 void t4_tracer_modload(void);
1379 void t4_tracer_modunload(void);
1380 void t4_tracer_port_detach(struct adapter *);
1381 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1382 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1383 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1384 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1385
1386 /* t4_sched.c */
1387 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1388 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1389 int t4_init_tx_sched(struct adapter *);
1390 int t4_free_tx_sched(struct adapter *);
1391 void t4_update_tx_sched(struct adapter *);
1392 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1393 void t4_release_cl_rl(struct adapter *, int, int);
1394 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1395 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1396 #ifdef RATELIMIT
1397 void t4_init_etid_table(struct adapter *);
1398 void t4_free_etid_table(struct adapter *);
1399 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1400 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1401 struct m_snd_tag **);
1402 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1403 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1404 void cxgbe_rate_tag_free(struct m_snd_tag *);
1405 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1406 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *);
1407 #endif
1408
1409 /* t4_filter.c */
1410 int get_filter_mode(struct adapter *, uint32_t *);
1411 int set_filter_mode(struct adapter *, uint32_t);
1412 int set_filter_mask(struct adapter *, uint32_t);
1413 int get_filter(struct adapter *, struct t4_filter *);
1414 int set_filter(struct adapter *, struct t4_filter *);
1415 int del_filter(struct adapter *, struct t4_filter *);
1416 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1417 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1418 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1419 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1420 void free_hftid_hash(struct tid_info *);
1421
1422 static inline struct wrqe *
alloc_wrqe(int wr_len,struct sge_wrq * wrq)1423 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1424 {
1425 int len = offsetof(struct wrqe, wr) + wr_len;
1426 struct wrqe *wr;
1427
1428 wr = malloc(len, M_CXGBE, M_NOWAIT);
1429 if (__predict_false(wr == NULL))
1430 return (NULL);
1431 wr->wr_len = wr_len;
1432 wr->wrq = wrq;
1433 return (wr);
1434 }
1435
1436 static inline void *
wrtod(struct wrqe * wr)1437 wrtod(struct wrqe *wr)
1438 {
1439 return (&wr->wr[0]);
1440 }
1441
1442 static inline void
free_wrqe(struct wrqe * wr)1443 free_wrqe(struct wrqe *wr)
1444 {
1445 free(wr, M_CXGBE);
1446 }
1447
1448 static inline void
t4_wrq_tx(struct adapter * sc,struct wrqe * wr)1449 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1450 {
1451 struct sge_wrq *wrq = wr->wrq;
1452
1453 TXQ_LOCK(wrq);
1454 t4_wrq_tx_locked(sc, wrq, wr);
1455 TXQ_UNLOCK(wrq);
1456 }
1457
1458 static inline int
read_via_memwin(struct adapter * sc,int idx,uint32_t addr,uint32_t * val,int len)1459 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1460 int len)
1461 {
1462
1463 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1464 }
1465
1466 static inline int
write_via_memwin(struct adapter * sc,int idx,uint32_t addr,const uint32_t * val,int len)1467 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1468 const uint32_t *val, int len)
1469 {
1470
1471 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1472 }
1473
1474 /* Number of len16 -> number of descriptors */
1475 static inline int
tx_len16_to_desc(int len16)1476 tx_len16_to_desc(int len16)
1477 {
1478
1479 return (howmany(len16, EQ_ESIZE / 16));
1480 }
1481 #endif
1482