1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2008, 2009 Rui Paulo <[email protected]>
5 * Copyright (c) 2009 Norikatsu Shigemura <[email protected]>
6 * Copyright (c) 2009-2012 Jung-uk Kim <[email protected]>
7 * All rights reserved.
8 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Driver for the AMD CPU on-die thermal sensors.
34 * Initially based on the k8temp Linux driver.
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/conf.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/sysctl.h>
48 #include <sys/systm.h>
49
50 #include <machine/cpufunc.h>
51 #include <machine/md_var.h>
52 #include <machine/specialreg.h>
53
54 #include <dev/pci/pcivar.h>
55 #include <x86/pci_cfgreg.h>
56
57 #include <dev/amdsmn/amdsmn.h>
58
59 typedef enum {
60 CORE0_SENSOR0,
61 CORE0_SENSOR1,
62 CORE1_SENSOR0,
63 CORE1_SENSOR1,
64 CORE0,
65 CORE1,
66 CCD1,
67 CCD_BASE = CCD1,
68 CCD2,
69 CCD3,
70 CCD4,
71 CCD5,
72 CCD6,
73 CCD7,
74 CCD8,
75 CCD_MAX = CCD8,
76 NUM_CCDS = CCD_MAX - CCD_BASE + 1,
77 } amdsensor_t;
78
79 struct amdtemp_softc {
80 int sc_ncores;
81 int sc_ntemps;
82 int sc_flags;
83 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
84 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
85 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
86 int32_t sc_offset;
87 int32_t (*sc_gettemp)(device_t, amdsensor_t);
88 struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
89 struct intr_config_hook sc_ich;
90 device_t sc_smn;
91 struct mtx sc_lock;
92 };
93
94 /*
95 * N.B. The numbers in macro names below are significant and represent CPU
96 * family and model numbers. Do not make up fictitious family or model numbers
97 * when adding support for new devices.
98 */
99 #define VENDORID_AMD 0x1022
100 #define DEVICEID_AMD_MISC0F 0x1103
101 #define DEVICEID_AMD_MISC10 0x1203
102 #define DEVICEID_AMD_MISC11 0x1303
103 #define DEVICEID_AMD_MISC14 0x1703
104 #define DEVICEID_AMD_MISC15 0x1603
105 #define DEVICEID_AMD_MISC15_M10H 0x1403
106 #define DEVICEID_AMD_MISC15_M30H 0x141d
107 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
108 #define DEVICEID_AMD_MISC16 0x1533
109 #define DEVICEID_AMD_MISC16_M30H 0x1583
110 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
111 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
112 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
113 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630
114
115 static const struct amdtemp_product {
116 uint16_t amdtemp_vendorid;
117 uint16_t amdtemp_deviceid;
118 /*
119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
120 * drivers do not attach to that device.
121 */
122 bool amdtemp_has_cpuid;
123 } amdtemp_products[] = {
124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true },
126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true },
127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true },
128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true },
129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true },
133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
137 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
138 };
139
140 /*
141 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
142 */
143 #define AMDTEMP_REPTMP_CTRL 0xa4
144
145 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
146 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
147 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
148 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
149
150 /*
151 * Reported Temperature, Family 15h, M60+
152 *
153 * Same register bit definitions as other Family 15h CPUs, but access is
154 * indirect via SMN, like Family 17h.
155 */
156 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
157
158 /*
159 * Reported Temperature, Family 17h
160 *
161 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
162 * provide the current temp. bit 19, when clear, means the temp is reported in
163 * a range 0.."225C" (probable typo for 255C), and when set changes the range
164 * to -49..206C.
165 */
166 #define AMDTEMP_17H_CUR_TMP 0x59800
167 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19)
168 /*
169 * The following register set was discovered experimentally by Ondrej Čerman
170 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
171 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
172 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
173 */
174 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954
175 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
176
177 /*
178 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
179 */
180 #define AMDTEMP_CURTMP_RANGE_ADJUST 490
181
182 /*
183 * Thermaltrip Status Register (Family 0Fh only)
184 */
185 #define AMDTEMP_THERMTP_STAT 0xe4
186 #define AMDTEMP_TTSR_SELCORE 0x04
187 #define AMDTEMP_TTSR_SELSENSOR 0x40
188
189 /*
190 * DRAM Configuration High Register
191 */
192 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
193 #define AMDTEMP_DRAM_MODE_DDR3 0x0100
194
195 /*
196 * CPU Family/Model Register
197 */
198 #define AMDTEMP_CPUID 0xfc
199
200 /*
201 * Device methods.
202 */
203 static void amdtemp_identify(driver_t *driver, device_t parent);
204 static int amdtemp_probe(device_t dev);
205 static int amdtemp_attach(device_t dev);
206 static void amdtemp_intrhook(void *arg);
207 static int amdtemp_detach(device_t dev);
208 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
209 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
210 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
211 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
212 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
213 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model);
214 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
215
216 static device_method_t amdtemp_methods[] = {
217 /* Device interface */
218 DEVMETHOD(device_identify, amdtemp_identify),
219 DEVMETHOD(device_probe, amdtemp_probe),
220 DEVMETHOD(device_attach, amdtemp_attach),
221 DEVMETHOD(device_detach, amdtemp_detach),
222
223 DEVMETHOD_END
224 };
225
226 static driver_t amdtemp_driver = {
227 "amdtemp",
228 amdtemp_methods,
229 sizeof(struct amdtemp_softc),
230 };
231
232 static devclass_t amdtemp_devclass;
233 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL);
234 MODULE_VERSION(amdtemp, 1);
235 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
236 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
237 nitems(amdtemp_products));
238
239 static bool
amdtemp_match(device_t dev,const struct amdtemp_product ** product_out)240 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
241 {
242 int i;
243 uint16_t vendor, devid;
244
245 vendor = pci_get_vendor(dev);
246 devid = pci_get_device(dev);
247
248 for (i = 0; i < nitems(amdtemp_products); i++) {
249 if (vendor == amdtemp_products[i].amdtemp_vendorid &&
250 devid == amdtemp_products[i].amdtemp_deviceid) {
251 if (product_out != NULL)
252 *product_out = &amdtemp_products[i];
253 return (true);
254 }
255 }
256 return (false);
257 }
258
259 static void
amdtemp_identify(driver_t * driver,device_t parent)260 amdtemp_identify(driver_t *driver, device_t parent)
261 {
262 device_t child;
263
264 /* Make sure we're not being doubly invoked. */
265 if (device_find_child(parent, "amdtemp", -1) != NULL)
266 return;
267
268 if (amdtemp_match(parent, NULL)) {
269 child = device_add_child(parent, "amdtemp", -1);
270 if (child == NULL)
271 device_printf(parent, "add amdtemp child failed\n");
272 }
273 }
274
275 static int
amdtemp_probe(device_t dev)276 amdtemp_probe(device_t dev)
277 {
278 uint32_t family, model;
279
280 if (resource_disabled("amdtemp", 0))
281 return (ENXIO);
282 if (!amdtemp_match(device_get_parent(dev), NULL))
283 return (ENXIO);
284
285 family = CPUID_TO_FAMILY(cpu_id);
286 model = CPUID_TO_MODEL(cpu_id);
287
288 switch (family) {
289 case 0x0f:
290 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
291 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
292 return (ENXIO);
293 break;
294 case 0x10:
295 case 0x11:
296 case 0x12:
297 case 0x14:
298 case 0x15:
299 case 0x16:
300 case 0x17:
301 case 0x19:
302 break;
303 default:
304 return (ENXIO);
305 }
306 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
307
308 return (BUS_PROBE_GENERIC);
309 }
310
311 static int
amdtemp_attach(device_t dev)312 amdtemp_attach(device_t dev)
313 {
314 char tn[32];
315 u_int regs[4];
316 const struct amdtemp_product *product;
317 struct amdtemp_softc *sc;
318 struct sysctl_ctx_list *sysctlctx;
319 struct sysctl_oid *sysctlnode;
320 uint32_t cpuid, family, model;
321 u_int bid;
322 int erratum319, unit;
323 bool needsmn;
324
325 sc = device_get_softc(dev);
326 erratum319 = 0;
327 needsmn = false;
328
329 if (!amdtemp_match(device_get_parent(dev), &product))
330 return (ENXIO);
331
332 cpuid = cpu_id;
333 family = CPUID_TO_FAMILY(cpuid);
334 model = CPUID_TO_MODEL(cpuid);
335
336 /*
337 * This checks for the byzantine condition of running a heterogenous
338 * revision multi-socket system where the attach thread is potentially
339 * probing a remote socket's PCI device.
340 *
341 * Currently, such scenarios are unsupported on models using the SMN
342 * (because on those models, amdtemp(4) attaches to a different PCI
343 * device than the one that contains AMDTEMP_CPUID).
344 *
345 * The ancient 0x0F family of devices only supports this register from
346 * models 40h+.
347 */
348 if (product->amdtemp_has_cpuid && (family > 0x0f ||
349 (family == 0x0f && model >= 0x40))) {
350 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
351 4);
352 family = CPUID_TO_FAMILY(cpuid);
353 model = CPUID_TO_MODEL(cpuid);
354 }
355
356 switch (family) {
357 case 0x0f:
358 /*
359 * Thermaltrip Status Register
360 *
361 * - ThermSenseCoreSel
362 *
363 * Revision F & G: 0 - Core1, 1 - Core0
364 * Other: 0 - Core0, 1 - Core1
365 *
366 * - CurTmp
367 *
368 * Revision G: bits 23-14
369 * Other: bits 23-16
370 *
371 * XXX According to the BKDG, CurTmp, ThermSenseSel and
372 * ThermSenseCoreSel bits were introduced in Revision F
373 * but CurTmp seems working fine as early as Revision C.
374 * However, it is not clear whether ThermSenseSel and/or
375 * ThermSenseCoreSel work in undocumented cases as well.
376 * In fact, the Linux driver suggests it may not work but
377 * we just assume it does until we find otherwise.
378 *
379 * XXX According to Linux, CurTmp starts at -28C on
380 * Socket AM2 Revision G processors, which is not
381 * documented anywhere.
382 */
383 if (model >= 0x40)
384 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
385 if (model >= 0x60 && model != 0xc1) {
386 do_cpuid(0x80000001, regs);
387 bid = (regs[1] >> 9) & 0x1f;
388 switch (model) {
389 case 0x68: /* Socket S1g1 */
390 case 0x6c:
391 case 0x7c:
392 break;
393 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
394 if (bid != 0x0b && bid != 0x0c)
395 sc->sc_flags |=
396 AMDTEMP_FLAG_ALT_OFFSET;
397 break;
398 case 0x6f: /* Socket AM2 and ASB1 (1 core) */
399 case 0x7f:
400 if (bid != 0x07 && bid != 0x09 &&
401 bid != 0x0c)
402 sc->sc_flags |=
403 AMDTEMP_FLAG_ALT_OFFSET;
404 break;
405 default:
406 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
407 }
408 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
409 }
410
411 /*
412 * There are two sensors per core.
413 */
414 sc->sc_ntemps = 2;
415
416 sc->sc_gettemp = amdtemp_gettemp0f;
417 break;
418 case 0x10:
419 /*
420 * Erratum 319 Inaccurate Temperature Measurement
421 *
422 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
423 */
424 do_cpuid(0x80000001, regs);
425 switch ((regs[1] >> 28) & 0xf) {
426 case 0: /* Socket F */
427 erratum319 = 1;
428 break;
429 case 1: /* Socket AM2+ or AM3 */
430 if ((pci_cfgregread(pci_get_bus(dev),
431 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
432 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
433 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
434 break;
435 /* XXX 00100F42h (RB-C2) exists in both formats. */
436 erratum319 = 1;
437 break;
438 }
439 /* FALLTHROUGH */
440 case 0x11:
441 case 0x12:
442 case 0x14:
443 case 0x15:
444 case 0x16:
445 sc->sc_ntemps = 1;
446 /*
447 * Some later (60h+) models of family 15h use a similar SMN
448 * network as family 17h. (However, the register index differs
449 * from 17h and the decoding matches other 10h-15h models,
450 * which differ from 17h.)
451 */
452 if (family == 0x15 && model >= 0x60) {
453 sc->sc_gettemp = amdtemp_gettemp15hm60h;
454 needsmn = true;
455 } else
456 sc->sc_gettemp = amdtemp_gettemp;
457 break;
458 case 0x17:
459 case 0x19:
460 sc->sc_ntemps = 1;
461 sc->sc_gettemp = amdtemp_gettemp17h;
462 needsmn = true;
463 break;
464 default:
465 device_printf(dev, "Bogus family 0x%x\n", family);
466 return (ENXIO);
467 }
468
469 if (needsmn) {
470 sc->sc_smn = device_find_child(
471 device_get_parent(dev), "amdsmn", -1);
472 if (sc->sc_smn == NULL) {
473 if (bootverbose)
474 device_printf(dev, "No SMN device found\n");
475 return (ENXIO);
476 }
477 }
478
479 /* Find number of cores per package. */
480 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
481 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
482 if (sc->sc_ncores > MAXCPU)
483 return (ENXIO);
484
485 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF);
486 if (erratum319)
487 device_printf(dev,
488 "Erratum 319: temperature measurement may be inaccurate\n");
489 if (bootverbose)
490 device_printf(dev, "Found %d cores and %d sensors.\n",
491 sc->sc_ncores,
492 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
493
494 /*
495 * dev.amdtemp.N tree.
496 */
497 unit = device_get_unit(dev);
498 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
499 TUNABLE_INT_FETCH(tn, &sc->sc_offset);
500
501 sysctlctx = device_get_sysctl_ctx(dev);
502 SYSCTL_ADD_INT(sysctlctx,
503 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
504 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
505 "Temperature sensor offset");
506 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
507 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
508 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");
509
510 SYSCTL_ADD_PROC(sysctlctx,
511 SYSCTL_CHILDREN(sysctlnode),
512 OID_AUTO, "sensor0",
513 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
514 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
515 "Core 0 / Sensor 0 temperature");
516
517 if (family == 0x17)
518 amdtemp_probe_ccd_sensors17h(dev, model);
519 else if (family == 0x19)
520 amdtemp_probe_ccd_sensors19h(dev, model);
521 else if (sc->sc_ntemps > 1) {
522 SYSCTL_ADD_PROC(sysctlctx,
523 SYSCTL_CHILDREN(sysctlnode),
524 OID_AUTO, "sensor1",
525 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
526 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
527 "Core 0 / Sensor 1 temperature");
528
529 if (sc->sc_ncores > 1) {
530 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
531 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
532 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE,
533 0, "Core 1");
534
535 SYSCTL_ADD_PROC(sysctlctx,
536 SYSCTL_CHILDREN(sysctlnode),
537 OID_AUTO, "sensor0",
538 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
539 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
540 "Core 1 / Sensor 0 temperature");
541
542 SYSCTL_ADD_PROC(sysctlctx,
543 SYSCTL_CHILDREN(sysctlnode),
544 OID_AUTO, "sensor1",
545 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
546 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
547 "Core 1 / Sensor 1 temperature");
548 }
549 }
550
551 /*
552 * Try to create dev.cpu sysctl entries and setup intrhook function.
553 * This is needed because the cpu driver may be loaded late on boot,
554 * after us.
555 */
556 amdtemp_intrhook(dev);
557 sc->sc_ich.ich_func = amdtemp_intrhook;
558 sc->sc_ich.ich_arg = dev;
559 if (config_intrhook_establish(&sc->sc_ich) != 0) {
560 device_printf(dev, "config_intrhook_establish failed!\n");
561 return (ENXIO);
562 }
563
564 return (0);
565 }
566
567 void
amdtemp_intrhook(void * arg)568 amdtemp_intrhook(void *arg)
569 {
570 struct amdtemp_softc *sc;
571 struct sysctl_ctx_list *sysctlctx;
572 device_t dev = (device_t)arg;
573 device_t acpi, cpu, nexus;
574 amdsensor_t sensor;
575 int i;
576
577 sc = device_get_softc(dev);
578
579 /*
580 * dev.cpu.N.temperature.
581 */
582 nexus = device_find_child(root_bus, "nexus", 0);
583 acpi = device_find_child(nexus, "acpi", 0);
584
585 for (i = 0; i < sc->sc_ncores; i++) {
586 if (sc->sc_sysctl_cpu[i] != NULL)
587 continue;
588 cpu = device_find_child(acpi, "cpu",
589 device_get_unit(dev) * sc->sc_ncores + i);
590 if (cpu != NULL) {
591 sysctlctx = device_get_sysctl_ctx(cpu);
592
593 sensor = sc->sc_ntemps > 1 ?
594 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
595 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
596 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
597 OID_AUTO, "temperature",
598 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
599 dev, sensor, amdtemp_sysctl, "IK",
600 "Current temparature");
601 }
602 }
603 if (sc->sc_ich.ich_arg != NULL)
604 config_intrhook_disestablish(&sc->sc_ich);
605 }
606
607 int
amdtemp_detach(device_t dev)608 amdtemp_detach(device_t dev)
609 {
610 struct amdtemp_softc *sc = device_get_softc(dev);
611 int i;
612
613 for (i = 0; i < sc->sc_ncores; i++)
614 if (sc->sc_sysctl_cpu[i] != NULL)
615 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
616
617 /* NewBus removes the dev.amdtemp.N tree by itself. */
618
619 mtx_destroy(&sc->sc_lock);
620 return (0);
621 }
622
623 static int
amdtemp_sysctl(SYSCTL_HANDLER_ARGS)624 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
625 {
626 device_t dev = (device_t)arg1;
627 struct amdtemp_softc *sc = device_get_softc(dev);
628 amdsensor_t sensor = (amdsensor_t)arg2;
629 int32_t auxtemp[2], temp;
630 int error;
631
632 switch (sensor) {
633 case CORE0:
634 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
635 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
636 temp = imax(auxtemp[0], auxtemp[1]);
637 break;
638 case CORE1:
639 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
640 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
641 temp = imax(auxtemp[0], auxtemp[1]);
642 break;
643 default:
644 temp = sc->sc_gettemp(dev, sensor);
645 break;
646 }
647 error = sysctl_handle_int(oidp, &temp, 0, req);
648
649 return (error);
650 }
651
652 #define AMDTEMP_ZERO_C_TO_K 2731
653
654 static int32_t
amdtemp_gettemp0f(device_t dev,amdsensor_t sensor)655 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
656 {
657 struct amdtemp_softc *sc = device_get_softc(dev);
658 uint32_t mask, offset, temp;
659
660 mtx_lock(&sc->sc_lock);
661
662 /* Set Sensor/Core selector. */
663 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
664 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
665 switch (sensor) {
666 case CORE0_SENSOR1:
667 temp |= AMDTEMP_TTSR_SELSENSOR;
668 /* FALLTHROUGH */
669 case CORE0_SENSOR0:
670 case CORE0:
671 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
672 temp |= AMDTEMP_TTSR_SELCORE;
673 break;
674 case CORE1_SENSOR1:
675 temp |= AMDTEMP_TTSR_SELSENSOR;
676 /* FALLTHROUGH */
677 case CORE1_SENSOR0:
678 case CORE1:
679 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
680 temp |= AMDTEMP_TTSR_SELCORE;
681 break;
682 default:
683 __assert_unreachable();
684 }
685 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
686
687 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
688 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
689 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
690 temp = ((temp >> 14) & mask) * 5 / 2;
691 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
692
693 mtx_unlock(&sc->sc_lock);
694 return (temp);
695 }
696
697 static uint32_t
amdtemp_decode_fam10h_to_17h(int32_t sc_offset,uint32_t val,bool minus49)698 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
699 {
700 uint32_t temp;
701
702 /* Convert raw register subfield units (0.125C) to units of 0.1C. */
703 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
704
705 if (minus49)
706 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
707
708 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
709 return (temp);
710 }
711
712 static uint32_t
amdtemp_decode_fam10h_to_16h(int32_t sc_offset,uint32_t val)713 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
714 {
715 bool minus49;
716
717 /*
718 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
719 * adjusted down by 49.0 degrees Celsius. (This adjustment is not
720 * documented in BKDGs prior to family 15h model 00h.)
721 */
722 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
723 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
724 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
725
726 return (amdtemp_decode_fam10h_to_17h(sc_offset,
727 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
728 }
729
730 static uint32_t
amdtemp_decode_fam17h_tctl(int32_t sc_offset,uint32_t val)731 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
732 {
733 bool minus49;
734
735 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0);
736 return (amdtemp_decode_fam10h_to_17h(sc_offset,
737 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
738 }
739
740 static int32_t
amdtemp_gettemp(device_t dev,amdsensor_t sensor)741 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
742 {
743 struct amdtemp_softc *sc = device_get_softc(dev);
744 uint32_t temp;
745
746 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
747 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
748 }
749
750 static int32_t
amdtemp_gettemp15hm60h(device_t dev,amdsensor_t sensor)751 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
752 {
753 struct amdtemp_softc *sc = device_get_softc(dev);
754 uint32_t val;
755 int error;
756
757 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
758 KASSERT(error == 0, ("amdsmn_read"));
759 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
760 }
761
762 static int32_t
amdtemp_gettemp17h(device_t dev,amdsensor_t sensor)763 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
764 {
765 struct amdtemp_softc *sc = device_get_softc(dev);
766 uint32_t val;
767 int error;
768
769 switch (sensor) {
770 case CORE0_SENSOR0:
771 /* Tctl */
772 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
773 KASSERT(error == 0, ("amdsmn_read"));
774 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
775 case CCD_BASE ... CCD_MAX:
776 /* Tccd<N> */
777 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
778 (((int)sensor - CCD_BASE) * sizeof(val)), &val);
779 KASSERT(error == 0, ("amdsmn_read2"));
780 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
781 ("sensor %d: not valid", (int)sensor));
782 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
783 default:
784 __assert_unreachable();
785 }
786 }
787
788 static void
amdtemp_probe_ccd_sensors(device_t dev,uint32_t maxreg)789 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg)
790 {
791 char sensor_name[16], sensor_descr[32];
792 struct amdtemp_softc *sc;
793 uint32_t i, val;
794 int error;
795
796 sc = device_get_softc(dev);
797 for (i = 0; i < maxreg; i++) {
798 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
799 (i * sizeof(val)), &val);
800 if (error != 0)
801 continue;
802 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
803 continue;
804
805 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
806 snprintf(sensor_descr, sizeof(sensor_descr),
807 "CCD %u temperature (Tccd%u)", i, i);
808
809 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
810 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
811 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
812 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);
813 }
814 }
815
816 static void
amdtemp_probe_ccd_sensors17h(device_t dev,uint32_t model)817 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
818 {
819 uint32_t maxreg;
820
821 switch (model) {
822 case 0x00 ... 0x2f: /* Zen1, Zen+ */
823 maxreg = 4;
824 break;
825 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
826 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
827 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
828 maxreg = 8;
829 _Static_assert((int)NUM_CCDS >= 8, "");
830 break;
831 default:
832 device_printf(dev,
833 "Unrecognized Family 17h Model: %02xh\n", model);
834 return;
835 }
836
837 amdtemp_probe_ccd_sensors(dev, maxreg);
838 }
839
840 static void
amdtemp_probe_ccd_sensors19h(device_t dev,uint32_t model)841 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model)
842 {
843 uint32_t maxreg;
844
845 switch (model) {
846 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
847 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
848 maxreg = 8;
849 _Static_assert((int)NUM_CCDS >= 8, "");
850 break;
851 default:
852 device_printf(dev,
853 "Unrecognized Family 19h Model: %02xh\n", model);
854 return;
855 }
856
857 amdtemp_probe_ccd_sensors(dev, maxreg);
858 }
859