1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8
9 #include <cassert>
10 #include <cstddef>
11 #include <vector>
12
13 #include "lldb/lldb-defines.h"
14 #include "llvm/Support/Compiler.h"
15
16 #include "RegisterInfoPOSIX_arm64.h"
17
18 // Based on RegisterContextDarwin_arm64.cpp
19 #define GPR_OFFSET(idx) ((idx)*8)
20 #define GPR_OFFSET_NAME(reg) \
21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
22
23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
24 #define FPU_OFFSET_NAME(reg) \
25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
26 sizeof(RegisterInfoPOSIX_arm64::GPR))
27
28 // This information is based on AArch64 with SVE architecture reference manual.
29 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
30 // (First Fault) register and a VG (Vector Granule) pseudo register.
31
32 // SVE 16-byte quad word is the basic unit of expansion in vector length.
33 #define SVE_QUAD_WORD_BYTES 16
34
35 // Vector length is the multiplier which decides the no of quad words,
36 // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
37 // is decided during execution and can change at runtime. SVE AArch64 register
38 // infos have modes one for each valid value of vector length. A change in
39 // vector length requires register context to update sizes of SVE Z, P and FFR.
40 // Also register context needs to update byte offsets of all registers affected
41 // by the change in vector length.
42 #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
43
44 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
45
46 #define EXC_OFFSET_NAME(reg) \
47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
49 sizeof(RegisterInfoPOSIX_arm64::FPU))
50 #define DBG_OFFSET_NAME(reg) \
51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
54 sizeof(RegisterInfoPOSIX_arm64::EXC))
55
56 #define DEFINE_DBG(reg, i) \
57 #reg, NULL, \
58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
62 dbg_##reg##i }, \
63 NULL, NULL, NULL, 0
64 #define REG_CONTEXT_SIZE \
65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
67 sizeof(RegisterInfoPOSIX_arm64::EXC))
68
69 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
70 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
71 #include "RegisterInfos_arm64.h"
72 #include "RegisterInfos_arm64_sve.h"
73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
74
75 // Number of register sets provided by this context.
76 enum {
77 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
78 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
79 k_num_sve_registers = sve_ffr - sve_vg + 1,
80 k_num_mte_register = 1,
81 k_num_pauth_register = 2,
82 k_num_register_sets_default = 2,
83 k_num_register_sets = 3
84 };
85
86 // ARM64 general purpose registers.
87 static const uint32_t g_gpr_regnums_arm64[] = {
88 gpr_x0, gpr_x1, gpr_x2, gpr_x3,
89 gpr_x4, gpr_x5, gpr_x6, gpr_x7,
90 gpr_x8, gpr_x9, gpr_x10, gpr_x11,
91 gpr_x12, gpr_x13, gpr_x14, gpr_x15,
92 gpr_x16, gpr_x17, gpr_x18, gpr_x19,
93 gpr_x20, gpr_x21, gpr_x22, gpr_x23,
94 gpr_x24, gpr_x25, gpr_x26, gpr_x27,
95 gpr_x28, gpr_fp, gpr_lr, gpr_sp,
96 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
97 gpr_w2, gpr_w3, gpr_w4, gpr_w5,
98 gpr_w6, gpr_w7, gpr_w8, gpr_w9,
99 gpr_w10, gpr_w11, gpr_w12, gpr_w13,
100 gpr_w14, gpr_w15, gpr_w16, gpr_w17,
101 gpr_w18, gpr_w19, gpr_w20, gpr_w21,
102 gpr_w22, gpr_w23, gpr_w24, gpr_w25,
103 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
104
105 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
106 1) == k_num_gpr_registers,
107 "g_gpr_regnums_arm64 has wrong number of register infos");
108
109 // ARM64 floating point registers.
110 static const uint32_t g_fpu_regnums_arm64[] = {
111 fpu_v0, fpu_v1, fpu_v2,
112 fpu_v3, fpu_v4, fpu_v5,
113 fpu_v6, fpu_v7, fpu_v8,
114 fpu_v9, fpu_v10, fpu_v11,
115 fpu_v12, fpu_v13, fpu_v14,
116 fpu_v15, fpu_v16, fpu_v17,
117 fpu_v18, fpu_v19, fpu_v20,
118 fpu_v21, fpu_v22, fpu_v23,
119 fpu_v24, fpu_v25, fpu_v26,
120 fpu_v27, fpu_v28, fpu_v29,
121 fpu_v30, fpu_v31, fpu_s0,
122 fpu_s1, fpu_s2, fpu_s3,
123 fpu_s4, fpu_s5, fpu_s6,
124 fpu_s7, fpu_s8, fpu_s9,
125 fpu_s10, fpu_s11, fpu_s12,
126 fpu_s13, fpu_s14, fpu_s15,
127 fpu_s16, fpu_s17, fpu_s18,
128 fpu_s19, fpu_s20, fpu_s21,
129 fpu_s22, fpu_s23, fpu_s24,
130 fpu_s25, fpu_s26, fpu_s27,
131 fpu_s28, fpu_s29, fpu_s30,
132 fpu_s31, fpu_d0, fpu_d1,
133 fpu_d2, fpu_d3, fpu_d4,
134 fpu_d5, fpu_d6, fpu_d7,
135 fpu_d8, fpu_d9, fpu_d10,
136 fpu_d11, fpu_d12, fpu_d13,
137 fpu_d14, fpu_d15, fpu_d16,
138 fpu_d17, fpu_d18, fpu_d19,
139 fpu_d20, fpu_d21, fpu_d22,
140 fpu_d23, fpu_d24, fpu_d25,
141 fpu_d26, fpu_d27, fpu_d28,
142 fpu_d29, fpu_d30, fpu_d31,
143 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
144 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
145 1) == k_num_fpr_registers,
146 "g_fpu_regnums_arm64 has wrong number of register infos");
147
148 // ARM64 SVE registers.
149 static const uint32_t g_sve_regnums_arm64[] = {
150 sve_vg, sve_z0, sve_z1,
151 sve_z2, sve_z3, sve_z4,
152 sve_z5, sve_z6, sve_z7,
153 sve_z8, sve_z9, sve_z10,
154 sve_z11, sve_z12, sve_z13,
155 sve_z14, sve_z15, sve_z16,
156 sve_z17, sve_z18, sve_z19,
157 sve_z20, sve_z21, sve_z22,
158 sve_z23, sve_z24, sve_z25,
159 sve_z26, sve_z27, sve_z28,
160 sve_z29, sve_z30, sve_z31,
161 sve_p0, sve_p1, sve_p2,
162 sve_p3, sve_p4, sve_p5,
163 sve_p6, sve_p7, sve_p8,
164 sve_p9, sve_p10, sve_p11,
165 sve_p12, sve_p13, sve_p14,
166 sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
167 static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
168 1) == k_num_sve_registers,
169 "g_sve_regnums_arm64 has wrong number of register infos");
170
171 // Register sets for ARM64.
172 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
173 {"General Purpose Registers", "gpr", k_num_gpr_registers,
174 g_gpr_regnums_arm64},
175 {"Floating Point Registers", "fpu", k_num_fpr_registers,
176 g_fpu_regnums_arm64},
177 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
178 g_sve_regnums_arm64}};
179
180 static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
181 "Pointer Authentication Registers", "pauth", k_num_pauth_register, NULL};
182
183 static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
184 "MTE Control Register", "mte", k_num_mte_register, NULL};
185
RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec & target_arch,lldb_private::Flags opt_regsets)186 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
187 const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
188 : lldb_private::RegisterInfoAndSetInterface(target_arch),
189 m_opt_regsets(opt_regsets) {
190 switch (target_arch.GetMachine()) {
191 case llvm::Triple::aarch64:
192 case llvm::Triple::aarch64_32: {
193 m_register_set_p = g_reg_sets_arm64;
194 m_register_set_count = k_num_register_sets_default;
195 m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
196 m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
197
198 // Now configure register sets supported by current target. If we have a
199 // dynamic register set like MTE, Pointer Authentication regset then we need
200 // to create dynamic register infos and regset array. Push back all optional
201 // register infos and regset and calculate register offsets accordingly.
202 if (m_opt_regsets.AllSet(eRegsetMaskSVE)) {
203 m_register_info_p = g_register_infos_arm64_sve_le;
204 m_register_info_count = sve_ffr + 1;
205 m_per_regset_regnum_range[m_register_set_count++] =
206 std::make_pair(sve_vg, sve_ffr + 1);
207 } else {
208 m_register_info_p = g_register_infos_arm64_le;
209 m_register_info_count = fpu_fpcr + 1;
210 }
211
212 if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) {
213 llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
214 llvm::makeArrayRef(m_register_info_p, m_register_info_count);
215 llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
216 llvm::makeArrayRef(m_register_set_p, m_register_set_count);
217 llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
218 llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
219
220 if (m_opt_regsets.AllSet(eRegsetMaskPAuth))
221 AddRegSetPAuth();
222
223 if (m_opt_regsets.AllSet(eRegsetMaskMTE))
224 AddRegSetMTE();
225
226 m_register_info_count = m_dynamic_reg_infos.size();
227 m_register_info_p = m_dynamic_reg_infos.data();
228 m_register_set_p = m_dynamic_reg_sets.data();
229 m_register_set_count = m_dynamic_reg_sets.size();
230 }
231 break;
232 }
233 default:
234 assert(false && "Unhandled target architecture.");
235 }
236 }
237
GetRegisterCount() const238 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const {
239 return m_register_info_count;
240 }
241
GetGPRSize() const242 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const {
243 return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
244 }
245
GetFPRSize() const246 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const {
247 return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
248 }
249
250 const lldb_private::RegisterInfo *
GetRegisterInfo() const251 RegisterInfoPOSIX_arm64::GetRegisterInfo() const {
252 return m_register_info_p;
253 }
254
GetRegisterSetCount() const255 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const {
256 return m_register_set_count;
257 }
258
GetRegisterSetFromRegisterIndex(uint32_t reg_index) const259 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex(
260 uint32_t reg_index) const {
261 for (const auto ®set_range : m_per_regset_regnum_range) {
262 if (reg_index >= regset_range.second.first &&
263 reg_index < regset_range.second.second)
264 return regset_range.first;
265 }
266 return LLDB_INVALID_REGNUM;
267 }
268
269 const lldb_private::RegisterSet *
GetRegisterSet(size_t set_index) const270 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const {
271 if (set_index < GetRegisterSetCount())
272 return &m_register_set_p[set_index];
273 return nullptr;
274 }
275
AddRegSetPAuth()276 void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
277 uint32_t pa_regnum = m_dynamic_reg_infos.size();
278 for (uint32_t i = 0; i < k_num_pauth_register; i++) {
279 pauth_regnum_collection.push_back(pa_regnum + i);
280 m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]);
281 m_dynamic_reg_infos[pa_regnum + i].byte_offset =
282 m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
283 m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
284 m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
285 pa_regnum + i;
286 }
287
288 m_per_regset_regnum_range[m_register_set_count] =
289 std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
290 m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64);
291 m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
292 }
293
AddRegSetMTE()294 void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
295 uint32_t mte_regnum = m_dynamic_reg_infos.size();
296 m_mte_regnum_collection.push_back(mte_regnum);
297 m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
298 m_dynamic_reg_infos[mte_regnum].byte_offset =
299 m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
300 m_dynamic_reg_infos[mte_regnum - 1].byte_size;
301 m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
302
303 m_per_regset_regnum_range[m_register_set_count] =
304 std::make_pair(mte_regnum, mte_regnum + 1);
305 m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64);
306 m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
307 }
308
ConfigureVectorLength(uint32_t sve_vq)309 uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLength(uint32_t sve_vq) {
310 // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
311 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
312 // Also if an invalid or previously set vector length is passed to this
313 // function then it will exit immediately with previously set vector length.
314 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
315 return m_vector_reg_vq;
316
317 // We cannot enable AArch64 only mode if SVE was enabled.
318 if (sve_vq == eVectorQuadwordAArch64 &&
319 m_vector_reg_vq > eVectorQuadwordAArch64)
320 sve_vq = eVectorQuadwordAArch64SVE;
321
322 m_vector_reg_vq = sve_vq;
323
324 if (sve_vq == eVectorQuadwordAArch64)
325 return m_vector_reg_vq;
326 std::vector<lldb_private::RegisterInfo> ®_info_ref =
327 m_per_vq_reg_infos[sve_vq];
328
329 if (reg_info_ref.empty()) {
330 reg_info_ref = llvm::makeArrayRef(m_register_info_p, m_register_info_count);
331
332 uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
333 reg_info_ref[fpu_fpsr].byte_offset = offset;
334 reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
335 reg_info_ref[sve_vg].byte_offset = offset + 8;
336 offset += 16;
337
338 // Update Z registers size and offset
339 uint32_t s_reg_base = fpu_s0;
340 uint32_t d_reg_base = fpu_d0;
341 uint32_t v_reg_base = fpu_v0;
342 uint32_t z_reg_base = sve_z0;
343
344 for (uint32_t index = 0; index < 32; index++) {
345 reg_info_ref[s_reg_base + index].byte_offset = offset;
346 reg_info_ref[d_reg_base + index].byte_offset = offset;
347 reg_info_ref[v_reg_base + index].byte_offset = offset;
348 reg_info_ref[z_reg_base + index].byte_offset = offset;
349
350 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
351 offset += reg_info_ref[z_reg_base + index].byte_size;
352 }
353
354 // Update P registers and FFR size and offset
355 for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
356 reg_info_ref[it].byte_offset = offset;
357 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
358 offset += reg_info_ref[it].byte_size;
359 }
360
361 for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
362 reg_info_ref[it].byte_offset = offset;
363 offset += reg_info_ref[it].byte_size;
364 }
365
366 m_per_vq_reg_infos[sve_vq] = reg_info_ref;
367 }
368
369 m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
370 return m_vector_reg_vq;
371 }
372
IsSVEReg(unsigned reg) const373 bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
374 if (m_vector_reg_vq > eVectorQuadwordAArch64)
375 return (sve_vg <= reg && reg <= sve_ffr);
376 else
377 return false;
378 }
379
IsSVEZReg(unsigned reg) const380 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
381 return (sve_z0 <= reg && reg <= sve_z31);
382 }
383
IsSVEPReg(unsigned reg) const384 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
385 return (sve_p0 <= reg && reg <= sve_p15);
386 }
387
IsSVERegVG(unsigned reg) const388 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
389 return sve_vg == reg;
390 }
391
IsPAuthReg(unsigned reg) const392 bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
393 return std::find(pauth_regnum_collection.begin(),
394 pauth_regnum_collection.end(),
395 reg) != pauth_regnum_collection.end();
396 }
397
IsMTEReg(unsigned reg) const398 bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
399 return std::find(m_mte_regnum_collection.begin(),
400 m_mte_regnum_collection.end(),
401 reg) != m_mte_regnum_collection.end();
402 }
403
GetRegNumSVEZ0() const404 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
405
GetRegNumSVEFFR() const406 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
407
GetRegNumFPCR() const408 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
409
GetRegNumFPSR() const410 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
411
GetRegNumSVEVG() const412 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
413
GetPAuthOffset() const414 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
415 return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
416 }
417
GetMTEOffset() const418 uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
419 return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
420 }
421