1 //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements SystemZ TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZ.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/LangOptions.h"
16 #include "clang/Basic/MacroBuilder.h"
17 #include "clang/Basic/TargetBuiltins.h"
18 #include "llvm/ADT/StringSwitch.h"
19
20 using namespace clang;
21 using namespace clang::targets;
22
23 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
24 #define BUILTIN(ID, TYPE, ATTRS) \
25 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
26 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
28 #include "clang/Basic/BuiltinsSystemZ.def"
29 };
30
31 const char *const SystemZTargetInfo::GCCRegNames[] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
35 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
36 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
37 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
38 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
39 };
40
41 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
42 {{"v0"}, 16}, {{"v2"}, 17}, {{"v4"}, 18}, {{"v6"}, 19},
43 {{"v1"}, 20}, {{"v3"}, 21}, {{"v5"}, 22}, {{"v7"}, 23},
44 {{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27},
45 {{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31}
46 };
47
getGCCRegNames() const48 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
49 return llvm::makeArrayRef(GCCRegNames);
50 }
51
getGCCAddlRegNames() const52 ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
53 return llvm::makeArrayRef(GCCAddlRegNames);
54 }
55
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const56 bool SystemZTargetInfo::validateAsmConstraint(
57 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
58 switch (*Name) {
59 default:
60 return false;
61
62 case 'a': // Address register
63 case 'd': // Data register (equivalent to 'r')
64 case 'f': // Floating-point register
65 case 'v': // Vector register
66 Info.setAllowsRegister();
67 return true;
68
69 case 'I': // Unsigned 8-bit constant
70 case 'J': // Unsigned 12-bit constant
71 case 'K': // Signed 16-bit constant
72 case 'L': // Signed 20-bit displacement (on all targets we support)
73 case 'M': // 0x7fffffff
74 return true;
75
76 case 'Q': // Memory with base and unsigned 12-bit displacement
77 case 'R': // Likewise, plus an index
78 case 'S': // Memory with base and signed 20-bit displacement
79 case 'T': // Likewise, plus an index
80 Info.setAllowsMemory();
81 return true;
82 }
83 }
84
85 struct ISANameRevision {
86 llvm::StringLiteral Name;
87 int ISARevisionID;
88 };
89 static constexpr ISANameRevision ISARevisions[] = {
90 {{"arch8"}, 8}, {{"z10"}, 8},
91 {{"arch9"}, 9}, {{"z196"}, 9},
92 {{"arch10"}, 10}, {{"zEC12"}, 10},
93 {{"arch11"}, 11}, {{"z13"}, 11},
94 {{"arch12"}, 12}, {{"z14"}, 12},
95 {{"arch13"}, 13}, {{"z15"}, 13},
96 {{"arch14"}, 14}
97 };
98
getISARevision(StringRef Name) const99 int SystemZTargetInfo::getISARevision(StringRef Name) const {
100 const auto Rev =
101 llvm::find_if(ISARevisions, [Name](const ISANameRevision &CR) {
102 return CR.Name == Name;
103 });
104 if (Rev == std::end(ISARevisions))
105 return -1;
106 return Rev->ISARevisionID;
107 }
108
fillValidCPUList(SmallVectorImpl<StringRef> & Values) const109 void SystemZTargetInfo::fillValidCPUList(
110 SmallVectorImpl<StringRef> &Values) const {
111 for (const ISANameRevision &Rev : ISARevisions)
112 Values.push_back(Rev.Name);
113 }
114
hasFeature(StringRef Feature) const115 bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
116 return llvm::StringSwitch<bool>(Feature)
117 .Case("systemz", true)
118 .Case("arch8", ISARevision >= 8)
119 .Case("arch9", ISARevision >= 9)
120 .Case("arch10", ISARevision >= 10)
121 .Case("arch11", ISARevision >= 11)
122 .Case("arch12", ISARevision >= 12)
123 .Case("arch13", ISARevision >= 13)
124 .Case("arch14", ISARevision >= 14)
125 .Case("htm", HasTransactionalExecution)
126 .Case("vx", HasVector)
127 .Default(false);
128 }
129
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const130 void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
131 MacroBuilder &Builder) const {
132 Builder.defineMacro("__s390__");
133 Builder.defineMacro("__s390x__");
134 Builder.defineMacro("__zarch__");
135 Builder.defineMacro("__LONG_DOUBLE_128__");
136
137 Builder.defineMacro("__ARCH__", Twine(ISARevision));
138
139 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
140 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
141 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
142 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
143
144 if (HasTransactionalExecution)
145 Builder.defineMacro("__HTM__");
146 if (HasVector)
147 Builder.defineMacro("__VX__");
148 if (Opts.ZVector)
149 Builder.defineMacro("__VEC__", "10304");
150 }
151
getTargetBuiltins() const152 ArrayRef<Builtin::Info> SystemZTargetInfo::getTargetBuiltins() const {
153 return llvm::makeArrayRef(BuiltinInfo, clang::SystemZ::LastTSBuiltin -
154 Builtin::FirstTSBuiltin);
155 }
156