1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2006 Michael Lorenz
5 * Copyright 2008 by Nathan Whitehorn
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/module.h>
39 #include <sys/bus.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/clock.h>
43 #include <sys/reboot.h>
44
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/openfirm.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <sys/rman.h>
58
59 #include <dev/adb/adb.h>
60
61 #include "clock_if.h"
62 #include "cudavar.h"
63 #include "viareg.h"
64
65 /*
66 * MacIO interface
67 */
68 static int cuda_probe(device_t);
69 static int cuda_attach(device_t);
70 static int cuda_detach(device_t);
71
72 static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
73 u_char *data, u_char poll);
74 static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
75 static u_int cuda_poll(device_t dev);
76 static void cuda_send_inbound(struct cuda_softc *sc);
77 static void cuda_send_outbound(struct cuda_softc *sc);
78 static void cuda_shutdown(void *xsc, int howto);
79
80 /*
81 * Clock interface
82 */
83 static int cuda_gettime(device_t dev, struct timespec *ts);
84 static int cuda_settime(device_t dev, struct timespec *ts);
85
86 static device_method_t cuda_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, cuda_probe),
89 DEVMETHOD(device_attach, cuda_attach),
90 DEVMETHOD(device_detach, cuda_detach),
91 DEVMETHOD(device_shutdown, bus_generic_shutdown),
92 DEVMETHOD(device_suspend, bus_generic_suspend),
93 DEVMETHOD(device_resume, bus_generic_resume),
94
95 /* ADB bus interface */
96 DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
97 DEVMETHOD(adb_hb_controller_poll, cuda_poll),
98 DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
99
100 /* Clock interface */
101 DEVMETHOD(clock_gettime, cuda_gettime),
102 DEVMETHOD(clock_settime, cuda_settime),
103
104 DEVMETHOD_END
105 };
106
107 static driver_t cuda_driver = {
108 "cuda",
109 cuda_methods,
110 sizeof(struct cuda_softc),
111 };
112
113 static devclass_t cuda_devclass;
114
115 DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
116 DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
117
118 static void cuda_intr(void *arg);
119 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
120 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
121 static void cuda_idle(struct cuda_softc *);
122 static void cuda_tip(struct cuda_softc *);
123 static void cuda_clear_tip(struct cuda_softc *);
124 static void cuda_in(struct cuda_softc *);
125 static void cuda_out(struct cuda_softc *);
126 static void cuda_toggle_ack(struct cuda_softc *);
127 static void cuda_ack_off(struct cuda_softc *);
128 static int cuda_intr_state(struct cuda_softc *);
129
130 static int
cuda_probe(device_t dev)131 cuda_probe(device_t dev)
132 {
133 const char *type = ofw_bus_get_type(dev);
134
135 if (strcmp(type, "via-cuda") != 0)
136 return (ENXIO);
137
138 device_set_desc(dev, CUDA_DEVSTR);
139 return (0);
140 }
141
142 static int
cuda_attach(device_t dev)143 cuda_attach(device_t dev)
144 {
145 struct cuda_softc *sc;
146
147 volatile int i;
148 uint8_t reg;
149 phandle_t node,child;
150
151 sc = device_get_softc(dev);
152 sc->sc_dev = dev;
153
154 sc->sc_memrid = 0;
155 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
156 &sc->sc_memrid, RF_ACTIVE);
157
158 if (sc->sc_memr == NULL) {
159 device_printf(dev, "Could not alloc mem resource!\n");
160 return (ENXIO);
161 }
162
163 sc->sc_irqrid = 0;
164 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
165 RF_ACTIVE);
166 if (sc->sc_irq == NULL) {
167 device_printf(dev, "could not allocate interrupt\n");
168 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
169 sc->sc_memr);
170 return (ENXIO);
171 }
172
173 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
174 | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
175 device_printf(dev, "could not setup interrupt\n");
176 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
177 sc->sc_memr);
178 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
179 sc->sc_irq);
180 return (ENXIO);
181 }
182
183 mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
184
185 sc->sc_sent = 0;
186 sc->sc_received = 0;
187 sc->sc_waiting = 0;
188 sc->sc_polling = 0;
189 sc->sc_state = CUDA_NOTREADY;
190 sc->sc_autopoll = 0;
191 sc->sc_rtc = -1;
192
193 STAILQ_INIT(&sc->sc_inq);
194 STAILQ_INIT(&sc->sc_outq);
195 STAILQ_INIT(&sc->sc_freeq);
196
197 for (i = 0; i < CUDA_MAXPACKETS; i++)
198 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
199
200 /* Init CUDA */
201
202 reg = cuda_read_reg(sc, vDirB);
203 reg |= 0x30; /* register B bits 4 and 5: outputs */
204 cuda_write_reg(sc, vDirB, reg);
205
206 reg = cuda_read_reg(sc, vDirB);
207 reg &= 0xf7; /* register B bit 3: input */
208 cuda_write_reg(sc, vDirB, reg);
209
210 reg = cuda_read_reg(sc, vACR);
211 reg &= ~vSR_OUT; /* make sure SR is set to IN */
212 cuda_write_reg(sc, vACR, reg);
213
214 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
215
216 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
217
218 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
219
220 cuda_idle(sc); /* reset ADB */
221
222 /* Reset CUDA */
223
224 i = cuda_read_reg(sc, vSR); /* clear interrupt */
225 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
226 cuda_idle(sc); /* reset state to idle */
227 DELAY(150);
228 cuda_tip(sc); /* signal start of frame */
229 DELAY(150);
230 cuda_toggle_ack(sc);
231 DELAY(150);
232 cuda_clear_tip(sc);
233 DELAY(150);
234 cuda_idle(sc); /* back to idle state */
235 i = cuda_read_reg(sc, vSR); /* clear interrupt */
236 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
237
238 /* Initialize child buses (ADB) */
239 node = ofw_bus_get_node(dev);
240
241 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
242 char name[32];
243
244 memset(name, 0, sizeof(name));
245 OF_getprop(child, "name", name, sizeof(name));
246
247 if (bootverbose)
248 device_printf(dev, "CUDA child <%s>\n",name);
249
250 if (strncmp(name, "adb", 4) == 0) {
251 sc->adb_bus = device_add_child(dev,"adb",-1);
252 }
253 }
254
255 clock_register(dev, 1000);
256 EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
257 SHUTDOWN_PRI_LAST);
258
259 return (bus_generic_attach(dev));
260 }
261
cuda_detach(device_t dev)262 static int cuda_detach(device_t dev) {
263 struct cuda_softc *sc;
264
265 sc = device_get_softc(dev);
266
267 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
268 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
269 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
270 mtx_destroy(&sc->sc_mutex);
271
272 return (bus_generic_detach(dev));
273 }
274
275 static uint8_t
cuda_read_reg(struct cuda_softc * sc,u_int offset)276 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
277 return (bus_read_1(sc->sc_memr, offset));
278 }
279
280 static void
cuda_write_reg(struct cuda_softc * sc,u_int offset,uint8_t value)281 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
282 bus_write_1(sc->sc_memr, offset, value);
283 }
284
285 static void
cuda_idle(struct cuda_softc * sc)286 cuda_idle(struct cuda_softc *sc)
287 {
288 uint8_t reg;
289
290 reg = cuda_read_reg(sc, vBufB);
291 reg |= (vPB4 | vPB5);
292 cuda_write_reg(sc, vBufB, reg);
293 }
294
295 static void
cuda_tip(struct cuda_softc * sc)296 cuda_tip(struct cuda_softc *sc)
297 {
298 uint8_t reg;
299
300 reg = cuda_read_reg(sc, vBufB);
301 reg &= ~vPB5;
302 cuda_write_reg(sc, vBufB, reg);
303 }
304
305 static void
cuda_clear_tip(struct cuda_softc * sc)306 cuda_clear_tip(struct cuda_softc *sc)
307 {
308 uint8_t reg;
309
310 reg = cuda_read_reg(sc, vBufB);
311 reg |= vPB5;
312 cuda_write_reg(sc, vBufB, reg);
313 }
314
315 static void
cuda_in(struct cuda_softc * sc)316 cuda_in(struct cuda_softc *sc)
317 {
318 uint8_t reg;
319
320 reg = cuda_read_reg(sc, vACR);
321 reg &= ~vSR_OUT;
322 cuda_write_reg(sc, vACR, reg);
323 }
324
325 static void
cuda_out(struct cuda_softc * sc)326 cuda_out(struct cuda_softc *sc)
327 {
328 uint8_t reg;
329
330 reg = cuda_read_reg(sc, vACR);
331 reg |= vSR_OUT;
332 cuda_write_reg(sc, vACR, reg);
333 }
334
335 static void
cuda_toggle_ack(struct cuda_softc * sc)336 cuda_toggle_ack(struct cuda_softc *sc)
337 {
338 uint8_t reg;
339
340 reg = cuda_read_reg(sc, vBufB);
341 reg ^= vPB4;
342 cuda_write_reg(sc, vBufB, reg);
343 }
344
345 static void
cuda_ack_off(struct cuda_softc * sc)346 cuda_ack_off(struct cuda_softc *sc)
347 {
348 uint8_t reg;
349
350 reg = cuda_read_reg(sc, vBufB);
351 reg |= vPB4;
352 cuda_write_reg(sc, vBufB, reg);
353 }
354
355 static int
cuda_intr_state(struct cuda_softc * sc)356 cuda_intr_state(struct cuda_softc *sc)
357 {
358 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
359 }
360
361 static int
cuda_send(void * cookie,int poll,int length,uint8_t * msg)362 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
363 {
364 struct cuda_softc *sc = cookie;
365 device_t dev = sc->sc_dev;
366 struct cuda_packet *pkt;
367
368 if (sc->sc_state == CUDA_NOTREADY)
369 return (-1);
370
371 mtx_lock(&sc->sc_mutex);
372
373 pkt = STAILQ_FIRST(&sc->sc_freeq);
374 if (pkt == NULL) {
375 mtx_unlock(&sc->sc_mutex);
376 return (-1);
377 }
378
379 pkt->len = length - 1;
380 pkt->type = msg[0];
381 memcpy(pkt->data, &msg[1], pkt->len);
382
383 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
384 STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
385
386 /*
387 * If we already are sending a packet, we should bail now that this
388 * one has been added to the queue.
389 */
390
391 if (sc->sc_waiting) {
392 mtx_unlock(&sc->sc_mutex);
393 return (0);
394 }
395
396 cuda_send_outbound(sc);
397 mtx_unlock(&sc->sc_mutex);
398
399 if (sc->sc_polling || poll || cold)
400 cuda_poll(dev);
401
402 return (0);
403 }
404
405 static void
cuda_send_outbound(struct cuda_softc * sc)406 cuda_send_outbound(struct cuda_softc *sc)
407 {
408 struct cuda_packet *pkt;
409
410 mtx_assert(&sc->sc_mutex, MA_OWNED);
411
412 pkt = STAILQ_FIRST(&sc->sc_outq);
413 if (pkt == NULL)
414 return;
415
416 sc->sc_out_length = pkt->len + 1;
417 memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
418 sc->sc_sent = 0;
419
420 STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
421 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
422
423 sc->sc_waiting = 1;
424
425 cuda_poll(sc->sc_dev);
426
427 DELAY(150);
428
429 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
430 sc->sc_state = CUDA_OUT;
431 cuda_out(sc);
432 cuda_write_reg(sc, vSR, sc->sc_out[0]);
433 cuda_ack_off(sc);
434 cuda_tip(sc);
435 }
436 }
437
438 static void
cuda_send_inbound(struct cuda_softc * sc)439 cuda_send_inbound(struct cuda_softc *sc)
440 {
441 device_t dev;
442 struct cuda_packet *pkt;
443
444 dev = sc->sc_dev;
445
446 mtx_lock(&sc->sc_mutex);
447
448 while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
449 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
450
451 mtx_unlock(&sc->sc_mutex);
452
453 /* check if we have a handler for this message */
454 switch (pkt->type) {
455 case CUDA_ADB:
456 if (pkt->len > 2) {
457 adb_receive_raw_packet(sc->adb_bus,
458 pkt->data[0],pkt->data[1],
459 pkt->len - 2,&pkt->data[2]);
460 } else {
461 adb_receive_raw_packet(sc->adb_bus,
462 pkt->data[0],pkt->data[1],0,NULL);
463 }
464 break;
465 case CUDA_PSEUDO:
466 mtx_lock(&sc->sc_mutex);
467 switch (pkt->data[1]) {
468 case CMD_AUTOPOLL:
469 sc->sc_autopoll = 1;
470 break;
471 case CMD_READ_RTC:
472 memcpy(&sc->sc_rtc, &pkt->data[2],
473 sizeof(sc->sc_rtc));
474 wakeup(&sc->sc_rtc);
475 break;
476 case CMD_WRITE_RTC:
477 break;
478 }
479 mtx_unlock(&sc->sc_mutex);
480 break;
481 case CUDA_ERROR:
482 /*
483 * CUDA will throw errors if we miss a race between
484 * sending and receiving packets. This is already
485 * handled when we abort packet output to handle
486 * this packet in cuda_intr(). Thus, we ignore
487 * these messages.
488 */
489 break;
490 default:
491 device_printf(dev,"unknown CUDA command %d\n",
492 pkt->type);
493 break;
494 }
495
496 mtx_lock(&sc->sc_mutex);
497
498 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
499 }
500
501 mtx_unlock(&sc->sc_mutex);
502 }
503
504 static u_int
cuda_poll(device_t dev)505 cuda_poll(device_t dev)
506 {
507 struct cuda_softc *sc = device_get_softc(dev);
508
509 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
510 !sc->sc_waiting)
511 return (0);
512
513 cuda_intr(dev);
514 return (0);
515 }
516
517 static void
cuda_intr(void * arg)518 cuda_intr(void *arg)
519 {
520 device_t dev;
521 struct cuda_softc *sc;
522
523 int i, ending, restart_send, process_inbound;
524 uint8_t reg;
525
526 dev = (device_t)arg;
527 sc = device_get_softc(dev);
528
529 mtx_lock(&sc->sc_mutex);
530
531 restart_send = 0;
532 process_inbound = 0;
533 reg = cuda_read_reg(sc, vIFR);
534 if ((reg & vSR_INT) != vSR_INT) {
535 mtx_unlock(&sc->sc_mutex);
536 return;
537 }
538
539 cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
540
541 switch_start:
542 switch (sc->sc_state) {
543 case CUDA_IDLE:
544 /*
545 * This is an unexpected packet, so grab the first (dummy)
546 * byte, set up the proper vars, and tell the chip we are
547 * starting to receive the packet by setting the TIP bit.
548 */
549 sc->sc_in[1] = cuda_read_reg(sc, vSR);
550
551 if (cuda_intr_state(sc) == 0) {
552 /* must have been a fake start */
553
554 if (sc->sc_waiting) {
555 /* start over */
556 DELAY(150);
557 sc->sc_state = CUDA_OUT;
558 sc->sc_sent = 0;
559 cuda_out(sc);
560 cuda_write_reg(sc, vSR, sc->sc_out[1]);
561 cuda_ack_off(sc);
562 cuda_tip(sc);
563 }
564 break;
565 }
566
567 cuda_in(sc);
568 cuda_tip(sc);
569
570 sc->sc_received = 1;
571 sc->sc_state = CUDA_IN;
572 break;
573
574 case CUDA_IN:
575 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
576 ending = 0;
577
578 if (sc->sc_received > 255) {
579 /* bitch only once */
580 if (sc->sc_received == 256) {
581 device_printf(dev,"input overflow\n");
582 ending = 1;
583 }
584 } else
585 sc->sc_received++;
586
587 /* intr off means this is the last byte (end of frame) */
588 if (cuda_intr_state(sc) == 0) {
589 ending = 1;
590 } else {
591 cuda_toggle_ack(sc);
592 }
593
594 if (ending == 1) { /* end of message? */
595 struct cuda_packet *pkt;
596
597 /* reset vars and signal the end of this frame */
598 cuda_idle(sc);
599
600 /* Queue up the packet */
601 pkt = STAILQ_FIRST(&sc->sc_freeq);
602 if (pkt != NULL) {
603 /* If we have a free packet, process it */
604
605 pkt->len = sc->sc_received - 2;
606 pkt->type = sc->sc_in[1];
607 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
608
609 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
610 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
611
612 process_inbound = 1;
613 }
614
615 sc->sc_state = CUDA_IDLE;
616 sc->sc_received = 0;
617
618 /*
619 * If there is something waiting to be sent out,
620 * set everything up and send the first byte.
621 */
622 if (sc->sc_waiting == 1) {
623 DELAY(1500); /* required */
624 sc->sc_sent = 0;
625 sc->sc_state = CUDA_OUT;
626
627 /*
628 * If the interrupt is on, we were too slow
629 * and the chip has already started to send
630 * something to us, so back out of the write
631 * and start a read cycle.
632 */
633 if (cuda_intr_state(sc)) {
634 cuda_in(sc);
635 cuda_idle(sc);
636 sc->sc_sent = 0;
637 sc->sc_state = CUDA_IDLE;
638 sc->sc_received = 0;
639 DELAY(150);
640 goto switch_start;
641 }
642
643 /*
644 * If we got here, it's ok to start sending
645 * so load the first byte and tell the chip
646 * we want to send.
647 */
648 cuda_out(sc);
649 cuda_write_reg(sc, vSR,
650 sc->sc_out[sc->sc_sent]);
651 cuda_ack_off(sc);
652 cuda_tip(sc);
653 }
654 }
655 break;
656
657 case CUDA_OUT:
658 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
659
660 sc->sc_sent++;
661 if (cuda_intr_state(sc)) { /* ADB intr low during write */
662 cuda_in(sc); /* make sure SR is set to IN */
663 cuda_idle(sc);
664 sc->sc_sent = 0; /* must start all over */
665 sc->sc_state = CUDA_IDLE; /* new state */
666 sc->sc_received = 0;
667 sc->sc_waiting = 1; /* must retry when done with
668 * read */
669 DELAY(150);
670 goto switch_start; /* process next state right
671 * now */
672 break;
673 }
674 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
675 sc->sc_waiting = 0; /* done writing */
676 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
677 cuda_in(sc);
678 cuda_idle(sc);
679 } else {
680 /* send next byte */
681 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
682 cuda_toggle_ack(sc); /* signal byte ready to
683 * shift */
684 }
685 break;
686
687 case CUDA_NOTREADY:
688 break;
689
690 default:
691 break;
692 }
693
694 mtx_unlock(&sc->sc_mutex);
695
696 if (process_inbound)
697 cuda_send_inbound(sc);
698
699 mtx_lock(&sc->sc_mutex);
700 /* If we have another packet waiting, set it up */
701 if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
702 cuda_send_outbound(sc);
703
704 mtx_unlock(&sc->sc_mutex);
705
706 }
707
708 static u_int
cuda_adb_send(device_t dev,u_char command_byte,int len,u_char * data,u_char poll)709 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
710 u_char poll)
711 {
712 struct cuda_softc *sc = device_get_softc(dev);
713 uint8_t packet[16];
714 int i;
715
716 /* construct an ADB command packet and send it */
717 packet[0] = CUDA_ADB;
718 packet[1] = command_byte;
719 for (i = 0; i < len; i++)
720 packet[i + 2] = data[i];
721
722 cuda_send(sc, poll, len + 2, packet);
723
724 return (0);
725 }
726
727 static u_int
cuda_adb_autopoll(device_t dev,uint16_t mask)728 cuda_adb_autopoll(device_t dev, uint16_t mask) {
729 struct cuda_softc *sc = device_get_softc(dev);
730
731 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
732
733 mtx_lock(&sc->sc_mutex);
734
735 if (cmd[2] == sc->sc_autopoll) {
736 mtx_unlock(&sc->sc_mutex);
737 return (0);
738 }
739
740 sc->sc_autopoll = -1;
741 cuda_send(sc, 1, 3, cmd);
742
743 mtx_unlock(&sc->sc_mutex);
744
745 return (0);
746 }
747
748 static void
cuda_shutdown(void * xsc,int howto)749 cuda_shutdown(void *xsc, int howto)
750 {
751 struct cuda_softc *sc = xsc;
752 uint8_t cmd[] = {CUDA_PSEUDO, 0};
753
754 cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET;
755 cuda_poll(sc->sc_dev);
756 cuda_send(sc, 1, 2, cmd);
757
758 while (1)
759 cuda_poll(sc->sc_dev);
760 }
761
762 #define DIFF19041970 2082844800
763
764 static int
cuda_gettime(device_t dev,struct timespec * ts)765 cuda_gettime(device_t dev, struct timespec *ts)
766 {
767 struct cuda_softc *sc = device_get_softc(dev);
768 uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
769
770 mtx_lock(&sc->sc_mutex);
771 sc->sc_rtc = -1;
772 cuda_send(sc, 1, 2, cmd);
773 if (sc->sc_rtc == -1)
774 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
775
776 ts->tv_sec = sc->sc_rtc - DIFF19041970;
777 ts->tv_nsec = 0;
778 mtx_unlock(&sc->sc_mutex);
779
780 return (0);
781 }
782
783 static int
cuda_settime(device_t dev,struct timespec * ts)784 cuda_settime(device_t dev, struct timespec *ts)
785 {
786 struct cuda_softc *sc = device_get_softc(dev);
787 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
788 uint32_t sec;
789
790 sec = ts->tv_sec + DIFF19041970;
791 memcpy(&cmd[2], &sec, sizeof(sec));
792
793 mtx_lock(&sc->sc_mutex);
794 cuda_send(sc, 0, 6, cmd);
795 mtx_unlock(&sc->sc_mutex);
796
797 return (0);
798 }
799
800