1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1993 Herb Peyerl ([email protected]) All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 2. The name 10 * of the author may not be used to endorse or promote products derived from 11 * this software without specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 16 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 18 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 19 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 20 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 21 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 22 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $FreeBSD$ 25 */ 26 27 /* 28 * Created from if_epreg.h by Fred Gray ([email protected]) to support the 29 * 3c590 family. 30 */ 31 32 /* 33 * Some global constants 34 */ 35 36 #define TX_INIT_RATE 16 37 #define TX_INIT_MAX_RATE 64 38 #define RX_INIT_LATENCY 64 39 #define RX_INIT_EARLY_THRESH 64 40 #define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 41 #define MIN_RX_EARLY_THRESHL 4 42 43 #define EEPROMSIZE 0x40 44 #define MAX_EEPROMBUSY 1000 45 #define VX_LAST_TAG 0xd7 46 #define VX_MAX_BOARDS 16 47 48 /* 49 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 50 * Offset 0xa) 51 */ 52 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 53 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 54 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 55 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 56 57 #define EEPROM_BUSY (1<<15) 58 #define EEPROM_TST_MODE (1<<14) 59 60 /* 61 * Some short functions, worth to let them be a macro 62 */ 63 #define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x)) 64 65 /************************************************************************** 66 * * 67 * These define the EEPROM data structure. They are used in the probe 68 * function to verify the existence of the adapter after having sent 69 * the ID_Sequence. 70 * 71 **************************************************************************/ 72 73 #define EEPROM_NODE_ADDR_0 0x0 /* Word */ 74 #define EEPROM_NODE_ADDR_1 0x1 /* Word */ 75 #define EEPROM_NODE_ADDR_2 0x2 /* Word */ 76 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 77 #define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 78 #define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 79 #define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 80 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 81 #define EEPROM_ADDR_CFG 0x8 /* Base addr */ 82 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 83 #define EEPROM_OEM_ADDR0 0xa 84 #define EEPROM_OEM_ADDR1 0xb 85 #define EEPROM_OEM_ADDR2 0xc 86 #define EEPROM_SOFTINFO 0xd 87 #define EEPROM_COMPAT 0xe 88 #define EEPROM_SOFTINFO2 0xf 89 #define EEPROM_CAP 0x10 90 #define EEPROM_INT_CONFIG_0 0x12 91 #define EEPROM_INT_CONFIG_1 0x13 92 /* RAM Partition TX FIFO/RX FIFO */ 93 #define ICW1_RAM_PART_MASK 0x03 94 #define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b 95 * default power-up/reset */ 96 #define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size == 97 * 000b) */ 98 #define ICW1_RAM_PART_11 0x10 /* 1:1 */ 99 #define ICW1_RAM_PART_RESV 0x11 /* Reserved */ 100 /* ISA Adapter Selection */ 101 #define ICW1_IAS_MASK 0x0c 102 #define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */ 103 #define ICW1_IAS_ISA 0x04 /* ISA contention only */ 104 #define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */ 105 #define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */ 106 107 #define EEPROM_CHECKSUM_EL3 0x17 108 109 #define NO_RX_OVN_ANOMALY (1<<5) 110 111 /************************************************************************** 112 * These are the registers for the 3Com 3c509 and their bit patterns when * 113 * applicable. They have been taken out the "EtherLink III Parallel * 114 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 115 * from 3com. * 116 **************************************************************************/ 117 #define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a 118 * command reg. */ 119 #define VX_STATUS 0x0e /* Read. BASE+0x0e is always status 120 * reg. */ 121 #define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window 122 * reg. */ 123 /* 124 * Window 0 registers. Setup. 125 */ 126 /* Write */ 127 #define VX_W0_EEPROM_DATA 0x0c 128 #define VX_W0_EEPROM_COMMAND 0x0a 129 #define VX_W0_RESOURCE_CFG 0x08 130 #define VX_W0_ADDRESS_CFG 0x06 131 #define VX_W0_CONFIG_CTRL 0x04 132 /* Read */ 133 #define VX_W0_PRODUCT_ID 0x02 134 #define VX_W0_MFG_ID 0x00 135 136 /* 137 * Window 1 registers. Operating Set. 138 */ 139 /* Write */ 140 #define VX_W1_TX_PIO_WR_2 0x02 141 #define VX_W1_TX_PIO_WR_1 0x00 142 /* Read */ 143 #define VX_W1_FREE_TX 0x0c 144 #define VX_W1_TX_STATUS 0x0b /* byte */ 145 #define VX_W1_TIMER 0x0a /* byte */ 146 #define VX_W1_RX_STATUS 0x08 147 #define VX_W1_RX_PIO_RD_2 0x02 148 #define VX_W1_RX_PIO_RD_1 0x00 149 150 /* 151 * Window 2 registers. Station Address Setup/Read 152 */ 153 /* Read/Write */ 154 #define VX_W2_ADDR_5 0x05 155 #define VX_W2_ADDR_4 0x04 156 #define VX_W2_ADDR_3 0x03 157 #define VX_W2_ADDR_2 0x02 158 #define VX_W2_ADDR_1 0x01 159 #define VX_W2_ADDR_0 0x00 160 161 /* 162 * Window 3 registers. FIFO Management. 163 */ 164 /* Read */ 165 #define VX_W3_INTERNAL_CFG 0x00 166 #define VX_W3_RESET_OPT 0x08 167 #define VX_W3_FREE_TX 0x0c 168 #define VX_W3_FREE_RX 0x0a 169 170 /* 171 * Window 4 registers. Diagnostics. 172 */ 173 /* Read/Write */ 174 #define VX_W4_MEDIA_TYPE 0x0a 175 #define VX_W4_CTRLR_STATUS 0x08 176 #define VX_W4_NET_DIAG 0x06 177 #define VX_W4_FIFO_DIAG 0x04 178 #define VX_W4_HOST_DIAG 0x02 179 #define VX_W4_TX_DIAG 0x00 180 181 /* 182 * Window 5 Registers. Results and Internal status. 183 */ 184 /* Read */ 185 #define VX_W5_READ_0_MASK 0x0c 186 #define VX_W5_INTR_MASK 0x0a 187 #define VX_W5_RX_FILTER 0x08 188 #define VX_W5_RX_EARLY_THRESH 0x06 189 #define VX_W5_TX_AVAIL_THRESH 0x02 190 #define VX_W5_TX_START_THRESH 0x00 191 192 /* 193 * Window 6 registers. Statistics. 194 */ 195 /* Read/Write */ 196 #define TX_TOTAL_OK 0x0c 197 #define RX_TOTAL_OK 0x0a 198 #define TX_DEFERRALS 0x08 199 #define RX_FRAMES_OK 0x07 200 #define TX_FRAMES_OK 0x06 201 #define RX_OVERRUNS 0x05 202 #define TX_COLLISIONS 0x04 203 #define TX_AFTER_1_COLLISION 0x03 204 #define TX_AFTER_X_COLLISIONS 0x02 205 #define TX_NO_SQE 0x01 206 #define TX_CD_LOST 0x00 207 208 /**************************************** 209 * 210 * Register definitions. 211 * 212 ****************************************/ 213 214 /* 215 * Command register. All windows. 216 * 217 * 16 bit register. 218 * 15-11: 5-bit code for command to be executed. 219 * 10-0: 11-bit arg if any. For commands with no args; 220 * this can be set to anything. 221 */ 222 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 223 * after issuing */ 224 #define WINDOW_SELECT (u_short) (0x1<<11) 225 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 226 * determine whether 227 * this is needed. If 228 * so; wait 800 uSec 229 * before using trans- 230 * ceiver. */ 231 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 232 * power-up */ 233 #define RX_ENABLE (u_short) (0x4<<11) 234 #define RX_RESET (u_short) (0x5<<11) 235 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 236 #define TX_ENABLE (u_short) (0x9<<11) 237 #define TX_DISABLE (u_short) (0xa<<11) 238 #define TX_RESET (u_short) (0xb<<11) 239 #define REQ_INTR (u_short) (0xc<<11) 240 /* 241 * The following C_* acknowledge the various interrupts. 242 * Some of them don't do anything. See the manual. 243 */ 244 #define ACK_INTR (u_short) (0x6800) 245 #define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 246 #define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 247 #define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 248 #define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 249 #define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 250 #define C_RX_EARLY (u_short) (ACK_INTR|0x20) 251 #define C_INT_RQD (u_short) (ACK_INTR|0x40) 252 #define C_UPD_STATS (u_short) (ACK_INTR|0x80) 253 #define SET_INTR_MASK (u_short) (0xe<<11) 254 #define SET_RD_0_MASK (u_short) (0xf<<11) 255 #define SET_RX_FILTER (u_short) (0x10<<11) 256 #define FIL_INDIVIDUAL (u_short) (0x1) 257 #define FIL_MULTICAST (u_short) (0x02) 258 #define FIL_BRDCST (u_short) (0x04) 259 #define FIL_PROMISC (u_short) (0x08) 260 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 261 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 262 #define SET_TX_START_THRESH (u_short) (0x13<<11) 263 #define STATS_ENABLE (u_short) (0x15<<11) 264 #define STATS_DISABLE (u_short) (0x16<<11) 265 #define STOP_TRANSCEIVER (u_short) (0x17<<11) 266 267 /* 268 * Status register. All windows. 269 * 270 * 15-13: Window number(0-7). 271 * 12: Command_in_progress. 272 * 11: reserved. 273 * 10: reserved. 274 * 9: reserved. 275 * 8: reserved. 276 * 7: Update Statistics. 277 * 6: Interrupt Requested. 278 * 5: RX Early. 279 * 4: RX Complete. 280 * 3: TX Available. 281 * 2: TX Complete. 282 * 1: Adapter Failure. 283 * 0: Interrupt Latch. 284 */ 285 #define S_INTR_LATCH (u_short) (0x1) 286 #define S_CARD_FAILURE (u_short) (0x2) 287 #define S_TX_COMPLETE (u_short) (0x4) 288 #define S_TX_AVAIL (u_short) (0x8) 289 #define S_RX_COMPLETE (u_short) (0x10) 290 #define S_RX_EARLY (u_short) (0x20) 291 #define S_INT_RQD (u_short) (0x40) 292 #define S_UPD_STATS (u_short) (0x80) 293 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 294 295 #define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS) 296 297 /* Address Config. Register. 298 * Window 0/Port 06 299 */ 300 301 #define ACF_CONNECTOR_BITS 14 302 #define ACF_CONNECTOR_UTP 0 303 #define ACF_CONNECTOR_AUI 1 304 #define ACF_CONNECTOR_BNC 3 305 306 #define INTERNAL_CONNECTOR_BITS 20 307 #define INTERNAL_CONNECTOR_MASK 0x01700000 308 309 /* 310 * FIFO Registers. RX Status. 311 * 312 * 15: Incomplete or FIFO empty. 313 * 14: 1: Error in RX Packet 0: Incomplete or no error. 314 * 13-11: Type of error. 315 * 1000 = Overrun. 316 * 1011 = Run Packet Error. 317 * 1100 = Alignment Error. 318 * 1101 = CRC Error. 319 * 1001 = Oversize Packet Error (>1514 bytes) 320 * 0010 = Dribble Bits. 321 * (all other error codes, no errors.) 322 * 323 * 10-0: RX Bytes (0-1514) 324 */ 325 #define ERR_INCOMPLETE (u_short) (0x8000) 326 #define ERR_RX (u_short) (0x4000) 327 #define ERR_MASK (u_short) (0x7800) 328 #define ERR_OVERRUN (u_short) (0x4000) 329 #define ERR_RUNT (u_short) (0x5800) 330 #define ERR_ALIGNMENT (u_short) (0x6000) 331 #define ERR_CRC (u_short) (0x6800) 332 #define ERR_OVERSIZE (u_short) (0x4800) 333 #define ERR_DRIBBLE (u_short) (0x1000) 334 335 /* 336 * TX Status. 337 * 338 * Reports the transmit status of a completed transmission. Writing this 339 * register pops the transmit completion stack. 340 * 341 * Window 1/Port 0x0b. 342 * 343 * 7: Complete 344 * 6: Interrupt on successful transmission requested. 345 * 5: Jabber Error (TP Only, TX Reset required. ) 346 * 4: Underrun (TX Reset required. ) 347 * 3: Maximum Collisions. 348 * 2: TX Status Overflow. 349 * 1-0: Undefined. 350 * 351 */ 352 #define TXS_COMPLETE 0x80 353 #define TXS_INTR_REQ 0x40 354 #define TXS_JABBER 0x20 355 #define TXS_UNDERRUN 0x10 356 #define TXS_MAX_COLLISION 0x8 357 #define TXS_STATUS_OVERFLOW 0x4 358 359 #define RS_AUI (1<<5) 360 #define RS_BNC (1<<4) 361 #define RS_UTP (1<<3) 362 #define RS_T4 (1<<0) 363 #define RS_TX (1<<1) 364 #define RS_FX (1<<2) 365 #define RS_MII (1<<6) 366 367 368 /* 369 * FIFO Status (Window 4) 370 * 371 * Supports FIFO diagnostics 372 * 373 * Window 4/Port 0x04.1 374 * 375 * 15: 1=RX receiving (RO). Set when a packet is being received 376 * into the RX FIFO. 377 * 14: Reserved 378 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 379 * Requires RX Reset or Global Reset command to recover. 380 * It is generated when you read past the end of a packet - 381 * reading past what has been received so far will give bad 382 * data. 383 * 12: 1=RX status overrun (RO). Set when there are already 8 384 * packets in the RX FIFO. While this bit is set, no additional 385 * packets are received. Requires no action on the part of 386 * the host. The condition is cleared once a packet has been 387 * read out of the RX FIFO. 388 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 389 * may not be an overrun packet yet). While this bit is set, 390 * no additional packets will be received (some additional 391 * bytes can still be pending between the wire and the RX 392 * FIFO). Requires no action on the part of the host. The 393 * condition is cleared once a few bytes have been read out 394 * from the RX FIFO. 395 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 396 * Requires TX Reset or Global Reset command to recover. 397 * Disables Transmitter. 398 * 9-8: Unassigned. 399 * 7-0: Built in self test bits for the RX and TX FIFO's. 400 */ 401 #define FIFOS_RX_RECEIVING (u_short) 0x8000 402 #define FIFOS_RX_UNDERRUN (u_short) 0x2000 403 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000 404 #define FIFOS_RX_OVERRUN (u_short) 0x0800 405 #define FIFOS_TX_OVERRUN (u_short) 0x0400 406 407 /* 408 * Misc defines for various things. 409 */ 410 #define TAG_ADAPTER 0xd0 411 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff 412 #define ENABLE_DRQ_IRQ 0x0001 413 #define MFG_ID 0x506d /* `TCM' */ 414 #define PROD_ID 0x5090 415 #define JABBER_GUARD_ENABLE 0x40 416 #define LINKBEAT_ENABLE 0x80 417 #define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 418 #define DISABLE_UTP 0x0 419 #define RX_BYTES_MASK (u_short) (0x07ff) 420 #define TX_INDICATE (1<<15) 421 422 #define VX_IOSIZE 0x20 423 424 #define VX_CONNECTORS 8 425