1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31 #include "opt_uart.h"
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/conf.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <machine/bus.h>
43
44 #ifdef FDT
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 #endif
49
50 #include <dev/uart/uart.h>
51 #include <dev/uart/uart_cpu.h>
52 #ifdef FDT
53 #include <dev/uart/uart_cpu_fdt.h>
54 #endif
55 #include <dev/uart/uart_bus.h>
56 #include <dev/uart/uart_dev_ns8250.h>
57 #include <dev/uart/uart_ppstypes.h>
58 #ifdef DEV_ACPI
59 #include <dev/uart/uart_cpu_acpi.h>
60 #endif
61
62 #include <dev/ic/ns16550.h>
63
64 #include "uart_if.h"
65
66 #define DEFAULT_RCLK 1843200
67
68 /*
69 * Set the default baudrate tolerance to 3.0%.
70 *
71 * Some embedded boards have odd reference clocks (eg 25MHz)
72 * and we need to handle higher variances in the target baud rate.
73 */
74 #ifndef UART_DEV_TOLERANCE_PCT
75 #define UART_DEV_TOLERANCE_PCT 30
76 #endif /* UART_DEV_TOLERANCE_PCT */
77
78 static int broken_txfifo = 0;
79 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
80 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
81
82 /*
83 * Clear pending interrupts. THRE is cleared by reading IIR. Data
84 * that may have been received gets lost here.
85 */
86 static void
ns8250_clrint(struct uart_bas * bas)87 ns8250_clrint(struct uart_bas *bas)
88 {
89 uint8_t iir, lsr;
90
91 iir = uart_getreg(bas, REG_IIR);
92 while ((iir & IIR_NOPEND) == 0) {
93 iir &= IIR_IMASK;
94 if (iir == IIR_RLS) {
95 lsr = uart_getreg(bas, REG_LSR);
96 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
97 (void)uart_getreg(bas, REG_DATA);
98 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
99 (void)uart_getreg(bas, REG_DATA);
100 else if (iir == IIR_MLSC)
101 (void)uart_getreg(bas, REG_MSR);
102 uart_barrier(bas);
103 iir = uart_getreg(bas, REG_IIR);
104 }
105 }
106
107 static int
ns8250_delay(struct uart_bas * bas)108 ns8250_delay(struct uart_bas *bas)
109 {
110 int divisor;
111 u_char lcr;
112
113 lcr = uart_getreg(bas, REG_LCR);
114 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
115 uart_barrier(bas);
116 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
117 uart_barrier(bas);
118 uart_setreg(bas, REG_LCR, lcr);
119 uart_barrier(bas);
120
121 /* 1/10th the time to transmit 1 character (estimate). */
122 if (divisor <= 134)
123 return (16000000 * divisor / bas->rclk);
124 return (16000 * divisor / (bas->rclk / 1000));
125 }
126
127 static int
ns8250_divisor(int rclk,int baudrate)128 ns8250_divisor(int rclk, int baudrate)
129 {
130 int actual_baud, divisor;
131 int error;
132
133 if (baudrate == 0)
134 return (0);
135
136 divisor = (rclk / (baudrate << 3) + 1) >> 1;
137 if (divisor == 0 || divisor >= 65536)
138 return (0);
139 actual_baud = rclk / (divisor << 4);
140
141 /* 10 times error in percent: */
142 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
143
144 /* enforce maximum error tolerance: */
145 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
146 return (0);
147
148 return (divisor);
149 }
150
151 static int
ns8250_drain(struct uart_bas * bas,int what)152 ns8250_drain(struct uart_bas *bas, int what)
153 {
154 int delay, limit;
155
156 delay = ns8250_delay(bas);
157
158 if (what & UART_DRAIN_TRANSMITTER) {
159 /*
160 * Pick an arbitrary high limit to avoid getting stuck in
161 * an infinite loop when the hardware is broken. Make the
162 * limit high enough to handle large FIFOs.
163 */
164 limit = 10*1024;
165 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
166 DELAY(delay);
167 if (limit == 0) {
168 /* printf("ns8250: transmitter appears stuck... "); */
169 return (EIO);
170 }
171 }
172
173 if (what & UART_DRAIN_RECEIVER) {
174 /*
175 * Pick an arbitrary high limit to avoid getting stuck in
176 * an infinite loop when the hardware is broken. Make the
177 * limit high enough to handle large FIFOs and integrated
178 * UARTs. The HP rx2600 for example has 3 UARTs on the
179 * management board that tend to get a lot of data send
180 * to it when the UART is first activated.
181 */
182 limit=10*4096;
183 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
184 (void)uart_getreg(bas, REG_DATA);
185 uart_barrier(bas);
186 DELAY(delay << 2);
187 }
188 if (limit == 0) {
189 /* printf("ns8250: receiver appears broken... "); */
190 return (EIO);
191 }
192 }
193
194 return (0);
195 }
196
197 /*
198 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
199 * drained. WARNING: this function clobbers the FIFO setting!
200 */
201 static void
ns8250_flush(struct uart_bas * bas,int what)202 ns8250_flush(struct uart_bas *bas, int what)
203 {
204 uint8_t fcr;
205
206 fcr = FCR_ENABLE;
207 #ifdef CPU_XBURST
208 fcr |= FCR_UART_ON;
209 #endif
210 if (what & UART_FLUSH_TRANSMITTER)
211 fcr |= FCR_XMT_RST;
212 if (what & UART_FLUSH_RECEIVER)
213 fcr |= FCR_RCV_RST;
214 uart_setreg(bas, REG_FCR, fcr);
215 uart_barrier(bas);
216 }
217
218 static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)219 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
220 int parity)
221 {
222 int divisor;
223 uint8_t lcr;
224
225 lcr = 0;
226 if (databits >= 8)
227 lcr |= LCR_8BITS;
228 else if (databits == 7)
229 lcr |= LCR_7BITS;
230 else if (databits == 6)
231 lcr |= LCR_6BITS;
232 else
233 lcr |= LCR_5BITS;
234 if (stopbits > 1)
235 lcr |= LCR_STOPB;
236 lcr |= parity << 3;
237
238 /* Set baudrate. */
239 if (baudrate > 0) {
240 divisor = ns8250_divisor(bas->rclk, baudrate);
241 if (divisor == 0)
242 return (EINVAL);
243 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
244 uart_barrier(bas);
245 uart_setreg(bas, REG_DLL, divisor & 0xff);
246 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
247 uart_barrier(bas);
248 }
249
250 /* Set LCR and clear DLAB. */
251 uart_setreg(bas, REG_LCR, lcr);
252 uart_barrier(bas);
253 return (0);
254 }
255
256 /*
257 * Low-level UART interface.
258 */
259 static int ns8250_probe(struct uart_bas *bas);
260 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
261 static void ns8250_term(struct uart_bas *bas);
262 static void ns8250_putc(struct uart_bas *bas, int);
263 static int ns8250_rxready(struct uart_bas *bas);
264 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
265
266 struct uart_ops uart_ns8250_ops = {
267 .probe = ns8250_probe,
268 .init = ns8250_init,
269 .term = ns8250_term,
270 .putc = ns8250_putc,
271 .rxready = ns8250_rxready,
272 .getc = ns8250_getc,
273 };
274
275 static int
ns8250_probe(struct uart_bas * bas)276 ns8250_probe(struct uart_bas *bas)
277 {
278 u_char val;
279
280 #ifdef CPU_XBURST
281 uart_setreg(bas, REG_FCR, FCR_UART_ON);
282 #endif
283
284 /* Check known 0 bits that don't depend on DLAB. */
285 val = uart_getreg(bas, REG_IIR);
286 if (val & 0x30)
287 return (ENXIO);
288 /*
289 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
290 * chip, but otherwise doesn't seem to have a function. In
291 * other words, uart(4) works regardless. Ignore that bit so
292 * the probe succeeds.
293 */
294 val = uart_getreg(bas, REG_MCR);
295 if (val & 0xa0)
296 return (ENXIO);
297
298 return (0);
299 }
300
301 static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)302 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
303 int parity)
304 {
305 u_char ier, val;
306
307 if (bas->rclk == 0)
308 bas->rclk = DEFAULT_RCLK;
309 ns8250_param(bas, baudrate, databits, stopbits, parity);
310
311 /* Disable all interrupt sources. */
312 /*
313 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
314 * UARTs split the receive time-out interrupt bit out separately as
315 * 0x10. This gets handled by ier_mask and ier_rxbits below.
316 */
317 ier = uart_getreg(bas, REG_IER) & 0xe0;
318 uart_setreg(bas, REG_IER, ier);
319 uart_barrier(bas);
320
321 /* Disable the FIFO (if present). */
322 val = 0;
323 #ifdef CPU_XBURST
324 val |= FCR_UART_ON;
325 #endif
326 uart_setreg(bas, REG_FCR, val);
327 uart_barrier(bas);
328
329 /* Set RTS & DTR. */
330 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
331 uart_barrier(bas);
332
333 ns8250_clrint(bas);
334 }
335
336 static void
ns8250_term(struct uart_bas * bas)337 ns8250_term(struct uart_bas *bas)
338 {
339
340 /* Clear RTS & DTR. */
341 uart_setreg(bas, REG_MCR, MCR_IE);
342 uart_barrier(bas);
343 }
344
345 static void
ns8250_putc(struct uart_bas * bas,int c)346 ns8250_putc(struct uart_bas *bas, int c)
347 {
348 int limit;
349
350 limit = 250000;
351 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
352 DELAY(4);
353 uart_setreg(bas, REG_DATA, c);
354 uart_barrier(bas);
355 }
356
357 static int
ns8250_rxready(struct uart_bas * bas)358 ns8250_rxready(struct uart_bas *bas)
359 {
360
361 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
362 }
363
364 static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)365 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
366 {
367 int c;
368
369 uart_lock(hwmtx);
370
371 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
372 uart_unlock(hwmtx);
373 DELAY(4);
374 uart_lock(hwmtx);
375 }
376
377 c = uart_getreg(bas, REG_DATA);
378
379 uart_unlock(hwmtx);
380
381 return (c);
382 }
383
384 static kobj_method_t ns8250_methods[] = {
385 KOBJMETHOD(uart_attach, ns8250_bus_attach),
386 KOBJMETHOD(uart_detach, ns8250_bus_detach),
387 KOBJMETHOD(uart_flush, ns8250_bus_flush),
388 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
389 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
390 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
391 KOBJMETHOD(uart_param, ns8250_bus_param),
392 KOBJMETHOD(uart_probe, ns8250_bus_probe),
393 KOBJMETHOD(uart_receive, ns8250_bus_receive),
394 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
395 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
396 KOBJMETHOD(uart_grab, ns8250_bus_grab),
397 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
398 { 0, 0 }
399 };
400
401 struct uart_class uart_ns8250_class = {
402 "ns8250",
403 ns8250_methods,
404 sizeof(struct ns8250_softc),
405 .uc_ops = &uart_ns8250_ops,
406 .uc_range = 8,
407 .uc_rclk = DEFAULT_RCLK,
408 .uc_rshift = 0
409 };
410
411 /*
412 * XXX -- refactor out ACPI and FDT ifdefs
413 */
414 #ifdef DEV_ACPI
415 static struct acpi_uart_compat_data acpi_compat_data[] = {
416 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
417 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
418 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
419 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
420 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
421 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
422 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
423 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
424 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
425 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
426 {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
427 };
428 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
429 #endif
430
431 #ifdef FDT
432 static struct ofw_compat_data compat_data[] = {
433 {"ns16550", (uintptr_t)&uart_ns8250_class},
434 {"ns16550a", (uintptr_t)&uart_ns8250_class},
435 {NULL, (uintptr_t)NULL},
436 };
437 UART_FDT_CLASS_AND_DEVICE(compat_data);
438 #endif
439
440 /* Use token-pasting to form SER_ and MSR_ named constants. */
441 #define SER(sig) SER_##sig
442 #define SERD(sig) SER_D##sig
443 #define MSR(sig) MSR_##sig
444 #define MSRD(sig) MSR_D##sig
445
446 /*
447 * Detect signal changes using software delta detection. The previous state of
448 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
449 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
450 * new state of both the signal and the delta bits.
451 */
452 #define SIGCHGSW(var, msr, sig) \
453 if ((msr) & MSR(sig)) { \
454 if ((var & SER(sig)) == 0) \
455 var |= SERD(sig) | SER(sig); \
456 } else { \
457 if ((var & SER(sig)) != 0) \
458 var = SERD(sig) | (var & ~SER(sig)); \
459 }
460
461 /*
462 * Detect signal changes using the hardware msr delta bits. This is currently
463 * used only when PPS timing information is being captured using the "narrow
464 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
465 * by time the interrupt handler is invoked. The hardware will latch the fact
466 * that it changed in the delta bits.
467 */
468 #define SIGCHGHW(var, msr, sig) \
469 if ((msr) & MSRD(sig)) { \
470 if (((msr) & MSR(sig)) != 0) \
471 var |= SERD(sig) | SER(sig); \
472 else \
473 var = SERD(sig) | (var & ~SER(sig)); \
474 }
475
476 int
ns8250_bus_attach(struct uart_softc * sc)477 ns8250_bus_attach(struct uart_softc *sc)
478 {
479 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
480 struct uart_bas *bas;
481 unsigned int ivar;
482 #ifdef FDT
483 phandle_t node;
484 pcell_t cell;
485 #endif
486
487 #ifdef FDT
488 /* Check whether uart has a broken txfifo. */
489 node = ofw_bus_get_node(sc->sc_dev);
490 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
491 broken_txfifo = cell ? 1 : 0;
492 #endif
493
494 bas = &sc->sc_bas;
495
496 ns8250->busy_detect = bas->busy_detect;
497 ns8250->mcr = uart_getreg(bas, REG_MCR);
498 ns8250->fcr = FCR_ENABLE;
499 #ifdef CPU_XBURST
500 ns8250->fcr |= FCR_UART_ON;
501 #endif
502 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
503 &ivar)) {
504 if (UART_FLAGS_FCR_RX_LOW(ivar))
505 ns8250->fcr |= FCR_RX_LOW;
506 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
507 ns8250->fcr |= FCR_RX_MEDL;
508 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
509 ns8250->fcr |= FCR_RX_HIGH;
510 else
511 ns8250->fcr |= FCR_RX_MEDH;
512 } else
513 ns8250->fcr |= FCR_RX_MEDH;
514
515 /* Get IER mask */
516 ivar = 0xf0;
517 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
518 &ivar);
519 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
520
521 /* Get IER RX interrupt bits */
522 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
523 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
524 &ivar);
525 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
526
527 uart_setreg(bas, REG_FCR, ns8250->fcr);
528 uart_barrier(bas);
529 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
530
531 if (ns8250->mcr & MCR_DTR)
532 sc->sc_hwsig |= SER_DTR;
533 if (ns8250->mcr & MCR_RTS)
534 sc->sc_hwsig |= SER_RTS;
535 ns8250_bus_getsig(sc);
536
537 ns8250_clrint(bas);
538 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
539 ns8250->ier |= ns8250->ier_rxbits;
540 uart_setreg(bas, REG_IER, ns8250->ier);
541 uart_barrier(bas);
542
543 /*
544 * Timing of the H/W access was changed with r253161 of uart_core.c
545 * It has been observed that an ITE IT8513E would signal a break
546 * condition with pretty much every character it received, unless
547 * it had enough time to settle between ns8250_bus_attach() and
548 * ns8250_bus_ipend() -- which it accidentally had before r253161.
549 * It's not understood why the UART chip behaves this way and it
550 * could very well be that the DELAY make the H/W work in the same
551 * accidental manner as before. More analysis is warranted, but
552 * at least now we fixed a known regression.
553 */
554 DELAY(200);
555 return (0);
556 }
557
558 int
ns8250_bus_detach(struct uart_softc * sc)559 ns8250_bus_detach(struct uart_softc *sc)
560 {
561 struct ns8250_softc *ns8250;
562 struct uart_bas *bas;
563 u_char ier;
564
565 ns8250 = (struct ns8250_softc *)sc;
566 bas = &sc->sc_bas;
567 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
568 uart_setreg(bas, REG_IER, ier);
569 uart_barrier(bas);
570 ns8250_clrint(bas);
571 return (0);
572 }
573
574 int
ns8250_bus_flush(struct uart_softc * sc,int what)575 ns8250_bus_flush(struct uart_softc *sc, int what)
576 {
577 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
578 struct uart_bas *bas;
579 int error;
580
581 bas = &sc->sc_bas;
582 uart_lock(sc->sc_hwmtx);
583 if (sc->sc_rxfifosz > 1) {
584 ns8250_flush(bas, what);
585 uart_setreg(bas, REG_FCR, ns8250->fcr);
586 uart_barrier(bas);
587 error = 0;
588 } else
589 error = ns8250_drain(bas, what);
590 uart_unlock(sc->sc_hwmtx);
591 return (error);
592 }
593
594 int
ns8250_bus_getsig(struct uart_softc * sc)595 ns8250_bus_getsig(struct uart_softc *sc)
596 {
597 uint32_t old, sig;
598 uint8_t msr;
599
600 /*
601 * The delta bits are reputed to be broken on some hardware, so use
602 * software delta detection by default. Use the hardware delta bits
603 * when capturing PPS pulses which are too narrow for software detection
604 * to see the edges. Hardware delta for RI doesn't work like the
605 * others, so always use software for it. Other threads may be changing
606 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
607 * update without other changes happening. Note that the SIGCHGxx()
608 * macros carefully preserve the delta bits when we have to loop several
609 * times and a signal transitions between iterations.
610 */
611 do {
612 old = sc->sc_hwsig;
613 sig = old;
614 uart_lock(sc->sc_hwmtx);
615 msr = uart_getreg(&sc->sc_bas, REG_MSR);
616 uart_unlock(sc->sc_hwmtx);
617 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
618 SIGCHGHW(sig, msr, DSR);
619 SIGCHGHW(sig, msr, CTS);
620 SIGCHGHW(sig, msr, DCD);
621 } else {
622 SIGCHGSW(sig, msr, DSR);
623 SIGCHGSW(sig, msr, CTS);
624 SIGCHGSW(sig, msr, DCD);
625 }
626 SIGCHGSW(sig, msr, RI);
627 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
628 return (sig);
629 }
630
631 int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)632 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
633 {
634 struct uart_bas *bas;
635 int baudrate, divisor, error;
636 uint8_t efr, lcr;
637
638 bas = &sc->sc_bas;
639 error = 0;
640 uart_lock(sc->sc_hwmtx);
641 switch (request) {
642 case UART_IOCTL_BREAK:
643 lcr = uart_getreg(bas, REG_LCR);
644 if (data)
645 lcr |= LCR_SBREAK;
646 else
647 lcr &= ~LCR_SBREAK;
648 uart_setreg(bas, REG_LCR, lcr);
649 uart_barrier(bas);
650 break;
651 case UART_IOCTL_IFLOW:
652 lcr = uart_getreg(bas, REG_LCR);
653 uart_barrier(bas);
654 uart_setreg(bas, REG_LCR, 0xbf);
655 uart_barrier(bas);
656 efr = uart_getreg(bas, REG_EFR);
657 if (data)
658 efr |= EFR_RTS;
659 else
660 efr &= ~EFR_RTS;
661 uart_setreg(bas, REG_EFR, efr);
662 uart_barrier(bas);
663 uart_setreg(bas, REG_LCR, lcr);
664 uart_barrier(bas);
665 break;
666 case UART_IOCTL_OFLOW:
667 lcr = uart_getreg(bas, REG_LCR);
668 uart_barrier(bas);
669 uart_setreg(bas, REG_LCR, 0xbf);
670 uart_barrier(bas);
671 efr = uart_getreg(bas, REG_EFR);
672 if (data)
673 efr |= EFR_CTS;
674 else
675 efr &= ~EFR_CTS;
676 uart_setreg(bas, REG_EFR, efr);
677 uart_barrier(bas);
678 uart_setreg(bas, REG_LCR, lcr);
679 uart_barrier(bas);
680 break;
681 case UART_IOCTL_BAUD:
682 lcr = uart_getreg(bas, REG_LCR);
683 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
684 uart_barrier(bas);
685 divisor = uart_getreg(bas, REG_DLL) |
686 (uart_getreg(bas, REG_DLH) << 8);
687 uart_barrier(bas);
688 uart_setreg(bas, REG_LCR, lcr);
689 uart_barrier(bas);
690 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
691 if (baudrate > 0)
692 *(int*)data = baudrate;
693 else
694 error = ENXIO;
695 break;
696 default:
697 error = EINVAL;
698 break;
699 }
700 uart_unlock(sc->sc_hwmtx);
701 return (error);
702 }
703
704 int
ns8250_bus_ipend(struct uart_softc * sc)705 ns8250_bus_ipend(struct uart_softc *sc)
706 {
707 struct uart_bas *bas;
708 struct ns8250_softc *ns8250;
709 int ipend;
710 uint8_t iir, lsr;
711
712 ns8250 = (struct ns8250_softc *)sc;
713 bas = &sc->sc_bas;
714 uart_lock(sc->sc_hwmtx);
715 iir = uart_getreg(bas, REG_IIR);
716
717 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
718 (void)uart_getreg(bas, DW_REG_USR);
719 uart_unlock(sc->sc_hwmtx);
720 return (0);
721 }
722 if (iir & IIR_NOPEND) {
723 uart_unlock(sc->sc_hwmtx);
724 return (0);
725 }
726 ipend = 0;
727 if (iir & IIR_RXRDY) {
728 lsr = uart_getreg(bas, REG_LSR);
729 if (lsr & LSR_OE)
730 ipend |= SER_INT_OVERRUN;
731 if (lsr & LSR_BI)
732 ipend |= SER_INT_BREAK;
733 if (lsr & LSR_RXRDY)
734 ipend |= SER_INT_RXREADY;
735 } else {
736 if (iir & IIR_TXRDY) {
737 ipend |= SER_INT_TXIDLE;
738 uart_setreg(bas, REG_IER, ns8250->ier);
739 uart_barrier(bas);
740 } else
741 ipend |= SER_INT_SIGCHG;
742 }
743 if (ipend == 0)
744 ns8250_clrint(bas);
745 uart_unlock(sc->sc_hwmtx);
746 return (ipend);
747 }
748
749 int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)750 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
751 int stopbits, int parity)
752 {
753 struct ns8250_softc *ns8250;
754 struct uart_bas *bas;
755 int error, limit;
756
757 ns8250 = (struct ns8250_softc*)sc;
758 bas = &sc->sc_bas;
759 uart_lock(sc->sc_hwmtx);
760 /*
761 * When using DW UART with BUSY detection it is necessary to wait
762 * until all serial transfers are finished before manipulating the
763 * line control. LCR will not be affected when UART is busy.
764 */
765 if (ns8250->busy_detect != 0) {
766 /*
767 * Pick an arbitrary high limit to avoid getting stuck in
768 * an infinite loop in case when the hardware is broken.
769 */
770 limit = 10 * 1024;
771 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
772 --limit)
773 DELAY(4);
774
775 if (limit <= 0) {
776 /* UART appears to be stuck */
777 uart_unlock(sc->sc_hwmtx);
778 return (EIO);
779 }
780 }
781
782 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
783 uart_unlock(sc->sc_hwmtx);
784 return (error);
785 }
786
787 int
ns8250_bus_probe(struct uart_softc * sc)788 ns8250_bus_probe(struct uart_softc *sc)
789 {
790 struct ns8250_softc *ns8250;
791 struct uart_bas *bas;
792 int count, delay, error, limit;
793 uint8_t lsr, mcr, ier;
794 uint8_t val;
795
796 ns8250 = (struct ns8250_softc *)sc;
797 bas = &sc->sc_bas;
798
799 error = ns8250_probe(bas);
800 if (error)
801 return (error);
802
803 mcr = MCR_IE;
804 if (sc->sc_sysdev == NULL) {
805 /* By using ns8250_init() we also set DTR and RTS. */
806 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
807 } else
808 mcr |= MCR_DTR | MCR_RTS;
809
810 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
811 if (error)
812 return (error);
813
814 /*
815 * Set loopback mode. This avoids having garbage on the wire and
816 * also allows us send and receive data. We set DTR and RTS to
817 * avoid the possibility that automatic flow-control prevents
818 * any data from being sent.
819 */
820 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
821 uart_barrier(bas);
822
823 /*
824 * Enable FIFOs. And check that the UART has them. If not, we're
825 * done. Since this is the first time we enable the FIFOs, we reset
826 * them.
827 */
828 val = FCR_ENABLE;
829 #ifdef CPU_XBURST
830 val |= FCR_UART_ON;
831 #endif
832 uart_setreg(bas, REG_FCR, val);
833 uart_barrier(bas);
834 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
835 /*
836 * NS16450 or INS8250. We don't bother to differentiate
837 * between them. They're too old to be interesting.
838 */
839 uart_setreg(bas, REG_MCR, mcr);
840 uart_barrier(bas);
841 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
842 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
843 return (0);
844 }
845
846 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
847 #ifdef CPU_XBURST
848 val |= FCR_UART_ON;
849 #endif
850 uart_setreg(bas, REG_FCR, val);
851 uart_barrier(bas);
852
853 count = 0;
854 delay = ns8250_delay(bas);
855
856 /* We have FIFOs. Drain the transmitter and receiver. */
857 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
858 if (error) {
859 uart_setreg(bas, REG_MCR, mcr);
860 val = 0;
861 #ifdef CPU_XBURST
862 val |= FCR_UART_ON;
863 #endif
864 uart_setreg(bas, REG_FCR, val);
865 uart_barrier(bas);
866 goto describe;
867 }
868
869 /*
870 * We should have a sufficiently clean "pipe" to determine the
871 * size of the FIFOs. We send as much characters as is reasonable
872 * and wait for the overflow bit in the LSR register to be
873 * asserted, counting the characters as we send them. Based on
874 * that count we know the FIFO size.
875 */
876 do {
877 uart_setreg(bas, REG_DATA, 0);
878 uart_barrier(bas);
879 count++;
880
881 limit = 30;
882 lsr = 0;
883 /*
884 * LSR bits are cleared upon read, so we must accumulate
885 * them to be able to test LSR_OE below.
886 */
887 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
888 --limit)
889 DELAY(delay);
890 if (limit == 0) {
891 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
892 uart_setreg(bas, REG_IER, ier);
893 uart_setreg(bas, REG_MCR, mcr);
894 val = 0;
895 #ifdef CPU_XBURST
896 val |= FCR_UART_ON;
897 #endif
898 uart_setreg(bas, REG_FCR, val);
899 uart_barrier(bas);
900 count = 0;
901 goto describe;
902 }
903 } while ((lsr & LSR_OE) == 0 && count < 260);
904 count--;
905
906 uart_setreg(bas, REG_MCR, mcr);
907
908 /* Reset FIFOs. */
909 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
910
911 describe:
912 if (count >= 14 && count <= 16) {
913 sc->sc_rxfifosz = 16;
914 device_set_desc(sc->sc_dev, "16550 or compatible");
915 } else if (count >= 28 && count <= 32) {
916 sc->sc_rxfifosz = 32;
917 device_set_desc(sc->sc_dev, "16650 or compatible");
918 } else if (count >= 56 && count <= 64) {
919 sc->sc_rxfifosz = 64;
920 device_set_desc(sc->sc_dev, "16750 or compatible");
921 } else if (count >= 112 && count <= 128) {
922 sc->sc_rxfifosz = 128;
923 device_set_desc(sc->sc_dev, "16950 or compatible");
924 } else if (count >= 224 && count <= 256) {
925 sc->sc_rxfifosz = 256;
926 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
927 } else {
928 sc->sc_rxfifosz = 16;
929 device_set_desc(sc->sc_dev,
930 "Non-standard ns8250 class UART with FIFOs");
931 }
932
933 /*
934 * Force the Tx FIFO size to 16 bytes for now. We don't program the
935 * Tx trigger. Also, we assume that all data has been sent when the
936 * interrupt happens.
937 */
938 sc->sc_txfifosz = 16;
939
940 #if 0
941 /*
942 * XXX there are some issues related to hardware flow control and
943 * it's likely that uart(4) is the cause. This basically needs more
944 * investigation, but we avoid using for hardware flow control
945 * until then.
946 */
947 /* 16650s or higher have automatic flow control. */
948 if (sc->sc_rxfifosz > 16) {
949 sc->sc_hwiflow = 1;
950 sc->sc_hwoflow = 1;
951 }
952 #endif
953
954 return (0);
955 }
956
957 int
ns8250_bus_receive(struct uart_softc * sc)958 ns8250_bus_receive(struct uart_softc *sc)
959 {
960 struct uart_bas *bas;
961 int xc;
962 uint8_t lsr;
963
964 bas = &sc->sc_bas;
965 uart_lock(sc->sc_hwmtx);
966 lsr = uart_getreg(bas, REG_LSR);
967 while (lsr & LSR_RXRDY) {
968 if (uart_rx_full(sc)) {
969 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
970 break;
971 }
972 xc = uart_getreg(bas, REG_DATA);
973 if (lsr & LSR_FE)
974 xc |= UART_STAT_FRAMERR;
975 if (lsr & LSR_PE)
976 xc |= UART_STAT_PARERR;
977 uart_rx_put(sc, xc);
978 lsr = uart_getreg(bas, REG_LSR);
979 }
980 /* Discard everything left in the Rx FIFO. */
981 while (lsr & LSR_RXRDY) {
982 (void)uart_getreg(bas, REG_DATA);
983 uart_barrier(bas);
984 lsr = uart_getreg(bas, REG_LSR);
985 }
986 uart_unlock(sc->sc_hwmtx);
987 return (0);
988 }
989
990 int
ns8250_bus_setsig(struct uart_softc * sc,int sig)991 ns8250_bus_setsig(struct uart_softc *sc, int sig)
992 {
993 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
994 struct uart_bas *bas;
995 uint32_t new, old;
996
997 bas = &sc->sc_bas;
998 do {
999 old = sc->sc_hwsig;
1000 new = old;
1001 if (sig & SER_DDTR) {
1002 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1003 }
1004 if (sig & SER_DRTS) {
1005 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1006 }
1007 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1008 uart_lock(sc->sc_hwmtx);
1009 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1010 if (new & SER_DTR)
1011 ns8250->mcr |= MCR_DTR;
1012 if (new & SER_RTS)
1013 ns8250->mcr |= MCR_RTS;
1014 uart_setreg(bas, REG_MCR, ns8250->mcr);
1015 uart_barrier(bas);
1016 uart_unlock(sc->sc_hwmtx);
1017 return (0);
1018 }
1019
1020 int
ns8250_bus_transmit(struct uart_softc * sc)1021 ns8250_bus_transmit(struct uart_softc *sc)
1022 {
1023 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1024 struct uart_bas *bas;
1025 int i;
1026
1027 bas = &sc->sc_bas;
1028 uart_lock(sc->sc_hwmtx);
1029 if (sc->sc_txdatasz > 1) {
1030 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
1031 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1032 } else {
1033 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1034 DELAY(4);
1035 }
1036 for (i = 0; i < sc->sc_txdatasz; i++) {
1037 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1038 uart_barrier(bas);
1039 }
1040 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
1041 uart_barrier(bas);
1042 if (broken_txfifo)
1043 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1044 else
1045 sc->sc_txbusy = 1;
1046 uart_unlock(sc->sc_hwmtx);
1047 if (broken_txfifo)
1048 uart_sched_softih(sc, SER_INT_TXIDLE);
1049 return (0);
1050 }
1051
1052 void
ns8250_bus_grab(struct uart_softc * sc)1053 ns8250_bus_grab(struct uart_softc *sc)
1054 {
1055 struct uart_bas *bas = &sc->sc_bas;
1056 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1057 u_char ier;
1058
1059 /*
1060 * turn off all interrupts to enter polling mode. Leave the
1061 * saved mask alone. We'll restore whatever it was in ungrab.
1062 * All pending interrupt signals are reset when IER is set to 0.
1063 */
1064 uart_lock(sc->sc_hwmtx);
1065 ier = uart_getreg(bas, REG_IER);
1066 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1067 uart_barrier(bas);
1068 uart_unlock(sc->sc_hwmtx);
1069 }
1070
1071 void
ns8250_bus_ungrab(struct uart_softc * sc)1072 ns8250_bus_ungrab(struct uart_softc *sc)
1073 {
1074 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1075 struct uart_bas *bas = &sc->sc_bas;
1076
1077 /*
1078 * Restore previous interrupt mask
1079 */
1080 uart_lock(sc->sc_hwmtx);
1081 uart_setreg(bas, REG_IER, ns8250->ier);
1082 uart_barrier(bas);
1083 uart_unlock(sc->sc_hwmtx);
1084 }
1085