1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Oleksandr Rybalko under sponsorship
8 * from the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include "opt_ddb.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/conf.h>
41 #include <sys/kdb.h>
42 #include <machine/bus.h>
43 #include <machine/fdt.h>
44
45 #include <dev/uart/uart.h>
46 #include <dev/uart/uart_cpu.h>
47 #include <dev/uart/uart_cpu_fdt.h>
48 #include <dev/uart/uart_bus.h>
49 #include <dev/uart/uart_dev_imx.h>
50 #include "uart_if.h"
51
52 #include <arm/freescale/imx/imx_ccmvar.h>
53
54 /*
55 * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes
56 * available to read or space for 24 more bytes to write. While 8 bytes of
57 * slack before over/underrun might seem excessive, the hardware can run at
58 * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS
59 * to get into the interrupt handler and service the fifo.
60 */
61 #define IMX_FIFOSZ 32
62 #define IMX_RXFIFO_LEVEL 24
63 #define IMX_TXFIFO_LEVEL 24
64
65 /*
66 * Low-level UART interface.
67 */
68 static int imx_uart_probe(struct uart_bas *bas);
69 static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
70 static void imx_uart_term(struct uart_bas *bas);
71 static void imx_uart_putc(struct uart_bas *bas, int);
72 static int imx_uart_rxready(struct uart_bas *bas);
73 static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
74
75 static struct uart_ops uart_imx_uart_ops = {
76 .probe = imx_uart_probe,
77 .init = imx_uart_init,
78 .term = imx_uart_term,
79 .putc = imx_uart_putc,
80 .rxready = imx_uart_rxready,
81 .getc = imx_uart_getc,
82 };
83
84 #if 0 /* Handy when debugging. */
85 static void
86 dumpregs(struct uart_bas *bas, const char * msg)
87 {
88
89 if (!bootverbose)
90 return;
91 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x "
92 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n",
93 msg, bas->bsh,
94 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),
95 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),
96 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));
97 }
98 #endif
99
100 static int
imx_uart_probe(struct uart_bas * bas)101 imx_uart_probe(struct uart_bas *bas)
102 {
103
104 return (0);
105 }
106
107 static u_int
imx_uart_getbaud(struct uart_bas * bas)108 imx_uart_getbaud(struct uart_bas *bas)
109 {
110 uint32_t rate, ubir, ubmr;
111 u_int baud, blo, bhi, i;
112 static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1};
113 static const u_int std_rates[] = {
114 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600
115 };
116
117 /*
118 * Get the baud rate the hardware is programmed for, then search the
119 * table of standard baud rates for a number that's within 3% of the
120 * actual rate the hardware is programmed for. It's more comforting to
121 * see that your console is running at 115200 than 114942. Note that
122 * here we cannot make a simplifying assumption that the predivider and
123 * numerator are 1 (like we do when setting the baud rate), because we
124 * don't know what u-boot might have set up.
125 */
126 i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >>
127 IMXUART_UFCR_RFDIV_SHIFT;
128 rate = imx_ccm_uart_hz() / predivs[i];
129 ubir = GETREG(bas, REG(UBIR)) + 1;
130 ubmr = GETREG(bas, REG(UBMR)) + 1;
131 baud = ((rate / 16 ) * ubir) / ubmr;
132
133 blo = (baud * 100) / 103;
134 bhi = (baud * 100) / 97;
135 for (i = 0; i < nitems(std_rates); i++) {
136 rate = std_rates[i];
137 if (rate >= blo && rate <= bhi) {
138 baud = rate;
139 break;
140 }
141 }
142
143 return (baud);
144 }
145
146 static void
imx_uart_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)147 imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
148 int stopbits, int parity)
149 {
150 uint32_t baseclk, reg;
151
152 /* Enable the device and the RX/TX channels. */
153 SET(bas, REG(UCR1), FLD(UCR1, UARTEN));
154 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));
155
156 if (databits == 7)
157 DIS(bas, UCR2, WS);
158 else
159 ENA(bas, UCR2, WS);
160
161 if (stopbits == 2)
162 ENA(bas, UCR2, STPB);
163 else
164 DIS(bas, UCR2, STPB);
165
166 switch (parity) {
167 case UART_PARITY_ODD:
168 DIS(bas, UCR2, PROE);
169 ENA(bas, UCR2, PREN);
170 break;
171 case UART_PARITY_EVEN:
172 ENA(bas, UCR2, PROE);
173 ENA(bas, UCR2, PREN);
174 break;
175 case UART_PARITY_MARK:
176 case UART_PARITY_SPACE:
177 /* FALLTHROUGH: Hardware doesn't support mark/space. */
178 case UART_PARITY_NONE:
179 default:
180 DIS(bas, UCR2, PREN);
181 break;
182 }
183
184 /*
185 * The hardware has an extremely flexible baud clock: it allows setting
186 * both the numerator and denominator of the divider, as well as a
187 * separate pre-divider. We simplify the problem of coming up with a
188 * workable pair of numbers by assuming a pre-divider and numerator of
189 * one because our base clock is so fast we can reach virtually any
190 * reasonable speed with a simple divisor. The numerator value actually
191 * includes the 16x over-sampling (so a value of 16 means divide by 1);
192 * the register value is the numerator-1, so we have a hard-coded 15.
193 * Note that a quirk of the hardware requires that both UBIR and UBMR be
194 * set back to back in order for the change to take effect.
195 */
196 if (baudrate > 0) {
197 baseclk = imx_ccm_uart_hz();
198 reg = GETREG(bas, REG(UFCR));
199 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;
200 SETREG(bas, REG(UFCR), reg);
201 SETREG(bas, REG(UBIR), 15);
202 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);
203 }
204
205 /*
206 * Program the tx lowater and rx hiwater levels at which fifo-service
207 * interrupts are signaled. The tx value is interpetted as "when there
208 * are only this many bytes remaining" (not "this many free").
209 */
210 reg = GETREG(bas, REG(UFCR));
211 reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK);
212 reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT;
213 reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT;
214 SETREG(bas, REG(UFCR), reg);
215 }
216
217 static void
imx_uart_term(struct uart_bas * bas)218 imx_uart_term(struct uart_bas *bas)
219 {
220
221 }
222
223 static void
imx_uart_putc(struct uart_bas * bas,int c)224 imx_uart_putc(struct uart_bas *bas, int c)
225 {
226
227 while (!(IS(bas, USR1, TRDY)))
228 ;
229 SETREG(bas, REG(UTXD), c);
230 }
231
232 static int
imx_uart_rxready(struct uart_bas * bas)233 imx_uart_rxready(struct uart_bas *bas)
234 {
235
236 return ((IS(bas, USR2, RDR)) ? 1 : 0);
237 }
238
239 static int
imx_uart_getc(struct uart_bas * bas,struct mtx * hwmtx)240 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
241 {
242 int c;
243
244 uart_lock(hwmtx);
245 while (!(IS(bas, USR2, RDR)))
246 ;
247
248 c = GETREG(bas, REG(URXD));
249 uart_unlock(hwmtx);
250 #if defined(KDB)
251 if (c & FLD(URXD, BRK)) {
252 if (kdb_break())
253 return (0);
254 }
255 #endif
256 return (c & 0xff);
257 }
258
259 /*
260 * High-level UART interface.
261 */
262 struct imx_uart_softc {
263 struct uart_softc base;
264 };
265
266 static int imx_uart_bus_attach(struct uart_softc *);
267 static int imx_uart_bus_detach(struct uart_softc *);
268 static int imx_uart_bus_flush(struct uart_softc *, int);
269 static int imx_uart_bus_getsig(struct uart_softc *);
270 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
271 static int imx_uart_bus_ipend(struct uart_softc *);
272 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
273 static int imx_uart_bus_probe(struct uart_softc *);
274 static int imx_uart_bus_receive(struct uart_softc *);
275 static int imx_uart_bus_setsig(struct uart_softc *, int);
276 static int imx_uart_bus_transmit(struct uart_softc *);
277 static void imx_uart_bus_grab(struct uart_softc *);
278 static void imx_uart_bus_ungrab(struct uart_softc *);
279
280 static kobj_method_t imx_uart_methods[] = {
281 KOBJMETHOD(uart_attach, imx_uart_bus_attach),
282 KOBJMETHOD(uart_detach, imx_uart_bus_detach),
283 KOBJMETHOD(uart_flush, imx_uart_bus_flush),
284 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
285 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
286 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
287 KOBJMETHOD(uart_param, imx_uart_bus_param),
288 KOBJMETHOD(uart_probe, imx_uart_bus_probe),
289 KOBJMETHOD(uart_receive, imx_uart_bus_receive),
290 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
291 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
292 KOBJMETHOD(uart_grab, imx_uart_bus_grab),
293 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab),
294 { 0, 0 }
295 };
296
297 static struct uart_class uart_imx_class = {
298 "imx",
299 imx_uart_methods,
300 sizeof(struct imx_uart_softc),
301 .uc_ops = &uart_imx_uart_ops,
302 .uc_range = 0x100,
303 .uc_rclk = 24000000, /* TODO: get value from CCM */
304 .uc_rshift = 0
305 };
306
307 static struct ofw_compat_data compat_data[] = {
308 {"fsl,imx6q-uart", (uintptr_t)&uart_imx_class},
309 {"fsl,imx53-uart", (uintptr_t)&uart_imx_class},
310 {"fsl,imx51-uart", (uintptr_t)&uart_imx_class},
311 {"fsl,imx31-uart", (uintptr_t)&uart_imx_class},
312 {"fsl,imx27-uart", (uintptr_t)&uart_imx_class},
313 {"fsl,imx25-uart", (uintptr_t)&uart_imx_class},
314 {"fsl,imx21-uart", (uintptr_t)&uart_imx_class},
315 {NULL, (uintptr_t)NULL},
316 };
317 UART_FDT_CLASS_AND_DEVICE(compat_data);
318
319 #define SIGCHG(c, i, s, d) \
320 if (c) { \
321 i |= (i & s) ? s : s | d; \
322 } else { \
323 i = (i & s) ? (i & ~s) | d : i; \
324 }
325
326 static int
imx_uart_bus_attach(struct uart_softc * sc)327 imx_uart_bus_attach(struct uart_softc *sc)
328 {
329 struct uart_bas *bas;
330 struct uart_devinfo *di;
331
332 bas = &sc->sc_bas;
333 if (sc->sc_sysdev != NULL) {
334 di = sc->sc_sysdev;
335 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
336 di->parity);
337 } else {
338 imx_uart_init(bas, 115200, 8, 1, 0);
339 }
340
341 (void)imx_uart_bus_getsig(sc);
342
343 /* Clear all pending interrupts. */
344 SETREG(bas, REG(USR1), 0xffff);
345 SETREG(bas, REG(USR2), 0xffff);
346
347 DIS(bas, UCR4, DREN);
348 ENA(bas, UCR1, RRDYEN);
349 DIS(bas, UCR1, IDEN);
350 DIS(bas, UCR3, RXDSEN);
351 ENA(bas, UCR2, ATEN);
352 DIS(bas, UCR1, TXMPTYEN);
353 DIS(bas, UCR1, TRDYEN);
354 DIS(bas, UCR4, TCEN);
355 DIS(bas, UCR4, OREN);
356 ENA(bas, UCR4, BKEN);
357 DIS(bas, UCR4, WKEN);
358 DIS(bas, UCR1, ADEN);
359 DIS(bas, UCR3, ACIEN);
360 DIS(bas, UCR2, ESCI);
361 DIS(bas, UCR4, ENIRI);
362 DIS(bas, UCR3, AIRINTEN);
363 DIS(bas, UCR3, AWAKEN);
364 DIS(bas, UCR3, FRAERREN);
365 DIS(bas, UCR3, PARERREN);
366 DIS(bas, UCR1, RTSDEN);
367 DIS(bas, UCR2, RTSEN);
368 DIS(bas, UCR3, DTREN);
369 DIS(bas, UCR3, RI);
370 DIS(bas, UCR3, DCD);
371 DIS(bas, UCR3, DTRDEN);
372 ENA(bas, UCR2, IRTS);
373 ENA(bas, UCR3, RXDMUXSEL);
374
375 return (0);
376 }
377
378 static int
imx_uart_bus_detach(struct uart_softc * sc)379 imx_uart_bus_detach(struct uart_softc *sc)
380 {
381
382 SETREG(&sc->sc_bas, REG(UCR4), 0);
383
384 return (0);
385 }
386
387 static int
imx_uart_bus_flush(struct uart_softc * sc,int what)388 imx_uart_bus_flush(struct uart_softc *sc, int what)
389 {
390
391 /* TODO */
392 return (0);
393 }
394
395 static int
imx_uart_bus_getsig(struct uart_softc * sc)396 imx_uart_bus_getsig(struct uart_softc *sc)
397 {
398 uint32_t new, old, sig;
399 uint8_t bes;
400
401 do {
402 old = sc->sc_hwsig;
403 sig = old;
404 uart_lock(sc->sc_hwmtx);
405 bes = GETREG(&sc->sc_bas, REG(USR2));
406 uart_unlock(sc->sc_hwmtx);
407 /* XXX: chip can show delta */
408 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
409 new = sig & ~SER_MASK_DELTA;
410 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
411
412 return (sig);
413 }
414
415 static int
imx_uart_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)416 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
417 {
418 struct uart_bas *bas;
419 int error;
420
421 bas = &sc->sc_bas;
422 error = 0;
423 uart_lock(sc->sc_hwmtx);
424 switch (request) {
425 case UART_IOCTL_BREAK:
426 /* TODO */
427 break;
428 case UART_IOCTL_BAUD:
429 *(u_int*)data = imx_uart_getbaud(bas);
430 break;
431 default:
432 error = EINVAL;
433 break;
434 }
435 uart_unlock(sc->sc_hwmtx);
436
437 return (error);
438 }
439
440 static int
imx_uart_bus_ipend(struct uart_softc * sc)441 imx_uart_bus_ipend(struct uart_softc *sc)
442 {
443 struct uart_bas *bas;
444 int ipend;
445 uint32_t usr1, usr2;
446 uint32_t ucr1, ucr2, ucr4;
447
448 bas = &sc->sc_bas;
449 ipend = 0;
450
451 uart_lock(sc->sc_hwmtx);
452
453 /* Read pending interrupts */
454 usr1 = GETREG(bas, REG(USR1));
455 usr2 = GETREG(bas, REG(USR2));
456 /* ACK interrupts */
457 SETREG(bas, REG(USR1), usr1);
458 SETREG(bas, REG(USR2), usr2);
459
460 ucr1 = GETREG(bas, REG(UCR1));
461 ucr2 = GETREG(bas, REG(UCR2));
462 ucr4 = GETREG(bas, REG(UCR4));
463
464 /* If we have reached tx low-water, we can tx some more now. */
465 if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) {
466 DIS(bas, UCR1, TRDYEN);
467 ipend |= SER_INT_TXIDLE;
468 }
469
470 /*
471 * If we have reached the rx high-water, or if there are bytes in the rx
472 * fifo and no new data has arrived for 8 character periods (aging
473 * timer), we have input data to process.
474 */
475 if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) ||
476 ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) {
477 DIS(bas, UCR1, RRDYEN);
478 DIS(bas, UCR2, ATEN);
479 ipend |= SER_INT_RXREADY;
480 }
481
482 /* A break can come in at any time, it never gets disabled. */
483 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
484 ipend |= SER_INT_BREAK;
485
486 uart_unlock(sc->sc_hwmtx);
487
488 return (ipend);
489 }
490
491 static int
imx_uart_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)492 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
493 int stopbits, int parity)
494 {
495
496 uart_lock(sc->sc_hwmtx);
497 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
498 uart_unlock(sc->sc_hwmtx);
499 return (0);
500 }
501
502 static int
imx_uart_bus_probe(struct uart_softc * sc)503 imx_uart_bus_probe(struct uart_softc *sc)
504 {
505 int error;
506
507 error = imx_uart_probe(&sc->sc_bas);
508 if (error)
509 return (error);
510
511 /*
512 * On input we can read up to the full fifo size at once. On output, we
513 * want to write only as much as the programmed tx low water level,
514 * because that's all we can be certain we have room for in the fifo
515 * when we get a tx-ready interrupt.
516 */
517 sc->sc_rxfifosz = IMX_FIFOSZ;
518 sc->sc_txfifosz = IMX_TXFIFO_LEVEL;
519
520 device_set_desc(sc->sc_dev, "Freescale i.MX UART");
521 return (0);
522 }
523
524 static int
imx_uart_bus_receive(struct uart_softc * sc)525 imx_uart_bus_receive(struct uart_softc *sc)
526 {
527 struct uart_bas *bas;
528 int xc, out;
529
530 bas = &sc->sc_bas;
531 uart_lock(sc->sc_hwmtx);
532
533 /*
534 * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL
535 * (the rx high-water level) is reached, but we set sc_rxfifosz to the
536 * full hardware fifo size, so we can safely process however much is
537 * there, not just the highwater size.
538 */
539 while (IS(bas, USR2, RDR)) {
540 if (uart_rx_full(sc)) {
541 /* No space left in input buffer */
542 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
543 break;
544 }
545 xc = GETREG(bas, REG(URXD));
546 out = xc & 0x000000ff;
547 if (xc & FLD(URXD, FRMERR))
548 out |= UART_STAT_FRAMERR;
549 if (xc & FLD(URXD, PRERR))
550 out |= UART_STAT_PARERR;
551 if (xc & FLD(URXD, OVRRUN))
552 out |= UART_STAT_OVERRUN;
553 if (xc & FLD(URXD, BRK))
554 out |= UART_STAT_BREAK;
555
556 uart_rx_put(sc, out);
557 }
558 ENA(bas, UCR1, RRDYEN);
559 ENA(bas, UCR2, ATEN);
560
561 uart_unlock(sc->sc_hwmtx);
562 return (0);
563 }
564
565 static int
imx_uart_bus_setsig(struct uart_softc * sc,int sig)566 imx_uart_bus_setsig(struct uart_softc *sc, int sig)
567 {
568
569 return (0);
570 }
571
572 static int
imx_uart_bus_transmit(struct uart_softc * sc)573 imx_uart_bus_transmit(struct uart_softc *sc)
574 {
575 struct uart_bas *bas = &sc->sc_bas;
576 int i;
577
578 bas = &sc->sc_bas;
579 uart_lock(sc->sc_hwmtx);
580
581 /*
582 * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes
583 * into the txbuf (because that's what sc_txfifosz is set to), and
584 * because we got the TRDY (low-water reached) interrupt we know at
585 * least that much space is available in the fifo.
586 */
587 for (i = 0; i < sc->sc_txdatasz; i++) {
588 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
589 }
590 sc->sc_txbusy = 1;
591 ENA(bas, UCR1, TRDYEN);
592
593 uart_unlock(sc->sc_hwmtx);
594
595 return (0);
596 }
597
598 static void
imx_uart_bus_grab(struct uart_softc * sc)599 imx_uart_bus_grab(struct uart_softc *sc)
600 {
601 struct uart_bas *bas = &sc->sc_bas;
602
603 bas = &sc->sc_bas;
604 uart_lock(sc->sc_hwmtx);
605 DIS(bas, UCR1, RRDYEN);
606 DIS(bas, UCR2, ATEN);
607 uart_unlock(sc->sc_hwmtx);
608 }
609
610 static void
imx_uart_bus_ungrab(struct uart_softc * sc)611 imx_uart_bus_ungrab(struct uart_softc *sc)
612 {
613 struct uart_bas *bas = &sc->sc_bas;
614
615 bas = &sc->sc_bas;
616 uart_lock(sc->sc_hwmtx);
617 ENA(bas, UCR1, RRDYEN);
618 ENA(bas, UCR2, ATEN);
619 uart_unlock(sc->sc_hwmtx);
620 }
621