1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 /*
33 * PCI "universal" communications card driver configuration data (used to
34 * match/attach the cards).
35 */
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/bus.h>
41 #include <sys/sysctl.h>
42
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <sys/rman.h>
46
47 #include <dev/ic/ns16550.h>
48
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51
52 #include <dev/puc/puc_bus.h>
53 #include <dev/puc/puc_cfg.h>
54 #include <dev/puc/puc_bfe.h>
55
56 static puc_config_f puc_config_advantech;
57 static puc_config_f puc_config_amc;
58 static puc_config_f puc_config_diva;
59 static puc_config_f puc_config_exar;
60 static puc_config_f puc_config_exar_pcie;
61 static puc_config_f puc_config_icbook;
62 static puc_config_f puc_config_moxa;
63 static puc_config_f puc_config_oxford_pci954;
64 static puc_config_f puc_config_oxford_pcie;
65 static puc_config_f puc_config_quatech;
66 static puc_config_f puc_config_syba;
67 static puc_config_f puc_config_siig;
68 static puc_config_f puc_config_sunix;
69 static puc_config_f puc_config_timedia;
70 static puc_config_f puc_config_titan;
71
72 const struct puc_cfg puc_pci_devices[] = {
73 { 0x0009, 0x7168, 0xffff, 0,
74 "Sunix SUN1889",
75 DEFAULT_RCLK * 8,
76 PUC_PORT_2S, 0x10, 0, 8,
77 },
78
79 { 0x103c, 0x1048, 0x103c, 0x1049,
80 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
81 DEFAULT_RCLK,
82 PUC_PORT_3S, 0x10, 0, -1,
83 .config_function = puc_config_diva
84 },
85
86 { 0x103c, 0x1048, 0x103c, 0x104a,
87 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
88 DEFAULT_RCLK,
89 PUC_PORT_2S, 0x10, 0, -1,
90 .config_function = puc_config_diva
91 },
92
93 { 0x103c, 0x1048, 0x103c, 0x104b,
94 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
95 DEFAULT_RCLK,
96 PUC_PORT_4S, 0x10, 0, -1,
97 .config_function = puc_config_diva
98 },
99
100 { 0x103c, 0x1048, 0x103c, 0x1223,
101 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
102 DEFAULT_RCLK,
103 PUC_PORT_3S, 0x10, 0, -1,
104 .config_function = puc_config_diva
105 },
106
107 { 0x103c, 0x1048, 0x103c, 0x1226,
108 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
109 DEFAULT_RCLK,
110 PUC_PORT_3S, 0x10, 0, -1,
111 .config_function = puc_config_diva
112 },
113
114 { 0x103c, 0x1048, 0x103c, 0x1282,
115 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
116 DEFAULT_RCLK,
117 PUC_PORT_3S, 0x10, 0, -1,
118 .config_function = puc_config_diva
119 },
120
121 { 0x10b5, 0x1076, 0x10b5, 0x1076,
122 "VScom PCI-800",
123 DEFAULT_RCLK * 8,
124 PUC_PORT_8S, 0x18, 0, 8,
125 },
126
127 { 0x10b5, 0x1077, 0x10b5, 0x1077,
128 "VScom PCI-400",
129 DEFAULT_RCLK * 8,
130 PUC_PORT_4S, 0x18, 0, 8,
131 },
132
133 { 0x10b5, 0x1103, 0x10b5, 0x1103,
134 "VScom PCI-200",
135 DEFAULT_RCLK * 8,
136 PUC_PORT_2S, 0x18, 4, 0,
137 },
138
139 /*
140 * Boca Research Turbo Serial 658 (8 serial port) card.
141 * Appears to be the same as Chase Research PLC PCI-FAST8
142 * and Perle PCI-FAST8 Multi-Port serial cards.
143 */
144 { 0x10b5, 0x9050, 0x12e0, 0x0021,
145 "Boca Research Turbo Serial 658",
146 DEFAULT_RCLK * 4,
147 PUC_PORT_8S, 0x18, 0, 8,
148 },
149
150 { 0x10b5, 0x9050, 0x12e0, 0x0031,
151 "Boca Research Turbo Serial 654",
152 DEFAULT_RCLK * 4,
153 PUC_PORT_4S, 0x18, 0, 8,
154 },
155
156 /*
157 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
158 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
159 * into the subsystem fields, and claims that it's a
160 * network/misc (0x02/0x80) device.
161 */
162 { 0x10b5, 0x9050, 0xd84d, 0x6808,
163 "Dolphin Peripherals 4035",
164 DEFAULT_RCLK,
165 PUC_PORT_2S, 0x18, 4, 0,
166 },
167
168 /*
169 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
170 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
171 * into the subsystem fields, and claims that it's a
172 * network/misc (0x02/0x80) device.
173 */
174 { 0x10b5, 0x9050, 0xd84d, 0x6810,
175 "Dolphin Peripherals 4014",
176 0,
177 PUC_PORT_2P, 0x20, 4, 0,
178 },
179
180 { 0x10e8, 0x818e, 0xffff, 0,
181 "Applied Micro Circuits 8 Port UART",
182 DEFAULT_RCLK,
183 PUC_PORT_8S, 0x14, -1, -1,
184 .config_function = puc_config_amc
185 },
186
187 /*
188 * The following members of the Digi International Neo series are
189 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
190 * Accordingly, the PCIe versions of these cards incorporate a PLX
191 * PCIe-PCI-bridge.
192 */
193
194 { 0x114f, 0x00b0, 0xffff, 0,
195 "Digi Neo PCI 4 Port",
196 DEFAULT_RCLK * 8,
197 PUC_PORT_4S, 0x10, 0, -1,
198 .config_function = puc_config_exar
199 },
200
201 { 0x114f, 0x00b1, 0xffff, 0,
202 "Digi Neo PCI 8 Port",
203 DEFAULT_RCLK * 8,
204 PUC_PORT_8S, 0x10, 0, -1,
205 .config_function = puc_config_exar
206 },
207
208 { 0x114f, 0x00f0, 0xffff, 0,
209 "Digi Neo PCIe 8 Port",
210 DEFAULT_RCLK * 8,
211 PUC_PORT_8S, 0x10, 0, -1,
212 .config_function = puc_config_exar
213 },
214
215 { 0x114f, 0x00f1, 0xffff, 0,
216 "Digi Neo PCIe 4 Port",
217 DEFAULT_RCLK * 8,
218 PUC_PORT_4S, 0x10, 0, -1,
219 .config_function = puc_config_exar
220 },
221
222 { 0x114f, 0x00f2, 0xffff, 0,
223 "Digi Neo PCIe 4 Port RJ45",
224 DEFAULT_RCLK * 8,
225 PUC_PORT_4S, 0x10, 0, -1,
226 .config_function = puc_config_exar
227 },
228
229 { 0x114f, 0x00f3, 0xffff, 0,
230 "Digi Neo PCIe 8 Port RJ45",
231 DEFAULT_RCLK * 8,
232 PUC_PORT_8S, 0x10, 0, -1,
233 .config_function = puc_config_exar
234 },
235
236 { 0x11fe, 0x8010, 0xffff, 0,
237 "Comtrol RocketPort 550/8 RJ11 part A",
238 DEFAULT_RCLK * 4,
239 PUC_PORT_4S, 0x10, 0, 8,
240 },
241
242 { 0x11fe, 0x8011, 0xffff, 0,
243 "Comtrol RocketPort 550/8 RJ11 part B",
244 DEFAULT_RCLK * 4,
245 PUC_PORT_4S, 0x10, 0, 8,
246 },
247
248 { 0x11fe, 0x8012, 0xffff, 0,
249 "Comtrol RocketPort 550/8 Octa part A",
250 DEFAULT_RCLK * 4,
251 PUC_PORT_4S, 0x10, 0, 8,
252 },
253
254 { 0x11fe, 0x8013, 0xffff, 0,
255 "Comtrol RocketPort 550/8 Octa part B",
256 DEFAULT_RCLK * 4,
257 PUC_PORT_4S, 0x10, 0, 8,
258 },
259
260 { 0x11fe, 0x8014, 0xffff, 0,
261 "Comtrol RocketPort 550/4 RJ45",
262 DEFAULT_RCLK * 4,
263 PUC_PORT_4S, 0x10, 0, 8,
264 },
265
266 { 0x11fe, 0x8015, 0xffff, 0,
267 "Comtrol RocketPort 550/Quad",
268 DEFAULT_RCLK * 4,
269 PUC_PORT_4S, 0x10, 0, 8,
270 },
271
272 { 0x11fe, 0x8016, 0xffff, 0,
273 "Comtrol RocketPort 550/16 part A",
274 DEFAULT_RCLK * 4,
275 PUC_PORT_4S, 0x10, 0, 8,
276 },
277
278 { 0x11fe, 0x8017, 0xffff, 0,
279 "Comtrol RocketPort 550/16 part B",
280 DEFAULT_RCLK * 4,
281 PUC_PORT_12S, 0x10, 0, 8,
282 },
283
284 { 0x11fe, 0x8018, 0xffff, 0,
285 "Comtrol RocketPort 550/8 part A",
286 DEFAULT_RCLK * 4,
287 PUC_PORT_4S, 0x10, 0, 8,
288 },
289
290 { 0x11fe, 0x8019, 0xffff, 0,
291 "Comtrol RocketPort 550/8 part B",
292 DEFAULT_RCLK * 4,
293 PUC_PORT_4S, 0x10, 0, 8,
294 },
295
296 /*
297 * IBM SurePOS 300 Series (481033H) serial ports
298 * Details can be found on the IBM RSS websites
299 */
300
301 { 0x1014, 0x0297, 0xffff, 0,
302 "IBM SurePOS 300 Series (481033H) serial ports",
303 DEFAULT_RCLK,
304 PUC_PORT_4S, 0x10, 4, 0
305 },
306
307 /*
308 * SIIG Boards.
309 *
310 * SIIG provides documentation for their boards at:
311 * <URL:http://www.siig.com/downloads.asp>
312 */
313
314 { 0x131f, 0x1010, 0xffff, 0,
315 "SIIG Cyber I/O PCI 16C550 (10x family)",
316 DEFAULT_RCLK,
317 PUC_PORT_1S1P, 0x18, 4, 0,
318 },
319
320 { 0x131f, 0x1011, 0xffff, 0,
321 "SIIG Cyber I/O PCI 16C650 (10x family)",
322 DEFAULT_RCLK,
323 PUC_PORT_1S1P, 0x18, 4, 0,
324 },
325
326 { 0x131f, 0x1012, 0xffff, 0,
327 "SIIG Cyber I/O PCI 16C850 (10x family)",
328 DEFAULT_RCLK,
329 PUC_PORT_1S1P, 0x18, 4, 0,
330 },
331
332 { 0x131f, 0x1021, 0xffff, 0,
333 "SIIG Cyber Parallel Dual PCI (10x family)",
334 0,
335 PUC_PORT_2P, 0x18, 8, 0,
336 },
337
338 { 0x131f, 0x1030, 0xffff, 0,
339 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
340 DEFAULT_RCLK,
341 PUC_PORT_2S, 0x18, 4, 0,
342 },
343
344 { 0x131f, 0x1031, 0xffff, 0,
345 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
346 DEFAULT_RCLK,
347 PUC_PORT_2S, 0x18, 4, 0,
348 },
349
350 { 0x131f, 0x1032, 0xffff, 0,
351 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
352 DEFAULT_RCLK,
353 PUC_PORT_2S, 0x18, 4, 0,
354 },
355
356 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
357 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
358 DEFAULT_RCLK,
359 PUC_PORT_2S1P, 0x18, 4, 0,
360 },
361
362 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
363 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
364 DEFAULT_RCLK,
365 PUC_PORT_2S1P, 0x18, 4, 0,
366 },
367
368 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
369 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
370 DEFAULT_RCLK,
371 PUC_PORT_2S1P, 0x18, 4, 0,
372 },
373
374 { 0x131f, 0x1050, 0xffff, 0,
375 "SIIG Cyber 4S PCI 16C550 (10x family)",
376 DEFAULT_RCLK,
377 PUC_PORT_4S, 0x18, 4, 0,
378 },
379
380 { 0x131f, 0x1051, 0xffff, 0,
381 "SIIG Cyber 4S PCI 16C650 (10x family)",
382 DEFAULT_RCLK,
383 PUC_PORT_4S, 0x18, 4, 0,
384 },
385
386 { 0x131f, 0x1052, 0xffff, 0,
387 "SIIG Cyber 4S PCI 16C850 (10x family)",
388 DEFAULT_RCLK,
389 PUC_PORT_4S, 0x18, 4, 0,
390 },
391
392 { 0x131f, 0x2010, 0xffff, 0,
393 "SIIG Cyber I/O PCI 16C550 (20x family)",
394 DEFAULT_RCLK,
395 PUC_PORT_1S1P, 0x10, 4, 0,
396 },
397
398 { 0x131f, 0x2011, 0xffff, 0,
399 "SIIG Cyber I/O PCI 16C650 (20x family)",
400 DEFAULT_RCLK,
401 PUC_PORT_1S1P, 0x10, 4, 0,
402 },
403
404 { 0x131f, 0x2012, 0xffff, 0,
405 "SIIG Cyber I/O PCI 16C850 (20x family)",
406 DEFAULT_RCLK,
407 PUC_PORT_1S1P, 0x10, 4, 0,
408 },
409
410 { 0x131f, 0x2021, 0xffff, 0,
411 "SIIG Cyber Parallel Dual PCI (20x family)",
412 0,
413 PUC_PORT_2P, 0x10, 8, 0,
414 },
415
416 { 0x131f, 0x2030, 0xffff, 0,
417 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
418 DEFAULT_RCLK,
419 PUC_PORT_2S, 0x10, 4, 0,
420 },
421
422 { 0x131f, 0x2031, 0xffff, 0,
423 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
424 DEFAULT_RCLK,
425 PUC_PORT_2S, 0x10, 4, 0,
426 },
427
428 { 0x131f, 0x2032, 0xffff, 0,
429 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
430 DEFAULT_RCLK,
431 PUC_PORT_2S, 0x10, 4, 0,
432 },
433
434 { 0x131f, 0x2040, 0xffff, 0,
435 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
436 DEFAULT_RCLK,
437 PUC_PORT_1S2P, 0x10, -1, 0,
438 .config_function = puc_config_siig
439 },
440
441 { 0x131f, 0x2041, 0xffff, 0,
442 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
443 DEFAULT_RCLK,
444 PUC_PORT_1S2P, 0x10, -1, 0,
445 .config_function = puc_config_siig
446 },
447
448 { 0x131f, 0x2042, 0xffff, 0,
449 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
450 DEFAULT_RCLK,
451 PUC_PORT_1S2P, 0x10, -1, 0,
452 .config_function = puc_config_siig
453 },
454
455 { 0x131f, 0x2050, 0xffff, 0,
456 "SIIG Cyber 4S PCI 16C550 (20x family)",
457 DEFAULT_RCLK,
458 PUC_PORT_4S, 0x10, 4, 0,
459 },
460
461 { 0x131f, 0x2051, 0xffff, 0,
462 "SIIG Cyber 4S PCI 16C650 (20x family)",
463 DEFAULT_RCLK,
464 PUC_PORT_4S, 0x10, 4, 0,
465 },
466
467 { 0x131f, 0x2052, 0xffff, 0,
468 "SIIG Cyber 4S PCI 16C850 (20x family)",
469 DEFAULT_RCLK,
470 PUC_PORT_4S, 0x10, 4, 0,
471 },
472
473 { 0x131f, 0x2060, 0xffff, 0,
474 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
475 DEFAULT_RCLK,
476 PUC_PORT_2S1P, 0x10, 4, 0,
477 },
478
479 { 0x131f, 0x2061, 0xffff, 0,
480 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
481 DEFAULT_RCLK,
482 PUC_PORT_2S1P, 0x10, 4, 0,
483 },
484
485 { 0x131f, 0x2062, 0xffff, 0,
486 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
487 DEFAULT_RCLK,
488 PUC_PORT_2S1P, 0x10, 4, 0,
489 },
490
491 { 0x131f, 0x2081, 0xffff, 0,
492 "SIIG PS8000 8S PCI 16C650 (20x family)",
493 DEFAULT_RCLK,
494 PUC_PORT_8S, 0x10, -1, -1,
495 .config_function = puc_config_siig
496 },
497
498 { 0x135c, 0x0010, 0xffff, 0,
499 "Quatech QSC-100",
500 -3, /* max 8x clock rate */
501 PUC_PORT_4S, 0x14, 0, 8,
502 .config_function = puc_config_quatech
503 },
504
505 { 0x135c, 0x0020, 0xffff, 0,
506 "Quatech DSC-100",
507 -1, /* max 2x clock rate */
508 PUC_PORT_2S, 0x14, 0, 8,
509 .config_function = puc_config_quatech
510 },
511
512 { 0x135c, 0x0030, 0xffff, 0,
513 "Quatech DSC-200/300",
514 -1, /* max 2x clock rate */
515 PUC_PORT_2S, 0x14, 0, 8,
516 .config_function = puc_config_quatech
517 },
518
519 { 0x135c, 0x0040, 0xffff, 0,
520 "Quatech QSC-200/300",
521 -3, /* max 8x clock rate */
522 PUC_PORT_4S, 0x14, 0, 8,
523 .config_function = puc_config_quatech
524 },
525
526 { 0x135c, 0x0050, 0xffff, 0,
527 "Quatech ESC-100D",
528 -3, /* max 8x clock rate */
529 PUC_PORT_8S, 0x14, 0, 8,
530 .config_function = puc_config_quatech
531 },
532
533 { 0x135c, 0x0060, 0xffff, 0,
534 "Quatech ESC-100M",
535 -3, /* max 8x clock rate */
536 PUC_PORT_8S, 0x14, 0, 8,
537 .config_function = puc_config_quatech
538 },
539
540 { 0x135c, 0x0170, 0xffff, 0,
541 "Quatech QSCLP-100",
542 -1, /* max 2x clock rate */
543 PUC_PORT_4S, 0x18, 0, 8,
544 .config_function = puc_config_quatech
545 },
546
547 { 0x135c, 0x0180, 0xffff, 0,
548 "Quatech DSCLP-100",
549 -1, /* max 3x clock rate */
550 PUC_PORT_2S, 0x18, 0, 8,
551 .config_function = puc_config_quatech
552 },
553
554 { 0x135c, 0x01b0, 0xffff, 0,
555 "Quatech DSCLP-200/300",
556 -1, /* max 2x clock rate */
557 PUC_PORT_2S, 0x18, 0, 8,
558 .config_function = puc_config_quatech
559 },
560
561 { 0x135c, 0x01e0, 0xffff, 0,
562 "Quatech ESCLP-100",
563 -3, /* max 8x clock rate */
564 PUC_PORT_8S, 0x10, 0, 8,
565 .config_function = puc_config_quatech
566 },
567
568 { 0x1393, 0x1024, 0xffff, 0,
569 "Moxa Technologies, Smartio CP-102E/PCIe",
570 DEFAULT_RCLK * 8,
571 PUC_PORT_2S, 0x14, 0, -1,
572 .config_function = puc_config_moxa
573 },
574
575 { 0x1393, 0x1025, 0xffff, 0,
576 "Moxa Technologies, Smartio CP-102EL/PCIe",
577 DEFAULT_RCLK * 8,
578 PUC_PORT_2S, 0x14, 0, -1,
579 .config_function = puc_config_moxa
580 },
581
582 { 0x1393, 0x1040, 0xffff, 0,
583 "Moxa Technologies, Smartio C104H/PCI",
584 DEFAULT_RCLK * 8,
585 PUC_PORT_4S, 0x18, 0, 8,
586 },
587
588 { 0x1393, 0x1041, 0xffff, 0,
589 "Moxa Technologies, Smartio CP-104UL/PCI",
590 DEFAULT_RCLK * 8,
591 PUC_PORT_4S, 0x18, 0, 8,
592 },
593
594 { 0x1393, 0x1042, 0xffff, 0,
595 "Moxa Technologies, Smartio CP-104JU/PCI",
596 DEFAULT_RCLK * 8,
597 PUC_PORT_4S, 0x18, 0, 8,
598 },
599
600 { 0x1393, 0x1043, 0xffff, 0,
601 "Moxa Technologies, Smartio CP-104EL/PCIe",
602 DEFAULT_RCLK * 8,
603 PUC_PORT_4S, 0x18, 0, 8,
604 },
605
606 { 0x1393, 0x1045, 0xffff, 0,
607 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
608 DEFAULT_RCLK * 8,
609 PUC_PORT_4S, 0x14, 0, -1,
610 .config_function = puc_config_moxa
611 },
612
613 { 0x1393, 0x1120, 0xffff, 0,
614 "Moxa Technologies, CP-112UL",
615 DEFAULT_RCLK * 8,
616 PUC_PORT_2S, 0x18, 0, 8,
617 },
618
619 { 0x1393, 0x1141, 0xffff, 0,
620 "Moxa Technologies, Industio CP-114",
621 DEFAULT_RCLK * 8,
622 PUC_PORT_4S, 0x18, 0, 8,
623 },
624
625 { 0x1393, 0x1144, 0xffff, 0,
626 "Moxa Technologies, Smartio CP-114EL/PCIe",
627 DEFAULT_RCLK * 8,
628 PUC_PORT_4S, 0x14, 0, -1,
629 .config_function = puc_config_moxa
630 },
631
632 { 0x1393, 0x1182, 0xffff, 0,
633 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
634 DEFAULT_RCLK * 8,
635 PUC_PORT_8S, 0x14, 0, -1,
636 .config_function = puc_config_moxa
637 },
638
639 { 0x1393, 0x1680, 0xffff, 0,
640 "Moxa Technologies, C168H/PCI",
641 DEFAULT_RCLK * 8,
642 PUC_PORT_8S, 0x18, 0, 8,
643 },
644
645 { 0x1393, 0x1681, 0xffff, 0,
646 "Moxa Technologies, C168U/PCI",
647 DEFAULT_RCLK * 8,
648 PUC_PORT_8S, 0x18, 0, 8,
649 },
650
651 { 0x1393, 0x1682, 0xffff, 0,
652 "Moxa Technologies, CP-168EL/PCIe",
653 DEFAULT_RCLK * 8,
654 PUC_PORT_8S, 0x18, 0, 8,
655 },
656
657 { 0x1393, 0x1683, 0xffff, 0,
658 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
659 DEFAULT_RCLK * 8,
660 PUC_PORT_8S, 0x14, 0, -1,
661 .config_function = puc_config_moxa
662 },
663
664 { 0x13a8, 0x0152, 0xffff, 0,
665 "Exar XR17C/D152",
666 DEFAULT_RCLK * 8,
667 PUC_PORT_2S, 0x10, 0, -1,
668 .config_function = puc_config_exar
669 },
670
671 { 0x13a8, 0x0154, 0xffff, 0,
672 "Exar XR17C154",
673 DEFAULT_RCLK * 8,
674 PUC_PORT_4S, 0x10, 0, -1,
675 .config_function = puc_config_exar
676 },
677
678 { 0x13a8, 0x0158, 0xffff, 0,
679 "Exar XR17C158",
680 DEFAULT_RCLK * 8,
681 PUC_PORT_8S, 0x10, 0, -1,
682 .config_function = puc_config_exar
683 },
684
685 { 0x13a8, 0x0258, 0xffff, 0,
686 "Exar XR17V258IV",
687 DEFAULT_RCLK * 8,
688 PUC_PORT_8S, 0x10, 0, -1,
689 .config_function = puc_config_exar
690 },
691
692 { 0x13a8, 0x0352, 0xffff, 0,
693 "Exar XR17V352",
694 125000000,
695 PUC_PORT_2S, 0x10, 0, -1,
696 .config_function = puc_config_exar_pcie
697 },
698
699 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
700 { 0x13a8, 0x0358, 0xffff, 0,
701 "Exar XR17V358",
702 125000000,
703 PUC_PORT_8S, 0x10, 0, -1,
704 .config_function = puc_config_exar_pcie
705 },
706
707 /*
708 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
709 * Semiconductor OXuPCI954. Note these boards have a hardware bug in
710 * that they drive the RS-422/485 transmitters after power-on until a
711 * driver initalizes the UARTs.
712 */
713 { 0x13fe, 0x1600, 0x1602, 0x0002,
714 "Advantech PCI-1602 Rev. A",
715 DEFAULT_RCLK * 8,
716 PUC_PORT_2S, 0x10, 0, 8,
717 .config_function = puc_config_advantech
718 },
719
720 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
721 { 0x13fe, 0xa102, 0x13fe, 0xa102,
722 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
723 DEFAULT_RCLK * 8,
724 PUC_PORT_2S, 0x10, 4, 0,
725 .config_function = puc_config_advantech
726 },
727
728 { 0x1407, 0x0100, 0xffff, 0,
729 "Lava Computers Dual Serial",
730 DEFAULT_RCLK,
731 PUC_PORT_2S, 0x10, 4, 0,
732 },
733
734 { 0x1407, 0x0101, 0xffff, 0,
735 "Lava Computers Quatro A",
736 DEFAULT_RCLK,
737 PUC_PORT_2S, 0x10, 4, 0,
738 },
739
740 { 0x1407, 0x0102, 0xffff, 0,
741 "Lava Computers Quatro B",
742 DEFAULT_RCLK,
743 PUC_PORT_2S, 0x10, 4, 0,
744 },
745
746 { 0x1407, 0x0120, 0xffff, 0,
747 "Lava Computers Quattro-PCI A",
748 DEFAULT_RCLK,
749 PUC_PORT_2S, 0x10, 4, 0,
750 },
751
752 { 0x1407, 0x0121, 0xffff, 0,
753 "Lava Computers Quattro-PCI B",
754 DEFAULT_RCLK,
755 PUC_PORT_2S, 0x10, 4, 0,
756 },
757
758 { 0x1407, 0x0180, 0xffff, 0,
759 "Lava Computers Octo A",
760 DEFAULT_RCLK,
761 PUC_PORT_4S, 0x10, 4, 0,
762 },
763
764 { 0x1407, 0x0181, 0xffff, 0,
765 "Lava Computers Octo B",
766 DEFAULT_RCLK,
767 PUC_PORT_4S, 0x10, 4, 0,
768 },
769
770 { 0x1409, 0x7268, 0xffff, 0,
771 "Sunix SUN1888",
772 0,
773 PUC_PORT_2P, 0x10, 0, 8,
774 },
775
776 { 0x1409, 0x7168, 0xffff, 0,
777 NULL,
778 DEFAULT_RCLK * 8,
779 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
780 .config_function = puc_config_timedia
781 },
782
783 /*
784 * Boards with an Oxford Semiconductor chip.
785 *
786 * Oxford Semiconductor provides documentation for their chip at:
787 * <URL:http://www.plxtech.com/products/uart/>
788 *
789 * As sold by Kouwell <URL:http://www.kouwell.com/>.
790 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
791 */
792 {
793 0x1415, 0x9501, 0x10fc, 0xc070,
794 "I-O DATA RSA-PCI2/R",
795 DEFAULT_RCLK * 8,
796 PUC_PORT_2S, 0x10, 0, 8,
797 },
798
799 { 0x1415, 0x9501, 0x131f, 0x2050,
800 "SIIG Cyber 4 PCI 16550",
801 DEFAULT_RCLK * 10,
802 PUC_PORT_4S, 0x10, 0, 8,
803 },
804
805 { 0x1415, 0x9501, 0x131f, 0x2051,
806 "SIIG Cyber 4S PCI 16C650 (20x family)",
807 DEFAULT_RCLK * 10,
808 PUC_PORT_4S, 0x10, 0, 8,
809 },
810
811 { 0x1415, 0x9501, 0x131f, 0x2052,
812 "SIIG Quartet Serial 850",
813 DEFAULT_RCLK * 10,
814 PUC_PORT_4S, 0x10, 0, 8,
815 },
816
817 { 0x1415, 0x9501, 0x14db, 0x2150,
818 "Kuroutoshikou SERIAL4P-LPPCI2",
819 DEFAULT_RCLK * 10,
820 PUC_PORT_4S, 0x10, 0, 8,
821 },
822
823 { 0x1415, 0x9501, 0xffff, 0,
824 "Oxford Semiconductor OX16PCI954 UARTs",
825 0,
826 PUC_PORT_4S, 0x10, 0, 8,
827 .config_function = puc_config_oxford_pci954
828 },
829
830 { 0x1415, 0x950a, 0x131f, 0x2030,
831 "SIIG Cyber 2S PCIe",
832 DEFAULT_RCLK * 10,
833 PUC_PORT_2S, 0x10, 0, 8,
834 },
835
836 { 0x1415, 0x950a, 0x131f, 0x2032,
837 "SIIG Cyber Serial Dual PCI 16C850",
838 DEFAULT_RCLK * 10,
839 PUC_PORT_4S, 0x10, 0, 8,
840 },
841
842 { 0x1415, 0x950a, 0x131f, 0x2061,
843 "SIIG Cyber 2SP1 PCIe",
844 DEFAULT_RCLK * 10,
845 PUC_PORT_2S, 0x10, 0, 8,
846 },
847
848 { 0x1415, 0x950a, 0xffff, 0,
849 "Oxford Semiconductor OX16PCI954 UARTs",
850 DEFAULT_RCLK,
851 PUC_PORT_4S, 0x10, 0, 8,
852 },
853
854 { 0x1415, 0x9511, 0xffff, 0,
855 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
856 DEFAULT_RCLK,
857 PUC_PORT_4S, 0x10, 0, 8,
858 },
859
860 { 0x1415, 0x9521, 0xffff, 0,
861 "Oxford Semiconductor OX16PCI952 UARTs",
862 DEFAULT_RCLK,
863 PUC_PORT_2S, 0x10, 4, 0,
864 },
865
866 { 0x1415, 0x9538, 0xffff, 0,
867 "Oxford Semiconductor OX16PCI958 UARTs",
868 DEFAULT_RCLK,
869 PUC_PORT_8S, 0x18, 0, 8,
870 },
871
872 /*
873 * Perle boards use Oxford Semiconductor chips, but they store the
874 * Oxford Semiconductor device ID as a subvendor device ID and use
875 * their own device IDs.
876 */
877
878 { 0x155f, 0x0331, 0xffff, 0,
879 "Perle Ultraport4 Express",
880 DEFAULT_RCLK * 8,
881 PUC_PORT_4S, 0x10, 0, 8,
882 },
883
884 { 0x155f, 0xB012, 0xffff, 0,
885 "Perle Speed2 LE",
886 DEFAULT_RCLK * 8,
887 PUC_PORT_2S, 0x10, 0, 8,
888 },
889
890 { 0x155f, 0xB022, 0xffff, 0,
891 "Perle Speed2 LE",
892 DEFAULT_RCLK * 8,
893 PUC_PORT_2S, 0x10, 0, 8,
894 },
895
896 { 0x155f, 0xB004, 0xffff, 0,
897 "Perle Speed4 LE",
898 DEFAULT_RCLK * 8,
899 PUC_PORT_4S, 0x10, 0, 8,
900 },
901
902 { 0x155f, 0xB008, 0xffff, 0,
903 "Perle Speed8 LE",
904 DEFAULT_RCLK * 8,
905 PUC_PORT_8S, 0x10, 0, 8,
906 },
907
908
909 /*
910 * Oxford Semiconductor PCI Express Expresso family
911 *
912 * Found in many 'native' PCI Express serial boards such as:
913 *
914 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
915 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
916 *
917 * Lindy 51189 (4 port)
918 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
919 *
920 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
921 * <URL:http://www.startech.com>
922 */
923
924 { 0x1415, 0xc11b, 0xffff, 0,
925 "Oxford Semiconductor OXPCIe952 1S1P",
926 DEFAULT_RCLK * 0x22,
927 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
928 .config_function = puc_config_oxford_pcie
929 },
930
931 { 0x1415, 0xc138, 0xffff, 0,
932 "Oxford Semiconductor OXPCIe952 UARTs",
933 DEFAULT_RCLK * 0x22,
934 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
935 .config_function = puc_config_oxford_pcie
936 },
937
938 { 0x1415, 0xc158, 0xffff, 0,
939 "Oxford Semiconductor OXPCIe952 UARTs",
940 DEFAULT_RCLK * 0x22,
941 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
942 .config_function = puc_config_oxford_pcie
943 },
944
945 { 0x1415, 0xc15d, 0xffff, 0,
946 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
947 DEFAULT_RCLK * 0x22,
948 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
949 .config_function = puc_config_oxford_pcie
950 },
951
952 { 0x1415, 0xc208, 0xffff, 0,
953 "Oxford Semiconductor OXPCIe954 UARTs",
954 DEFAULT_RCLK * 0x22,
955 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
956 .config_function = puc_config_oxford_pcie
957 },
958
959 { 0x1415, 0xc20d, 0xffff, 0,
960 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
961 DEFAULT_RCLK * 0x22,
962 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
963 .config_function = puc_config_oxford_pcie
964 },
965
966 { 0x1415, 0xc308, 0xffff, 0,
967 "Oxford Semiconductor OXPCIe958 UARTs",
968 DEFAULT_RCLK * 0x22,
969 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
970 .config_function = puc_config_oxford_pcie
971 },
972
973 { 0x1415, 0xc30d, 0xffff, 0,
974 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
975 DEFAULT_RCLK * 0x22,
976 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
977 .config_function = puc_config_oxford_pcie
978 },
979
980 { 0x14d2, 0x8010, 0xffff, 0,
981 "VScom PCI-100L",
982 DEFAULT_RCLK * 8,
983 PUC_PORT_1S, 0x14, 0, 0,
984 },
985
986 { 0x14d2, 0x8020, 0xffff, 0,
987 "VScom PCI-200L",
988 DEFAULT_RCLK * 8,
989 PUC_PORT_2S, 0x14, 4, 0,
990 },
991
992 { 0x14d2, 0x8028, 0xffff, 0,
993 "VScom 200Li",
994 DEFAULT_RCLK,
995 PUC_PORT_2S, 0x20, 0, 8,
996 },
997
998 /*
999 * VScom (Titan?) PCI-800L. More modern variant of the
1000 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1001 * two of them obviously implemented as macro cells in
1002 * the ASIC. This causes the weird port access pattern
1003 * below, where two of the IO port ranges each access
1004 * one of the ASIC UARTs, and a block of IO addresses
1005 * access the external UARTs.
1006 */
1007 { 0x14d2, 0x8080, 0xffff, 0,
1008 "Titan VScom PCI-800L",
1009 DEFAULT_RCLK * 8,
1010 PUC_PORT_8S, 0x14, -1, -1,
1011 .config_function = puc_config_titan
1012 },
1013
1014 /*
1015 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1016 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1017 * device ID 3 and PCI device 1 device ID 4.
1018 */
1019 { 0x14d2, 0xa003, 0xffff, 0,
1020 "Titan PCI-800H",
1021 DEFAULT_RCLK * 8,
1022 PUC_PORT_4S, 0x10, 0, 8,
1023 },
1024
1025 { 0x14d2, 0xa004, 0xffff, 0,
1026 "Titan PCI-800H",
1027 DEFAULT_RCLK * 8,
1028 PUC_PORT_4S, 0x10, 0, 8,
1029 },
1030
1031 { 0x14d2, 0xa005, 0xffff, 0,
1032 "Titan PCI-200H",
1033 DEFAULT_RCLK * 8,
1034 PUC_PORT_2S, 0x10, 0, 8,
1035 },
1036
1037 { 0x14d2, 0xe020, 0xffff, 0,
1038 "Titan VScom PCI-200HV2",
1039 DEFAULT_RCLK * 8,
1040 PUC_PORT_2S, 0x10, 4, 0,
1041 },
1042
1043 { 0x14d2, 0xa007, 0xffff, 0,
1044 "Titan VScom PCIex-800H",
1045 DEFAULT_RCLK * 8,
1046 PUC_PORT_4S, 0x10, 0, 8,
1047 },
1048
1049 { 0x14d2, 0xa008, 0xffff, 0,
1050 "Titan VScom PCIex-800H",
1051 DEFAULT_RCLK * 8,
1052 PUC_PORT_4S, 0x10, 0, 8,
1053 },
1054
1055 { 0x14db, 0x2130, 0xffff, 0,
1056 "Avlab Technology, PCI IO 2S",
1057 DEFAULT_RCLK,
1058 PUC_PORT_2S, 0x10, 4, 0,
1059 },
1060
1061 { 0x14db, 0x2150, 0xffff, 0,
1062 "Avlab Low Profile PCI 4 Serial",
1063 DEFAULT_RCLK,
1064 PUC_PORT_4S, 0x10, 4, 0,
1065 },
1066
1067 { 0x14db, 0x2152, 0xffff, 0,
1068 "Avlab Low Profile PCI 4 Serial",
1069 DEFAULT_RCLK,
1070 PUC_PORT_4S, 0x10, 4, 0,
1071 },
1072
1073 { 0x1592, 0x0781, 0xffff, 0,
1074 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1075 DEFAULT_RCLK,
1076 PUC_PORT_4S1P, 0x10, 0, -1,
1077 .config_function = puc_config_syba
1078 },
1079
1080 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1081 "Sunix SER5xxxx 2-port serial",
1082 DEFAULT_RCLK * 8,
1083 PUC_PORT_2S, 0x10, 0, 8,
1084 },
1085
1086 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1087 "Sunix SER5xxxx 4-port serial",
1088 DEFAULT_RCLK * 8,
1089 PUC_PORT_4S, 0x10, 0, 8,
1090 },
1091
1092 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1093 "Sunix SER5xxxx 8-port serial",
1094 DEFAULT_RCLK * 8,
1095 PUC_PORT_8S, -1, -1, -1,
1096 .config_function = puc_config_sunix
1097 },
1098
1099 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1100 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1101 DEFAULT_RCLK * 8,
1102 PUC_PORT_1S1P, -1, -1, -1,
1103 .config_function = puc_config_sunix
1104 },
1105
1106 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1107 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1108 DEFAULT_RCLK * 8,
1109 PUC_PORT_2S1P, -1, -1, -1,
1110 .config_function = puc_config_sunix
1111 },
1112
1113 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1114 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1115 DEFAULT_RCLK * 8,
1116 PUC_PORT_4S1P, -1, -1, -1,
1117 .config_function = puc_config_sunix
1118 },
1119
1120 { 0x5372, 0x6872, 0xffff, 0,
1121 "Feasso PCI FPP-02 2S1P",
1122 DEFAULT_RCLK,
1123 PUC_PORT_2S1P, 0x10, 4, 0,
1124 },
1125
1126 { 0x5372, 0x6873, 0xffff, 0,
1127 "Sun 1040 PCI Quad Serial",
1128 DEFAULT_RCLK,
1129 PUC_PORT_4S, 0x10, 4, 0,
1130 },
1131
1132 { 0x6666, 0x0001, 0xffff, 0,
1133 "Decision Computer Inc, PCCOM 4-port serial",
1134 DEFAULT_RCLK,
1135 PUC_PORT_4S, 0x1c, 0, 8,
1136 },
1137
1138 { 0x6666, 0x0002, 0xffff, 0,
1139 "Decision Computer Inc, PCCOM 8-port serial",
1140 DEFAULT_RCLK,
1141 PUC_PORT_8S, 0x1c, 0, 8,
1142 },
1143
1144 { 0x6666, 0x0004, 0xffff, 0,
1145 "PCCOM dual port RS232/422/485",
1146 DEFAULT_RCLK,
1147 PUC_PORT_2S, 0x1c, 0, 8,
1148 },
1149
1150 { 0x9710, 0x9815, 0xffff, 0,
1151 "NetMos NM9815 Dual 1284 Printer port",
1152 0,
1153 PUC_PORT_2P, 0x10, 8, 0,
1154 },
1155
1156 /*
1157 * This is more specific than the generic NM9835 entry, and is placed
1158 * here to _prevent_ puc(4) from claiming this single port card.
1159 *
1160 * uart(4) will claim this device.
1161 */
1162 { 0x9710, 0x9835, 0x1000, 1,
1163 "NetMos NM9835 based 1-port serial",
1164 DEFAULT_RCLK,
1165 PUC_PORT_1S, 0x10, 4, 0,
1166 },
1167
1168 { 0x9710, 0x9835, 0x1000, 2,
1169 "NetMos NM9835 based 2-port serial",
1170 DEFAULT_RCLK,
1171 PUC_PORT_2S, 0x10, 4, 0,
1172 },
1173
1174 { 0x9710, 0x9835, 0xffff, 0,
1175 "NetMos NM9835 Dual UART and 1284 Printer port",
1176 DEFAULT_RCLK,
1177 PUC_PORT_2S1P, 0x10, 4, 0,
1178 },
1179
1180 { 0x9710, 0x9845, 0x1000, 0x0006,
1181 "NetMos NM9845 6 Port UART",
1182 DEFAULT_RCLK,
1183 PUC_PORT_6S, 0x10, 4, 0,
1184 },
1185
1186 { 0x9710, 0x9845, 0xffff, 0,
1187 "NetMos NM9845 Quad UART and 1284 Printer port",
1188 DEFAULT_RCLK,
1189 PUC_PORT_4S1P, 0x10, 4, 0,
1190 },
1191
1192 { 0x9710, 0x9865, 0xa000, 0x3002,
1193 "NetMos NM9865 Dual UART",
1194 DEFAULT_RCLK,
1195 PUC_PORT_2S, 0x10, 4, 0,
1196 },
1197
1198 { 0x9710, 0x9865, 0xa000, 0x3003,
1199 "NetMos NM9865 Triple UART",
1200 DEFAULT_RCLK,
1201 PUC_PORT_3S, 0x10, 4, 0,
1202 },
1203
1204 { 0x9710, 0x9865, 0xa000, 0x3004,
1205 "NetMos NM9865 Quad UART",
1206 DEFAULT_RCLK,
1207 PUC_PORT_4S, 0x10, 4, 0,
1208 },
1209
1210 { 0x9710, 0x9865, 0xa000, 0x3011,
1211 "NetMos NM9865 Single UART and 1284 Printer port",
1212 DEFAULT_RCLK,
1213 PUC_PORT_1S1P, 0x10, 4, 0,
1214 },
1215
1216 { 0x9710, 0x9865, 0xa000, 0x3012,
1217 "NetMos NM9865 Dual UART and 1284 Printer port",
1218 DEFAULT_RCLK,
1219 PUC_PORT_2S1P, 0x10, 4, 0,
1220 },
1221
1222 { 0x9710, 0x9865, 0xa000, 0x3020,
1223 "NetMos NM9865 Dual 1284 Printer port",
1224 DEFAULT_RCLK,
1225 PUC_PORT_2P, 0x10, 4, 0,
1226 },
1227
1228 { 0xb00c, 0x021c, 0xffff, 0,
1229 "IC Book Labs Gunboat x4 Lite",
1230 DEFAULT_RCLK,
1231 PUC_PORT_4S, 0x10, 0, 8,
1232 .config_function = puc_config_icbook
1233 },
1234
1235 { 0xb00c, 0x031c, 0xffff, 0,
1236 "IC Book Labs Gunboat x4 Pro",
1237 DEFAULT_RCLK,
1238 PUC_PORT_4S, 0x10, 0, 8,
1239 .config_function = puc_config_icbook
1240 },
1241
1242 { 0xb00c, 0x041c, 0xffff, 0,
1243 "IC Book Labs Ironclad x8 Lite",
1244 DEFAULT_RCLK,
1245 PUC_PORT_8S, 0x10, 0, 8,
1246 .config_function = puc_config_icbook
1247 },
1248
1249 { 0xb00c, 0x051c, 0xffff, 0,
1250 "IC Book Labs Ironclad x8 Pro",
1251 DEFAULT_RCLK,
1252 PUC_PORT_8S, 0x10, 0, 8,
1253 .config_function = puc_config_icbook
1254 },
1255
1256 { 0xb00c, 0x081c, 0xffff, 0,
1257 "IC Book Labs Dreadnought x16 Pro",
1258 DEFAULT_RCLK * 8,
1259 PUC_PORT_16S, 0x10, 0, 8,
1260 .config_function = puc_config_icbook
1261 },
1262
1263 { 0xb00c, 0x091c, 0xffff, 0,
1264 "IC Book Labs Dreadnought x16 Lite",
1265 DEFAULT_RCLK,
1266 PUC_PORT_16S, 0x10, 0, 8,
1267 .config_function = puc_config_icbook
1268 },
1269
1270 { 0xb00c, 0x0a1c, 0xffff, 0,
1271 "IC Book Labs Gunboat x2 Low Profile",
1272 DEFAULT_RCLK,
1273 PUC_PORT_2S, 0x10, 0, 8,
1274 },
1275
1276 { 0xb00c, 0x0b1c, 0xffff, 0,
1277 "IC Book Labs Gunboat x4 Low Profile",
1278 DEFAULT_RCLK,
1279 PUC_PORT_4S, 0x10, 0, 8,
1280 .config_function = puc_config_icbook
1281 },
1282
1283 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1284 };
1285
1286 static int
puc_config_advantech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res __unused)1287 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1288 intptr_t *res __unused)
1289 {
1290 const struct puc_cfg *cfg;
1291 struct resource *cres;
1292 struct puc_bar *bar;
1293 device_t cdev, dev;
1294 bus_size_t off;
1295 int base, crtype, fixed, high, i, oxpcie;
1296 uint8_t acr, func, mask;
1297
1298 if (cmd != PUC_CFG_SETUP)
1299 return (ENXIO);
1300
1301 base = fixed = oxpcie = 0;
1302 crtype = SYS_RES_IOPORT;
1303 acr = mask = 0x0;
1304 func = high = 1;
1305 off = 0x60;
1306
1307 cfg = sc->sc_cfg;
1308 switch (cfg->subvendor) {
1309 case 0x13fe:
1310 switch (cfg->device) {
1311 case 0xa102:
1312 high = 0;
1313 break;
1314 default:
1315 break;
1316 }
1317 default:
1318 break;
1319 }
1320 if (fixed == 1)
1321 goto setup;
1322
1323 dev = sc->sc_dev;
1324 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1325 pci_get_slot(dev), func);
1326 if (cdev == NULL) {
1327 device_printf(dev, "could not find config function\n");
1328 return (ENXIO);
1329 }
1330
1331 i = PCIR_BAR(0);
1332 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE);
1333 if (cres == NULL) {
1334 device_printf(dev, "could not allocate config resource\n");
1335 return (ENXIO);
1336 }
1337
1338 if (oxpcie == 0) {
1339 mask = bus_read_1(cres, off);
1340 if (pci_get_function(dev) == 1)
1341 base = 4;
1342 }
1343
1344 setup:
1345 for (i = 0; i < sc->sc_nports; ++i) {
1346 device_printf(dev, "port %d: ", i);
1347 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);
1348 if (bar == NULL) {
1349 printf("could not get BAR\n");
1350 continue;
1351 }
1352
1353 if (fixed == 0) {
1354 if ((mask & (1 << (base + i))) == 0) {
1355 acr = 0;
1356 printf("RS-232\n");
1357 } else {
1358 acr = (high == 1 ? 0x18 : 0x10);
1359 printf("RS-422/RS-485, active-%s auto-DTR\n",
1360 high == 1 ? "high" : "low");
1361 }
1362 }
1363
1364 bus_write_1(bar->b_res, REG_SPR, REG_ACR);
1365 bus_write_1(bar->b_res, REG_ICR, acr);
1366 }
1367
1368 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres);
1369 return (0);
1370 }
1371
1372 static int
puc_config_amc(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1373 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port,
1374 intptr_t *res)
1375 {
1376
1377 switch (cmd) {
1378 case PUC_CFG_GET_OFS:
1379 *res = 8 * (port & 1);
1380 return (0);
1381 case PUC_CFG_GET_RID:
1382 *res = 0x14 + (port >> 1) * 4;
1383 return (0);
1384 default:
1385 break;
1386 }
1387 return (ENXIO);
1388 }
1389
1390 static int
puc_config_diva(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1391 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1392 intptr_t *res)
1393 {
1394 const struct puc_cfg *cfg = sc->sc_cfg;
1395
1396 if (cmd == PUC_CFG_GET_OFS) {
1397 if (cfg->subdevice == 0x1282) /* Everest SP */
1398 port <<= 1;
1399 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1400 port = (port == 3) ? 4 : port;
1401 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1402 return (0);
1403 }
1404 return (ENXIO);
1405 }
1406
1407 static int
puc_config_exar(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1408 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1409 int port, intptr_t *res)
1410 {
1411
1412 if (cmd == PUC_CFG_GET_OFS) {
1413 *res = port * 0x200;
1414 return (0);
1415 }
1416 return (ENXIO);
1417 }
1418
1419 static int
puc_config_exar_pcie(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1420 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1421 int port, intptr_t *res)
1422 {
1423
1424 if (cmd == PUC_CFG_GET_OFS) {
1425 *res = port * 0x400;
1426 return (0);
1427 }
1428 return (ENXIO);
1429 }
1430
1431 static int
puc_config_icbook(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1432 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1433 int port __unused, intptr_t *res)
1434 {
1435
1436 if (cmd == PUC_CFG_GET_ILR) {
1437 *res = PUC_ILR_DIGI;
1438 return (0);
1439 }
1440 return (ENXIO);
1441 }
1442
1443 static int
puc_config_moxa(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1444 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1445 intptr_t *res)
1446 {
1447 const struct puc_cfg *cfg = sc->sc_cfg;
1448
1449 if (cmd == PUC_CFG_GET_OFS) {
1450 if (port == 3 && (cfg->device == 0x1045 ||
1451 cfg->device == 0x1144))
1452 port = 7;
1453 *res = port * 0x200;
1454
1455 return 0;
1456 }
1457 return (ENXIO);
1458 }
1459
1460 static int
puc_config_quatech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1461 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1462 int port __unused, intptr_t *res)
1463 {
1464 const struct puc_cfg *cfg = sc->sc_cfg;
1465 struct puc_bar *bar;
1466 uint8_t v0, v1;
1467
1468 switch (cmd) {
1469 case PUC_CFG_SETUP:
1470 /*
1471 * Check if the scratchpad register is enabled or if the
1472 * interrupt status and options registers are active.
1473 */
1474 bar = puc_get_bar(sc, cfg->rid);
1475 if (bar == NULL)
1476 return (ENXIO);
1477 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);
1478 bus_write_1(bar->b_res, REG_SPR, 0);
1479 v0 = bus_read_1(bar->b_res, REG_SPR);
1480 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);
1481 v1 = bus_read_1(bar->b_res, REG_SPR);
1482 bus_write_1(bar->b_res, REG_LCR, 0);
1483 sc->sc_cfg_data = (v0 << 8) | v1;
1484 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1485 /*
1486 * The SPR register echoed the two values written
1487 * by us. This means that the SPAD jumper is set.
1488 */
1489 device_printf(sc->sc_dev, "warning: extra features "
1490 "not usable -- SPAD compatibility enabled\n");
1491 return (0);
1492 }
1493 if (v0 != 0) {
1494 /*
1495 * The first value doesn't match. This can only mean
1496 * that the SPAD jumper is not set and that a non-
1497 * standard fixed clock multiplier jumper is set.
1498 */
1499 if (bootverbose)
1500 device_printf(sc->sc_dev, "fixed clock rate "
1501 "multiplier of %d\n", 1 << v0);
1502 if (v0 < -cfg->clock)
1503 device_printf(sc->sc_dev, "warning: "
1504 "suboptimal fixed clock rate multiplier "
1505 "setting\n");
1506 return (0);
1507 }
1508 /*
1509 * The first value matched, but the second didn't. We know
1510 * that the SPAD jumper is not set. We also know that the
1511 * clock rate multiplier is software controlled *and* that
1512 * we just programmed it to the maximum allowed.
1513 */
1514 if (bootverbose)
1515 device_printf(sc->sc_dev, "clock rate multiplier of "
1516 "%d selected\n", 1 << -cfg->clock);
1517 return (0);
1518 case PUC_CFG_GET_CLOCK:
1519 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1520 v1 = sc->sc_cfg_data & 0xff;
1521 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1522 /*
1523 * XXX With the SPAD jumper applied, there's no
1524 * easy way of knowing if there's also a clock
1525 * rate multiplier jumper installed. Let's hope
1526 * not ...
1527 */
1528 *res = DEFAULT_RCLK;
1529 } else if (v0 == 0) {
1530 /*
1531 * No clock rate multiplier jumper installed,
1532 * so we programmed the board with the maximum
1533 * multiplier allowed as given to us in the
1534 * clock field of the config record (negated).
1535 */
1536 *res = DEFAULT_RCLK << -cfg->clock;
1537 } else
1538 *res = DEFAULT_RCLK << v0;
1539 return (0);
1540 case PUC_CFG_GET_ILR:
1541 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1542 v1 = sc->sc_cfg_data & 0xff;
1543 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ?
1544 PUC_ILR_NONE : PUC_ILR_QUATECH;
1545 return (0);
1546 default:
1547 break;
1548 }
1549 return (ENXIO);
1550 }
1551
1552 static int
puc_config_syba(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1553 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1554 intptr_t *res)
1555 {
1556 static int base[] = { 0x251, 0x3f0, 0 };
1557 const struct puc_cfg *cfg = sc->sc_cfg;
1558 struct puc_bar *bar;
1559 int efir, idx, ofs;
1560 uint8_t v;
1561
1562 switch (cmd) {
1563 case PUC_CFG_SETUP:
1564 bar = puc_get_bar(sc, cfg->rid);
1565 if (bar == NULL)
1566 return (ENXIO);
1567
1568 /* configure both W83877TFs */
1569 bus_write_1(bar->b_res, 0x250, 0x89);
1570 bus_write_1(bar->b_res, 0x3f0, 0x87);
1571 bus_write_1(bar->b_res, 0x3f0, 0x87);
1572 idx = 0;
1573 while (base[idx] != 0) {
1574 efir = base[idx];
1575 bus_write_1(bar->b_res, efir, 0x09);
1576 v = bus_read_1(bar->b_res, efir + 1);
1577 if ((v & 0x0f) != 0x0c)
1578 return (ENXIO);
1579 bus_write_1(bar->b_res, efir, 0x16);
1580 v = bus_read_1(bar->b_res, efir + 1);
1581 bus_write_1(bar->b_res, efir, 0x16);
1582 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1583 bus_write_1(bar->b_res, efir, 0x16);
1584 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1585 ofs = base[idx] & 0x300;
1586 bus_write_1(bar->b_res, efir, 0x23);
1587 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1588 bus_write_1(bar->b_res, efir, 0x24);
1589 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1590 bus_write_1(bar->b_res, efir, 0x25);
1591 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1592 bus_write_1(bar->b_res, efir, 0x17);
1593 bus_write_1(bar->b_res, efir + 1, 0x03);
1594 bus_write_1(bar->b_res, efir, 0x28);
1595 bus_write_1(bar->b_res, efir + 1, 0x43);
1596 idx++;
1597 }
1598 bus_write_1(bar->b_res, 0x250, 0xaa);
1599 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1600 return (0);
1601 case PUC_CFG_GET_OFS:
1602 switch (port) {
1603 case 0:
1604 *res = 0x2f8;
1605 return (0);
1606 case 1:
1607 *res = 0x2e8;
1608 return (0);
1609 case 2:
1610 *res = 0x3f8;
1611 return (0);
1612 case 3:
1613 *res = 0x3e8;
1614 return (0);
1615 case 4:
1616 *res = 0x278;
1617 return (0);
1618 }
1619 break;
1620 default:
1621 break;
1622 }
1623 return (ENXIO);
1624 }
1625
1626 static int
puc_config_siig(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1627 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1628 intptr_t *res)
1629 {
1630 const struct puc_cfg *cfg = sc->sc_cfg;
1631
1632 switch (cmd) {
1633 case PUC_CFG_GET_OFS:
1634 if (cfg->ports == PUC_PORT_8S) {
1635 *res = (port > 4) ? 8 * (port - 4) : 0;
1636 return (0);
1637 }
1638 break;
1639 case PUC_CFG_GET_RID:
1640 if (cfg->ports == PUC_PORT_8S) {
1641 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1642 return (0);
1643 }
1644 if (cfg->ports == PUC_PORT_2S1P) {
1645 switch (port) {
1646 case 0: *res = 0x10; return (0);
1647 case 1: *res = 0x14; return (0);
1648 case 2: *res = 0x1c; return (0);
1649 }
1650 }
1651 break;
1652 default:
1653 break;
1654 }
1655 return (ENXIO);
1656 }
1657
1658 static int
puc_config_timedia(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1659 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1660 intptr_t *res)
1661 {
1662 static const uint16_t dual[] = {
1663 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1664 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1665 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1666 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1667 0xD079, 0
1668 };
1669 static const uint16_t quad[] = {
1670 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1671 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1672 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1673 0xB157, 0
1674 };
1675 static const uint16_t octa[] = {
1676 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1677 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1678 };
1679 static const struct {
1680 int ports;
1681 const uint16_t *ids;
1682 } subdevs[] = {
1683 { 2, dual },
1684 { 4, quad },
1685 { 8, octa },
1686 { 0, NULL }
1687 };
1688 static char desc[64];
1689 int dev, id;
1690 uint16_t subdev;
1691
1692 switch (cmd) {
1693 case PUC_CFG_GET_CLOCK:
1694 if (port < 2)
1695 *res = DEFAULT_RCLK * 8;
1696 else
1697 *res = DEFAULT_RCLK;
1698 return (0);
1699 case PUC_CFG_GET_DESC:
1700 snprintf(desc, sizeof(desc),
1701 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1702 *res = (intptr_t)desc;
1703 return (0);
1704 case PUC_CFG_GET_NPORTS:
1705 subdev = pci_get_subdevice(sc->sc_dev);
1706 dev = 0;
1707 while (subdevs[dev].ports != 0) {
1708 id = 0;
1709 while (subdevs[dev].ids[id] != 0) {
1710 if (subdev == subdevs[dev].ids[id]) {
1711 sc->sc_cfg_data = subdevs[dev].ports;
1712 *res = sc->sc_cfg_data;
1713 return (0);
1714 }
1715 id++;
1716 }
1717 dev++;
1718 }
1719 return (ENXIO);
1720 case PUC_CFG_GET_OFS:
1721 *res = (port == 1 || port == 3) ? 8 : 0;
1722 return (0);
1723 case PUC_CFG_GET_RID:
1724 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1725 return (0);
1726 case PUC_CFG_GET_TYPE:
1727 *res = PUC_TYPE_SERIAL;
1728 return (0);
1729 default:
1730 break;
1731 }
1732 return (ENXIO);
1733 }
1734
1735 static int
puc_config_oxford_pci954(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1736 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1737 int port __unused, intptr_t *res)
1738 {
1739
1740 switch (cmd) {
1741 case PUC_CFG_GET_CLOCK:
1742 /*
1743 * OXu16PCI954 use a 14.7456 MHz clock by default while
1744 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1745 */
1746 if (pci_get_revid(sc->sc_dev) == 1)
1747 *res = DEFAULT_RCLK * 8;
1748 else
1749 *res = DEFAULT_RCLK;
1750 return (0);
1751 default:
1752 break;
1753 }
1754 return (ENXIO);
1755 }
1756
1757 static int
puc_config_oxford_pcie(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1758 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1759 intptr_t *res)
1760 {
1761 const struct puc_cfg *cfg = sc->sc_cfg;
1762 int idx;
1763 struct puc_bar *bar;
1764 uint8_t value;
1765
1766 switch (cmd) {
1767 case PUC_CFG_SETUP:
1768 device_printf(sc->sc_dev, "%d UARTs detected\n",
1769 sc->sc_nports);
1770
1771 /* Set UARTs to enhanced mode */
1772 bar = puc_get_bar(sc, cfg->rid);
1773 if (bar == NULL)
1774 return (ENXIO);
1775 for (idx = 0; idx < sc->sc_nports; idx++) {
1776 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1777 0x92);
1778 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1779 value | 0x10);
1780 }
1781 return (0);
1782 case PUC_CFG_GET_LEN:
1783 *res = 0x200;
1784 return (0);
1785 case PUC_CFG_GET_NPORTS:
1786 /*
1787 * Check if we are being called from puc_bfe_attach()
1788 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1789 * puc_get_bar(), so we return a value of 16. This has
1790 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC,
1791 * sc->sc_cfg_data will not contain the true number of
1792 * ports in PUC_CFG_GET_DESC, but we are not implementing
1793 * that call for this device family anyway.
1794 *
1795 * The check is for initialization of sc->sc_bar[idx],
1796 * which is only done in puc_bfe_attach().
1797 */
1798 idx = 0;
1799 do {
1800 if (sc->sc_bar[idx++].b_rid != -1) {
1801 sc->sc_cfg_data = 16;
1802 *res = sc->sc_cfg_data;
1803 return (0);
1804 }
1805 } while (idx < PUC_PCI_BARS);
1806
1807 bar = puc_get_bar(sc, cfg->rid);
1808 if (bar == NULL)
1809 return (ENXIO);
1810
1811 value = bus_read_1(bar->b_res, 0x04);
1812 if (value == 0)
1813 return (ENXIO);
1814
1815 sc->sc_cfg_data = value;
1816 *res = sc->sc_cfg_data;
1817 return (0);
1818 case PUC_CFG_GET_OFS:
1819 *res = 0x1000 + (port << 9);
1820 return (0);
1821 case PUC_CFG_GET_TYPE:
1822 *res = PUC_TYPE_SERIAL;
1823 return (0);
1824 default:
1825 break;
1826 }
1827 return (ENXIO);
1828 }
1829
1830 static int
puc_config_sunix(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1831 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1832 intptr_t *res)
1833 {
1834 int error;
1835
1836 switch (cmd) {
1837 case PUC_CFG_GET_OFS:
1838 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1839 if (error != 0)
1840 return (error);
1841 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1842 return (0);
1843 case PUC_CFG_GET_RID:
1844 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1845 if (error != 0)
1846 return (error);
1847 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1848 return (0);
1849 default:
1850 break;
1851 }
1852 return (ENXIO);
1853 }
1854
1855 static int
puc_config_titan(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1856 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1857 int port, intptr_t *res)
1858 {
1859
1860 switch (cmd) {
1861 case PUC_CFG_GET_OFS:
1862 *res = (port < 3) ? 0 : (port - 2) << 3;
1863 return (0);
1864 case PUC_CFG_GET_RID:
1865 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1866 return (0);
1867 default:
1868 break;
1869 }
1870 return (ENXIO);
1871 }
1872