1 /*-
2 * SPDX-License-Identifier: Beerware
3 *
4 * ----------------------------------------------------------------------------
5 * "THE BEER-WARE LICENSE" (Revision 42):
6 * <[email protected]> wrote this file. As long as you retain this notice you
7 * can do whatever you want with this stuff. If we meet some day, and you think
8 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
9 * ----------------------------------------------------------------------------
10 */
11
12 /*
13 * Driver for Siemens reference design card "Easy321-R1".
14 *
15 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
16 * controller.
17 *
18 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
19 * check it coming in.
20 *
21 * The FALC54 and MUNICH32X have far too many registers and weird modes for
22 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
23 * you will (badly!) need the documentation anyway if you want to mess with
24 * this gadget.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * Stuff to describe the MUNIC32X and FALC54 chips.
32 */
33
34 #define M32_CHAN 32 /* We have 32 channels */
35 #define M32_TS 32 /* We have 32 timeslots */
36
37 #define NG_MN_NODE_TYPE "mn"
38
39 #include <sys/param.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <sys/bus.h>
43 #include <sys/mbuf.h>
44 #include <sys/systm.h>
45 #include <sys/malloc.h>
46
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include "pci_if.h"
50
51 #include <machine/bus.h>
52 #include <machine/resource.h>
53
54 #include <sys/rman.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58
59 #include <netgraph/ng_message.h>
60 #include <netgraph/netgraph.h>
61
62
63 static int mn_maxlatency = 1000;
64 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
65 &mn_maxlatency, 0,
66 "The number of milliseconds a packet is allowed to spend in the output queue. "
67 "If the output queue is longer than this number of milliseconds when the packet "
68 "arrives for output, the packet will be dropped."
69 );
70
71 #ifndef NMN
72 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
73 #define NMN 4
74 #endif
75
76 /* From: PEB 20321 data sheet, p187, table 22 */
77 struct m32xreg {
78 u_int32_t conf, cmd, stat, imask;
79 u_int32_t fill10, piqba, piql, fill1c;
80 u_int32_t mode1, mode2, ccba, txpoll;
81 u_int32_t tiqba, tiql, riqba, riql;
82 u_int32_t lconf, lccba, fill48, ltran;
83 u_int32_t ltiqba, ltiql, lriqba, lriql;
84 u_int32_t lreg0, lreg1, lreg2, lreg3;
85 u_int32_t lreg4, lreg5, lre6, lstat;
86 u_int32_t gpdir, gpdata, gpod, fill8c;
87 u_int32_t ssccon, sscbr, ssctb, sscrb;
88 u_int32_t ssccse, sscim, fillab, fillac;
89 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
91 u_int32_t iomtmo, iomrmo, filld8, filldc;
92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
94 };
95
96 /* From: PEB 2254 data sheet, p80, table 10 */
97 struct f54wreg {
98 u_int16_t xfifo;
99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
106 u_int8_t lim2, fill39[7];
107 u_int8_t fill40[8];
108 u_int8_t fill48[8];
109 u_int8_t fill50[8];
110 u_int8_t fill58[8];
111 u_int8_t dec, fill61, test2, fill63[5];
112 u_int8_t fill68[8];
113 u_int8_t xs[16];
114 };
115
116 /* From: PEB 2254 data sheet, p117, table 10 */
117 struct f54rreg {
118 u_int16_t rfifo;
119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
126 u_int8_t lim2, fill39[7];
127 u_int8_t fill40[8];
128 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
129 u_int16_t fec, cvc, cec1, ebc;
130 u_int16_t cec2, cec3;
131 u_int8_t rsa4, rsa5, rsa6, rsa7;
132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
133 u_int16_t rbc;
134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
135 u_int8_t rs[16];
136 };
137
138 /* Transmit & receive descriptors */
139 struct trxd {
140 u_int32_t flags;
141 vm_offset_t next;
142 vm_offset_t data;
143 u_int32_t status; /* only used for receive */
144 struct mbuf *m; /* software use only */
145 struct trxd *vnext; /* software use only */
146 };
147
148 /* Channel specification */
149 struct cspec {
150 u_int32_t flags;
151 vm_offset_t rdesc;
152 vm_offset_t tdesc;
153 u_int32_t itbs;
154 };
155
156 struct m32_mem {
157 vm_offset_t csa;
158 u_int32_t ccb;
159 u_int32_t reserve1[2];
160 u_int32_t ts[M32_TS];
161 struct cspec cs[M32_CHAN];
162 vm_offset_t crxd[M32_CHAN];
163 vm_offset_t ctxd[M32_CHAN];
164 };
165
166 struct mn_softc;
167 struct sockaddr;
168 struct rtentry;
169
170 static int mn_probe(device_t self);
171 static int mn_attach(device_t self);
172 static void mn_create_channel(struct mn_softc *sc, int chan);
173 static int mn_reset(struct mn_softc *sc);
174 static struct trxd * mn_alloc_desc(void);
175 static void mn_free_desc(struct trxd *dp);
176 static void mn_intr(void *xsc);
177 static u_int32_t mn_parse_ts(const char *s, int *nbit);
178 #ifdef notyet
179 static void m32_dump(struct mn_softc *sc);
180 static void f54_dump(struct mn_softc *sc);
181 static void mn_fmt_ts(char *p, u_int32_t ts);
182 #endif /* notyet */
183 static void f54_init(struct mn_softc *sc);
184
185 static ng_constructor_t ngmn_constructor;
186 static ng_rcvmsg_t ngmn_rcvmsg;
187 static ng_shutdown_t ngmn_shutdown;
188 static ng_newhook_t ngmn_newhook;
189 static ng_connect_t ngmn_connect;
190 static ng_rcvdata_t ngmn_rcvdata;
191 static ng_disconnect_t ngmn_disconnect;
192
193 static struct ng_type mntypestruct = {
194 .version = NG_ABI_VERSION,
195 .name = NG_MN_NODE_TYPE,
196 .constructor = ngmn_constructor,
197 .rcvmsg = ngmn_rcvmsg,
198 .shutdown = ngmn_shutdown,
199 .newhook = ngmn_newhook,
200 .connect = ngmn_connect,
201 .rcvdata = ngmn_rcvdata,
202 .disconnect = ngmn_disconnect,
203 };
204
205 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
206
207 #define NIQB 64
208
209 struct schan {
210 enum {DOWN, UP} state;
211 struct mn_softc *sc;
212 int chan;
213 u_int32_t ts;
214 char name[8];
215 struct trxd *r1, *rl;
216 struct trxd *x1, *xl;
217 hook_p hook;
218
219 time_t last_recv;
220 time_t last_rxerr;
221 time_t last_xmit;
222
223 u_long rx_error;
224
225 u_long short_error;
226 u_long crc_error;
227 u_long dribble_error;
228 u_long long_error;
229 u_long abort_error;
230 u_long overflow_error;
231
232 int last_error;
233 int prev_error;
234
235 u_long tx_pending;
236 u_long tx_limit;
237 };
238
239 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
240
241 struct mn_softc {
242 int unit;
243 device_t dev;
244 struct resource *irq;
245 void *intrhand;
246 enum framing framing;
247 int nhooks;
248 void *m0v, *m1v;
249 vm_offset_t m0p, m1p;
250 struct m32xreg *m32x;
251 struct f54wreg *f54w;
252 struct f54rreg *f54r;
253 struct m32_mem m32_mem;
254 u_int32_t tiqb[NIQB];
255 u_int32_t riqb[NIQB];
256 u_int32_t piqb[NIQB];
257 u_int32_t ltiqb[NIQB];
258 u_int32_t lriqb[NIQB];
259 char name[8];
260 u_int32_t falc_irq, falc_state, framer_state;
261 struct schan *ch[M32_CHAN];
262 char nodename[NG_NODESIZ];
263 node_p node;
264
265 u_long cnt_fec;
266 u_long cnt_cvc;
267 u_long cnt_cec1;
268 u_long cnt_ebc;
269 u_long cnt_cec2;
270 u_long cnt_cec3;
271 u_long cnt_rbc;
272 };
273
274 static int
ngmn_constructor(node_p node)275 ngmn_constructor(node_p node)
276 {
277
278 return (EINVAL);
279 }
280
281 static int
ngmn_shutdown(node_p nodep)282 ngmn_shutdown(node_p nodep)
283 {
284
285 return (EINVAL);
286 }
287
288 static void
ngmn_config(node_p node,char * set,char * ret)289 ngmn_config(node_p node, char *set, char *ret)
290 {
291 struct mn_softc *sc;
292 enum framing wframing;
293
294 sc = NG_NODE_PRIVATE(node);
295
296 if (set != NULL) {
297 if (!strncmp(set, "line ", 5)) {
298 wframing = sc->framing;
299 if (!strcmp(set, "line e1")) {
300 wframing = E1;
301 } else if (!strcmp(set, "line e1u")) {
302 wframing = E1U;
303 } else {
304 strcat(ret, "ENOGROK\n");
305 return;
306 }
307 if (wframing == sc->framing)
308 return;
309 if (sc->nhooks > 0) {
310 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
311 return;
312 }
313 sc->framing = wframing;
314 #if 1
315 f54_init(sc);
316 #else
317 mn_reset(sc);
318 #endif
319 } else {
320 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
321 strcat(ret, "ENOGROK\n");
322 return;
323 }
324 }
325
326 }
327
328 static int
ngmn_rcvmsg(node_p node,item_p item,hook_p lasthook)329 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
330 {
331 struct mn_softc *sc;
332 struct ng_mesg *resp = NULL;
333 struct schan *sch;
334 char *s, *r;
335 int pos, i;
336 struct ng_mesg *msg;
337
338 NGI_GET_MSG(item, msg);
339 sc = NG_NODE_PRIVATE(node);
340
341 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
342 NG_FREE_ITEM(item);
343 NG_FREE_MSG(msg);
344 return (EINVAL);
345 }
346
347 if (msg->header.cmd != NGM_TEXT_CONFIG &&
348 msg->header.cmd != NGM_TEXT_STATUS) {
349 NG_FREE_ITEM(item);
350 NG_FREE_MSG(msg);
351 return (EINVAL);
352 }
353
354 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
355 M_NOWAIT);
356 if (resp == NULL) {
357 NG_FREE_ITEM(item);
358 NG_FREE_MSG(msg);
359 return (ENOMEM);
360 }
361
362 if (msg->header.arglen)
363 s = (char *)msg->data;
364 else
365 s = NULL;
366 r = (char *)resp->data;
367 *r = '\0';
368
369 if (msg->header.cmd == NGM_TEXT_CONFIG) {
370 ngmn_config(node, s, r);
371 resp->header.arglen = strlen(r) + 1;
372 NG_RESPOND_MSG(i, node, item, resp);
373 NG_FREE_MSG(msg);
374 return (0);
375 }
376 pos = 0;
377 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
378 "\40LOS\37AIS\36LFA\35RRA"
379 "\34AUXP\33NMF\32LMFA\31frs0.0"
380 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
381 "\24TS16LFA\23frs1.2\22XLS\21XLO"
382 "\20RS1\17rsw.6\16RRA\15RY0"
383 "\14RY1\13RY2\12RY3\11RY4"
384 "\10SI1\7SI2\6rsp.5\5rsp.4"
385 "\4rsp.3\3RSIF\2RS13\1RS15");
386 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
387 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
388
389 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
390 "\40LOS\37AIS\36LFA\35RRA"
391 "\34AUXP\33NMF\32LMFA\31frs0.0"
392 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
393 "\24TS16LFA\23frs1.2\22XLS\21XLO"
394 "\20RS1\17rsw.6\16RRA\15RY0"
395 "\14RY1\13RY2\12RY3\11RY4"
396 "\10SI1\7SI2\6rsp.5\5rsp.4"
397 "\4rsp.3\3RSIF\2RS13\1RS15");
398 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
399 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
400 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
401 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
402 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
403 for (i = 0; i < M32_CHAN; i++) {
404 if (!sc->ch[i])
405 continue;
406 sch = sc->ch[i];
407
408 pos += sprintf(r + pos, " Chan %d <%s> ",
409 i, NG_HOOK_NAME(sch->hook));
410
411 pos += sprintf(r + pos, " Last Rx: ");
412 if (sch->last_recv)
413 pos += sprintf(r + pos, "%lu s",
414 (unsigned long)(time_second - sch->last_recv));
415 else
416 pos += sprintf(r + pos, "never");
417
418 pos += sprintf(r + pos, ", last RxErr: ");
419 if (sch->last_rxerr)
420 pos += sprintf(r + pos, "%lu s",
421 (unsigned long)(time_second - sch->last_rxerr));
422 else
423 pos += sprintf(r + pos, "never");
424
425 pos += sprintf(r + pos, ", last Tx: ");
426 if (sch->last_xmit)
427 pos += sprintf(r + pos, "%lu s\n",
428 (unsigned long)(time_second - sch->last_xmit));
429 else
430 pos += sprintf(r + pos, "never\n");
431
432 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
433 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
434 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
435 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
436 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
437 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
438 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
439
440 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
441 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
442 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
443 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
444 sch->tx_pending);
445 }
446 resp->header.arglen = pos + 1;
447
448 /* Take care of synchronous response, if any */
449 NG_RESPOND_MSG(i, node, item, resp);
450 NG_FREE_MSG(msg);
451 return (0);
452 }
453
454 static int
ngmn_newhook(node_p node,hook_p hook,const char * name)455 ngmn_newhook(node_p node, hook_p hook, const char *name)
456 {
457 u_int32_t ts, chan;
458 struct mn_softc *sc;
459 int nbit;
460
461 sc = NG_NODE_PRIVATE(node);
462
463 if (name[0] != 't' || name[1] != 's')
464 return (EINVAL);
465
466 ts = mn_parse_ts(name + 2, &nbit);
467 printf("%d bits %x\n", nbit, ts);
468 if (sc->framing == E1 && (ts & 1))
469 return (EINVAL);
470 if (sc->framing == E1U && nbit != 32)
471 return (EINVAL);
472 if (ts == 0)
473 return (EINVAL);
474 if (sc->framing == E1)
475 chan = ffs(ts) - 1;
476 else
477 chan = 1;
478 if (!sc->ch[chan])
479 mn_create_channel(sc, chan);
480 else if (sc->ch[chan]->state == UP)
481 return (EBUSY);
482 sc->ch[chan]->ts = ts;
483 sc->ch[chan]->hook = hook;
484 sc->ch[chan]->tx_limit = nbit * 8;
485 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
486 sc->nhooks++;
487 return(0);
488 }
489
490
491 static struct trxd *mn_desc_free;
492
493 static struct trxd *
mn_alloc_desc(void)494 mn_alloc_desc(void)
495 {
496 struct trxd *dp;
497
498 dp = mn_desc_free;
499 if (dp)
500 mn_desc_free = dp->vnext;
501 else
502 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
503 return (dp);
504 }
505
506 static void
mn_free_desc(struct trxd * dp)507 mn_free_desc(struct trxd *dp)
508 {
509 dp->vnext = mn_desc_free;
510 mn_desc_free = dp;
511 }
512
513 static u_int32_t
mn_parse_ts(const char * s,int * nbit)514 mn_parse_ts(const char *s, int *nbit)
515 {
516 unsigned r;
517 int i, j;
518 char *p;
519
520 r = 0;
521 j = -1;
522 *nbit = 0;
523 while(*s) {
524 i = strtol(s, &p, 0);
525 if (i < 0 || i > 31)
526 return (0);
527 while (j != -1 && j < i) {
528 r |= 1 << j++;
529 (*nbit)++;
530 }
531 j = -1;
532 r |= 1 << i;
533 (*nbit)++;
534 if (*p == ',') {
535 s = p + 1;
536 continue;
537 } else if (*p == '-') {
538 j = i + 1;
539 s = p + 1;
540 continue;
541 } else if (!*p) {
542 break;
543 } else {
544 return (0);
545 }
546 }
547 return (r);
548 }
549
550 #ifdef notyet
551 static void
mn_fmt_ts(char * p,u_int32_t ts)552 mn_fmt_ts(char *p, u_int32_t ts)
553 {
554 char *s;
555 int j;
556
557 s = "";
558 ts &= 0xffffffff;
559 for (j = 0; j < 32; j++) {
560 if (!(ts & (1 << j)))
561 continue;
562 sprintf(p, "%s%d", s, j);
563 p += strlen(p);
564 s = ",";
565 if (!(ts & (1 << (j+1))))
566 continue;
567 for (; j < 32; j++)
568 if (!(ts & (1 << (j+1))))
569 break;
570 sprintf(p, "-%d", j);
571 p += strlen(p);
572 s = ",";
573 }
574 }
575 #endif /* notyet */
576
577 /*
578 * OUTPUT
579 */
580
581 static int
ngmn_rcvdata(hook_p hook,item_p item)582 ngmn_rcvdata(hook_p hook, item_p item)
583 {
584 struct mbuf *m2;
585 struct trxd *dp, *dp2;
586 struct schan *sch;
587 struct mn_softc *sc;
588 int chan, pitch, len;
589 struct mbuf *m;
590
591 sch = NG_HOOK_PRIVATE(hook);
592 sc = sch->sc;
593 chan = sch->chan;
594
595 if (sch->state != UP) {
596 NG_FREE_ITEM(item);
597 return (0);
598 }
599 NGI_GET_M(item, m);
600 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
601 NG_FREE_M(m);
602 NG_FREE_ITEM(item);
603 return (0);
604 }
605 NG_FREE_ITEM(item);
606 pitch = 0;
607 m2 = m;
608 dp2 = sc->ch[chan]->xl;
609 len = m->m_pkthdr.len;
610 while (len) {
611 dp = mn_alloc_desc();
612 if (!dp) {
613 pitch++;
614 m_freem(m);
615 sc->ch[chan]->xl = dp2;
616 dp = dp2->vnext;
617 while (dp) {
618 dp2 = dp->vnext;
619 mn_free_desc(dp);
620 dp = dp2;
621 }
622 sc->ch[chan]->xl->vnext = NULL;
623 break;
624 }
625 dp->data = vtophys(m2->m_data);
626 dp->flags = m2->m_len << 16;
627 dp->flags += 1;
628 len -= m2->m_len;
629 dp->next = vtophys(dp);
630 dp->vnext = NULL;
631 sc->ch[chan]->xl->next = vtophys(dp);
632 sc->ch[chan]->xl->vnext = dp;
633 sc->ch[chan]->xl = dp;
634 if (!len) {
635 dp->m = m;
636 dp->flags |= 0xc0000000;
637 dp2->flags &= ~0x40000000;
638 } else {
639 dp->m = NULL;
640 m2 = m2->m_next;
641 }
642 }
643 if (pitch)
644 printf("%s%d: Short on mem, pitched %d packets\n",
645 sc->name, chan, pitch);
646 else {
647 #if 0
648 printf("%d = %d + %d (%p)\n",
649 sch->tx_pending + m->m_pkthdr.len,
650 sch->tx_pending , m->m_pkthdr.len, m);
651 #endif
652 sch->tx_pending += m->m_pkthdr.len;
653 sc->m32x->txpoll &= ~(1 << chan);
654 }
655 return (0);
656 }
657
658 /*
659 * OPEN
660 */
661 static int
ngmn_connect(hook_p hook)662 ngmn_connect(hook_p hook)
663 {
664 int i, nts, chan;
665 struct trxd *dp, *dp2;
666 struct mbuf *m;
667 struct mn_softc *sc;
668 struct schan *sch;
669 u_int32_t u;
670
671 sch = NG_HOOK_PRIVATE(hook);
672 chan = sch->chan;
673 sc = sch->sc;
674
675 if (sch->state == UP)
676 return (0);
677 sch->state = UP;
678
679 /* Count and configure the timeslots for this channel */
680 for (nts = i = 0; i < 32; i++)
681 if (sch->ts & (1 << i)) {
682 sc->m32_mem.ts[i] = 0x00ff00ff |
683 (chan << 24) | (chan << 8);
684 nts++;
685 }
686
687 /* Init the receiver & xmitter to HDLC */
688 sc->m32_mem.cs[chan].flags = 0x80e90006;
689 /* Allocate two buffers per timeslot */
690 if (nts == 32)
691 sc->m32_mem.cs[chan].itbs = 63;
692 else
693 sc->m32_mem.cs[chan].itbs = nts * 2;
694
695 /* Setup a transmit chain with one descriptor */
696 /* XXX: we actually send a 1 byte packet */
697 dp = mn_alloc_desc();
698 MGETHDR(m, M_WAITOK, MT_DATA);
699 m->m_pkthdr.len = 0;
700 dp->m = m;
701 dp->flags = 0xc0000000 + (1 << 16);
702 dp->next = vtophys(dp);
703 dp->vnext = NULL;
704 dp->data = vtophys(sc->name);
705 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
706 sc->ch[chan]->x1 = dp;
707 sc->ch[chan]->xl = dp;
708
709 /* Setup a receive chain with 5 + NTS descriptors */
710
711 dp = mn_alloc_desc();
712 m = NULL;
713 MGETHDR(m, M_WAITOK, MT_DATA);
714 MCLGET(m, M_WAITOK);
715 dp->m = m;
716 dp->data = vtophys(m->m_data);
717 dp->flags = 0x40000000;
718 dp->flags += 1600 << 16;
719 dp->next = vtophys(dp);
720 dp->vnext = NULL;
721 sc->ch[chan]->rl = dp;
722
723 for (i = 0; i < (nts + 10); i++) {
724 dp2 = dp;
725 dp = mn_alloc_desc();
726 m = NULL;
727 MGETHDR(m, M_WAITOK, MT_DATA);
728 MCLGET(m, M_WAITOK);
729 dp->m = m;
730 dp->data = vtophys(m->m_data);
731 dp->flags = 0x00000000;
732 dp->flags += 1600 << 16;
733 dp->next = vtophys(dp2);
734 dp->vnext = dp2;
735 }
736 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
737 sc->ch[chan]->r1 = dp;
738
739 /* Initialize this channel */
740 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
741 sc->m32x->cmd = 0x1;
742 DELAY(1000);
743 u = sc->m32x->stat;
744 if (!(u & 1))
745 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
746 sc->m32x->stat = 1;
747 /* probably not at splnet, force outward queueing */
748 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
749
750 return (0);
751 }
752
753 /*
754 * CLOSE
755 */
756 static int
ngmn_disconnect(hook_p hook)757 ngmn_disconnect(hook_p hook)
758 {
759 int chan, i;
760 struct mn_softc *sc;
761 struct schan *sch;
762 struct trxd *dp, *dp2;
763 u_int32_t u;
764
765 sch = NG_HOOK_PRIVATE(hook);
766 chan = sch->chan;
767 sc = sch->sc;
768
769 if (sch->state == DOWN)
770 return (0);
771 sch->state = DOWN;
772
773 /* Set receiver & transmitter off */
774 sc->m32_mem.cs[chan].flags = 0x80920006;
775 sc->m32_mem.cs[chan].itbs = 0;
776
777 /* free the timeslots */
778 for (i = 0; i < 32; i++)
779 if (sc->ch[chan]->ts & (1 << i))
780 sc->m32_mem.ts[i] = 0x20002000;
781
782 /* Initialize this channel */
783 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
784 sc->m32x->cmd = 0x1;
785 DELAY(30);
786 u = sc->m32x->stat;
787 if (!(u & 1))
788 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
789 sc->m32x->stat = 1;
790
791 /* Free all receive descriptors and mbufs */
792 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
793 if (dp->m)
794 m_freem(dp->m);
795 sc->ch[chan]->r1 = dp2 = dp->vnext;
796 mn_free_desc(dp);
797 }
798
799 /* Free all transmit descriptors and mbufs */
800 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
801 if (dp->m) {
802 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
803 m_freem(dp->m);
804 }
805 sc->ch[chan]->x1 = dp2 = dp->vnext;
806 mn_free_desc(dp);
807 }
808 sc->nhooks--;
809 return(0);
810 }
811
812 /*
813 * Create a new channel.
814 */
815 static void
mn_create_channel(struct mn_softc * sc,int chan)816 mn_create_channel(struct mn_softc *sc, int chan)
817 {
818 struct schan *sch;
819
820 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
821 M_MN, M_WAITOK | M_ZERO);
822 sch->sc = sc;
823 sch->state = DOWN;
824 sch->chan = chan;
825 sprintf(sch->name, "%s%d", sc->name, chan);
826 return;
827 }
828
829 #ifdef notyet
830 /*
831 * Dump Munich32x state
832 */
833 static void
m32_dump(struct mn_softc * sc)834 m32_dump(struct mn_softc *sc)
835 {
836 u_int32_t *tp4;
837 int i, j;
838
839 printf("mn%d: MUNICH32X dump\n", sc->unit);
840 tp4 = (u_int32_t *)sc->m0v;
841 for(j = 0; j < 64; j += 8) {
842 printf("%02x", j * sizeof *tp4);
843 for(i = 0; i < 8; i++)
844 printf(" %08x", tp4[i+j]);
845 printf("\n");
846 }
847 for(j = 0; j < M32_CHAN; j++) {
848 if (!sc->ch[j])
849 continue;
850 printf("CH%d: state %d ts %08x",
851 j, sc->ch[j]->state, sc->ch[j]->ts);
852 printf(" %08x %08x %08x %08x %08x %08x\n",
853 sc->m32_mem.cs[j].flags,
854 sc->m32_mem.cs[j].rdesc,
855 sc->m32_mem.cs[j].tdesc,
856 sc->m32_mem.cs[j].itbs,
857 sc->m32_mem.crxd[j],
858 sc->m32_mem.ctxd[j] );
859 }
860 }
861
862 /*
863 * Dump Falch54 state
864 */
865 static void
f54_dump(struct mn_softc * sc)866 f54_dump(struct mn_softc *sc)
867 {
868 u_int8_t *tp1;
869 int i, j;
870
871 printf("%s: FALC54 dump\n", sc->name);
872 tp1 = (u_int8_t *)sc->m1v;
873 for(j = 0; j < 128; j += 16) {
874 printf("%s: %02x |", sc->name, j * sizeof *tp1);
875 for(i = 0; i < 16; i++)
876 printf(" %02x", tp1[i+j]);
877 printf("\n");
878 }
879 }
880 #endif /* notyet */
881
882 /*
883 * Init Munich32x
884 */
885 static void
m32_init(struct mn_softc * sc)886 m32_init(struct mn_softc *sc)
887 {
888
889 sc->m32x->conf = 0x00000000;
890 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
891 #if 1
892 sc->m32x->mode2 = 0x00000081;
893 sc->m32x->txpoll = 0xffffffff;
894 #elif 1
895 sc->m32x->mode2 = 0x00000081;
896 sc->m32x->txpoll = 0xffffffff;
897 #else
898 sc->m32x->mode2 = 0x00000101;
899 #endif
900 sc->m32x->lconf = 0x6060009B;
901 sc->m32x->imask = 0x00000000;
902 }
903
904 /*
905 * Init the Falc54
906 */
907 static void
f54_init(struct mn_softc * sc)908 f54_init(struct mn_softc *sc)
909 {
910 sc->f54w->ipc = 0x07;
911
912 sc->f54w->xpm0 = 0xbd;
913 sc->f54w->xpm1 = 0x03;
914 sc->f54w->xpm2 = 0x00;
915
916 sc->f54w->imr0 = 0x18; /* RMB, CASC */
917 sc->f54w->imr1 = 0x08; /* XMB */
918 sc->f54w->imr2 = 0x00;
919 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
920 sc->f54w->imr4 = 0x00;
921
922 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
923 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
924 if (sc->framing == E1)
925 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
926 else if (sc->framing == E1U)
927 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
928
929 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
930 sc->f54w->pcd = 0x0a;
931 sc->f54w->pcr = 0x15;
932 sc->f54w->xsw = 0x9f; /* fmr4 */
933 if (sc->framing == E1)
934 sc->f54w->xsp = 0x1c; /* fmr5 */
935 else if (sc->framing == E1U)
936 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
937 sc->f54w->xc0 = 0x07;
938 sc->f54w->xc1 = 0x3d;
939 sc->f54w->rc0 = 0x05;
940 sc->f54w->rc1 = 0x00;
941 sc->f54w->cmdr = 0x51;
942 }
943
944 static int
mn_reset(struct mn_softc * sc)945 mn_reset(struct mn_softc *sc)
946 {
947 u_int32_t u;
948 int i;
949
950 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
951 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
952
953 bzero(sc->tiqb, sizeof sc->tiqb);
954 sc->m32x->tiqba = vtophys(&sc->tiqb);
955 sc->m32x->tiql = NIQB / 16 - 1;
956
957 bzero(sc->riqb, sizeof sc->riqb);
958 sc->m32x->riqba = vtophys(&sc->riqb);
959 sc->m32x->riql = NIQB / 16 - 1;
960
961 bzero(sc->ltiqb, sizeof sc->ltiqb);
962 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
963 sc->m32x->ltiql = NIQB / 16 - 1;
964
965 bzero(sc->lriqb, sizeof sc->lriqb);
966 sc->m32x->lriqba = vtophys(&sc->lriqb);
967 sc->m32x->lriql = NIQB / 16 - 1;
968
969 bzero(sc->piqb, sizeof sc->piqb);
970 sc->m32x->piqba = vtophys(&sc->piqb);
971 sc->m32x->piql = NIQB / 16 - 1;
972
973 m32_init(sc);
974 f54_init(sc);
975
976 u = sc->m32x->stat;
977 sc->m32x->stat = u;
978 sc->m32_mem.ccb = 0x4;
979 sc->m32x->cmd = 0x1;
980 DELAY(1000);
981 u = sc->m32x->stat;
982 sc->m32x->stat = u;
983
984 /* set all timeslots to known state */
985 for (i = 0; i < 32; i++)
986 sc->m32_mem.ts[i] = 0x20002000;
987
988 if (!(u & 1)) {
989 printf(
990 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
991 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
992 sc->unit, sc->unit);
993 return (0);
994 }
995 return (1);
996 }
997
998 /*
999 * FALC54 interrupt handling
1000 */
1001 static void
f54_intr(struct mn_softc * sc)1002 f54_intr(struct mn_softc *sc)
1003 {
1004 unsigned g, u, s;
1005
1006 g = sc->f54r->gis;
1007 u = sc->f54r->isr0 << 24;
1008 u |= sc->f54r->isr1 << 16;
1009 u |= sc->f54r->isr2 << 8;
1010 u |= sc->f54r->isr3;
1011 sc->falc_irq = u;
1012 /* don't chat about the 1 sec heart beat */
1013 if (u & ~0x40) {
1014 #if 0
1015 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1016 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1017 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1018 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1019 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1020 #endif
1021 s = sc->f54r->frs0 << 24;
1022 s |= sc->f54r->frs1 << 16;
1023 s |= sc->f54r->rsw << 8;
1024 s |= sc->f54r->rsp;
1025 sc->falc_state = s;
1026
1027 s &= ~0x01844038; /* undefined or static bits */
1028 s &= ~0x00009fc7; /* bits we don't care about */
1029 s &= ~0x00780000; /* XXX: TS16 related */
1030 s &= ~0x06000000; /* XXX: Multiframe related */
1031 #if 0
1032 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1033 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1034 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1035 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1036 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1037 #endif
1038 if (s != sc->framer_state) {
1039 #if 0
1040 for (i = 0; i < M32_CHAN; i++) {
1041 if (!sc->ch[i])
1042 continue;
1043 sp = &sc->ch[i]->ifsppp;
1044 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1045 continue;
1046 if (s)
1047 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1048 else
1049 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1050 }
1051 #endif
1052 sc->framer_state = s;
1053 }
1054 }
1055 /* Once per second check error counters */
1056 /* XXX: not clear if this is actually ok */
1057 if (!(u & 0x40))
1058 return;
1059 sc->cnt_fec += sc->f54r->fec;
1060 sc->cnt_cvc += sc->f54r->cvc;
1061 sc->cnt_cec1 += sc->f54r->cec1;
1062 sc->cnt_ebc += sc->f54r->ebc;
1063 sc->cnt_cec2 += sc->f54r->cec2;
1064 sc->cnt_cec3 += sc->f54r->cec3;
1065 sc->cnt_rbc += sc->f54r->rbc;
1066 }
1067
1068 /*
1069 * Transmit interrupt for one channel
1070 */
1071 static void
mn_tx_intr(struct mn_softc * sc,u_int32_t vector)1072 mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1073 {
1074 u_int32_t chan;
1075 struct trxd *dp;
1076 struct mbuf *m;
1077
1078 chan = vector & 0x1f;
1079 if (!sc->ch[chan])
1080 return;
1081 if (sc->ch[chan]->state != UP) {
1082 printf("%s: tx_intr when not UP\n", sc->name);
1083 return;
1084 }
1085 for (;;) {
1086 dp = sc->ch[chan]->x1;
1087 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1088 return;
1089 m = dp->m;
1090 if (m) {
1091 #if 0
1092 printf("%d = %d - %d (%p)\n",
1093 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1094 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1095 #endif
1096 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1097 m_freem(m);
1098 }
1099 sc->ch[chan]->last_xmit = time_second;
1100 sc->ch[chan]->x1 = dp->vnext;
1101 mn_free_desc(dp);
1102 }
1103 }
1104
1105 /*
1106 * Receive interrupt for one channel
1107 */
1108 static void
mn_rx_intr(struct mn_softc * sc,u_int32_t vector)1109 mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1110 {
1111 u_int32_t chan, err;
1112 struct trxd *dp;
1113 struct mbuf *m;
1114 struct schan *sch;
1115
1116 chan = vector & 0x1f;
1117 if (!sc->ch[chan])
1118 return;
1119 sch = sc->ch[chan];
1120 if (sch->state != UP) {
1121 printf("%s: rx_intr when not UP\n", sc->name);
1122 return;
1123 }
1124 vector &= ~0x1f;
1125 if (vector == 0x30000b00)
1126 sch->rx_error++;
1127 for (;;) {
1128 dp = sch->r1;
1129 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1130 return;
1131 m = dp->m;
1132 dp->m = NULL;
1133 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1134 err = (dp->status >> 8) & 0xff;
1135 if (!err) {
1136 int error;
1137 NG_SEND_DATA_ONLY(error, sch->hook, m);
1138 sch->last_recv = time_second;
1139 /* we could be down by now... */
1140 if (sch->state != UP)
1141 return;
1142 } else if (err & 0x40) {
1143 sch->short_error++;
1144 } else if (err & 0x10) {
1145 sch->crc_error++;
1146 } else if (err & 0x08) {
1147 sch->dribble_error++;
1148 } else if (err & 0x04) {
1149 sch->long_error++;
1150 } else if (err & 0x02) {
1151 sch->abort_error++;
1152 } else if (err & 0x01) {
1153 sch->overflow_error++;
1154 }
1155 if (err) {
1156 sch->last_rxerr = time_second;
1157 sch->prev_error = sch->last_error;
1158 sch->last_error = err;
1159 }
1160
1161 sc->ch[chan]->r1 = dp->vnext;
1162
1163 /* Replenish desc + mbuf supplies */
1164 if (!m) {
1165 MGETHDR(m, M_NOWAIT, MT_DATA);
1166 if (m == NULL) {
1167 mn_free_desc(dp);
1168 return; /* ENOBUFS */
1169 }
1170 if (!(MCLGET(m, M_NOWAIT))) {
1171 mn_free_desc(dp);
1172 m_freem(m);
1173 return; /* ENOBUFS */
1174 }
1175 }
1176 dp->m = m;
1177 dp->data = vtophys(m->m_data);
1178 dp->flags = 0x40000000;
1179 dp->flags += 1600 << 16;
1180 dp->next = vtophys(dp);
1181 dp->vnext = NULL;
1182 sc->ch[chan]->rl->next = vtophys(dp);
1183 sc->ch[chan]->rl->vnext = dp;
1184 sc->ch[chan]->rl->flags &= ~0x40000000;
1185 sc->ch[chan]->rl = dp;
1186 }
1187 }
1188
1189
1190 /*
1191 * Interrupt handler
1192 */
1193
1194 static void
mn_intr(void * xsc)1195 mn_intr(void *xsc)
1196 {
1197 struct mn_softc *sc;
1198 u_int32_t stat, lstat, u;
1199 int i, j;
1200
1201 sc = xsc;
1202 stat = sc->m32x->stat;
1203 lstat = sc->m32x->lstat;
1204 #if 0
1205 if (!stat && !(lstat & 2))
1206 return;
1207 #endif
1208
1209 if (stat & ~0xc200) {
1210 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1211 }
1212
1213 if ((stat & 0x200) || (lstat & 2))
1214 f54_intr(sc);
1215
1216 for (j = i = 0; i < 64; i ++) {
1217 u = sc->riqb[i];
1218 if (u) {
1219 sc->riqb[i] = 0;
1220 mn_rx_intr(sc, u);
1221 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1222 continue;
1223 u &= ~0x30000400; /* bits we don't care about */
1224 if ((u & ~0x1f) == 0x00000900)
1225 continue;
1226 if (!(u & ~0x1f))
1227 continue;
1228 if (!j)
1229 printf("%s*: RIQB:", sc->name);
1230 printf(" [%d]=%08x", i, u);
1231 j++;
1232 }
1233 }
1234 if (j)
1235 printf("\n");
1236
1237 for (j = i = 0; i < 64; i ++) {
1238 u = sc->tiqb[i];
1239 if (u) {
1240 sc->tiqb[i] = 0;
1241 mn_tx_intr(sc, u);
1242 if ((u & ~0x1f) == 0x20000800)
1243 continue;
1244 u &= ~0x20000000; /* bits we don't care about */
1245 if (!u)
1246 continue;
1247 if (!j)
1248 printf("%s*: TIQB:", sc->name);
1249 printf(" [%d]=%08x", i, u);
1250 j++;
1251 }
1252 }
1253 if (j)
1254 printf("\n");
1255 sc->m32x->stat = stat;
1256 }
1257
1258 /*
1259 * PCI initialization stuff
1260 */
1261
1262 static int
mn_probe(device_t self)1263 mn_probe (device_t self)
1264 {
1265 u_int id = pci_get_devid(self);
1266
1267 if (sizeof (struct m32xreg) != 256) {
1268 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1269 return (ENXIO);
1270 }
1271 if (sizeof (struct f54rreg) != 128) {
1272 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1273 return (ENXIO);
1274 }
1275 if (sizeof (struct f54wreg) != 128) {
1276 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1277 return (ENXIO);
1278 }
1279
1280 if (id != 0x2101110a)
1281 return (ENXIO);
1282
1283 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1284 return (BUS_PROBE_DEFAULT);
1285 }
1286
1287 static int
mn_attach(device_t self)1288 mn_attach (device_t self)
1289 {
1290 struct mn_softc *sc;
1291 u_int32_t u;
1292 u_int32_t ver;
1293 static int once;
1294 int rid, error;
1295 struct resource *res;
1296
1297 if (!once) {
1298 if (ng_newtype(&mntypestruct))
1299 printf("ng_newtype failed\n");
1300 once++;
1301 }
1302
1303 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1304 device_set_softc(self, sc);
1305
1306 sc->dev = self;
1307 sc->unit = device_get_unit(self);
1308 sc->framing = E1;
1309 sprintf(sc->name, "mn%d", sc->unit);
1310
1311 rid = PCIR_BAR(0);
1312 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1313 if (res == NULL) {
1314 device_printf(self, "Could not map memory\n");
1315 free(sc, M_MN);
1316 return ENXIO;
1317 }
1318 sc->m0v = rman_get_virtual(res);
1319 sc->m0p = rman_get_start(res);
1320
1321 rid = PCIR_BAR(1);
1322 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1323 if (res == NULL) {
1324 device_printf(self, "Could not map memory\n");
1325 free(sc, M_MN);
1326 return ENXIO;
1327 }
1328 sc->m1v = rman_get_virtual(res);
1329 sc->m1p = rman_get_start(res);
1330
1331 /* Allocate interrupt */
1332 rid = 0;
1333 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1334 RF_SHAREABLE | RF_ACTIVE);
1335
1336 if (sc->irq == NULL) {
1337 printf("couldn't map interrupt\n");
1338 free(sc, M_MN);
1339 return(ENXIO);
1340 }
1341
1342 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1343
1344 if (error) {
1345 printf("couldn't set up irq\n");
1346 free(sc, M_MN);
1347 return(ENXIO);
1348 }
1349
1350 u = pci_read_config(self, PCIR_COMMAND, 2);
1351 printf("%x\n", u);
1352 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2);
1353 #if 0
1354 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1355 #endif
1356 u = pci_read_config(self, PCIR_COMMAND, 1);
1357 printf("%x\n", u);
1358
1359 ver = pci_get_revid(self);
1360
1361 sc->m32x = (struct m32xreg *) sc->m0v;
1362 sc->f54w = (struct f54wreg *) sc->m1v;
1363 sc->f54r = (struct f54rreg *) sc->m1v;
1364
1365 /* We must reset before poking at FALC54 registers */
1366 u = mn_reset(sc);
1367 if (!u)
1368 return (0);
1369
1370 printf("mn%d: Munich32X", sc->unit);
1371 switch (ver) {
1372 case 0x13:
1373 printf(" Rev 2.2");
1374 break;
1375 default:
1376 printf(" Rev 0x%x\n", ver);
1377 }
1378 printf(", Falc54");
1379 switch (sc->f54r->vstr) {
1380 case 0:
1381 printf(" Rev < 1.3\n");
1382 break;
1383 case 1:
1384 printf(" Rev 1.3\n");
1385 break;
1386 case 2:
1387 printf(" Rev 1.4\n");
1388 break;
1389 case 0x10:
1390 printf("-LH Rev 1.1\n");
1391 break;
1392 case 0x13:
1393 printf("-LH Rev 1.3\n");
1394 break;
1395 default:
1396 printf(" Rev 0x%x\n", sc->f54r->vstr);
1397 }
1398
1399 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1400 printf("ng_make_node_common failed\n");
1401 return (0);
1402 }
1403 NG_NODE_SET_PRIVATE(sc->node, sc);
1404 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1405 if (ng_name_node(sc->node, sc->nodename)) {
1406 NG_NODE_UNREF(sc->node);
1407 return (0);
1408 }
1409
1410 return (0);
1411 }
1412
1413
1414 static device_method_t mn_methods[] = {
1415 /* Device interface */
1416 DEVMETHOD(device_probe, mn_probe),
1417 DEVMETHOD(device_attach, mn_attach),
1418 DEVMETHOD(device_suspend, bus_generic_suspend),
1419 DEVMETHOD(device_resume, bus_generic_resume),
1420 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1421
1422 DEVMETHOD_END
1423 };
1424
1425 static driver_t mn_driver = {
1426 "mn",
1427 mn_methods,
1428 0
1429 };
1430
1431 static devclass_t mn_devclass;
1432
1433 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
1434