1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H
34
35 #include "t4_hw.h"
36
37 enum {
38 MAX_NPORTS = 4, /* max # of ports */
39 SERNUM_LEN = 24, /* Serial # length */
40 EC_LEN = 16, /* E/C length */
41 ID_LEN = 16, /* ID length */
42 PN_LEN = 16, /* Part Number length */
43 MD_LEN = 16, /* MFG diags version length */
44 MACADDR_LEN = 12, /* MAC Address length */
45 };
46
47 enum {
48 T4_REGMAP_SIZE = (160 * 1024),
49 T5_REGMAP_SIZE = (332 * 1024),
50 };
51
52 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
53
54 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
55
56 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
57
58 enum {
59 PAUSE_RX = 1 << 0,
60 PAUSE_TX = 1 << 1,
61 PAUSE_AUTONEG = 1 << 2
62 };
63
64 enum {
65 FEC_NONE = 0,
66 FEC_RS = 1 << 0,
67 FEC_BASER_RS = 1 << 1,
68 FEC_AUTO = 1 << 5, /* M_FW_PORT_CAP32_FEC + 1 */
69 };
70
71 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
72
73 struct port_stats {
74 u64 tx_octets; /* total # of octets in good frames */
75 u64 tx_frames; /* all good frames */
76 u64 tx_bcast_frames; /* all broadcast frames */
77 u64 tx_mcast_frames; /* all multicast frames */
78 u64 tx_ucast_frames; /* all unicast frames */
79 u64 tx_error_frames; /* all error frames */
80
81 u64 tx_frames_64; /* # of Tx frames in a particular range */
82 u64 tx_frames_65_127;
83 u64 tx_frames_128_255;
84 u64 tx_frames_256_511;
85 u64 tx_frames_512_1023;
86 u64 tx_frames_1024_1518;
87 u64 tx_frames_1519_max;
88
89 u64 tx_drop; /* # of dropped Tx frames */
90 u64 tx_pause; /* # of transmitted pause frames */
91 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
92 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
93 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
94 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
95 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
96 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
97 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
98 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
99
100 u64 rx_octets; /* total # of octets in good frames */
101 u64 rx_frames; /* all good frames */
102 u64 rx_bcast_frames; /* all broadcast frames */
103 u64 rx_mcast_frames; /* all multicast frames */
104 u64 rx_ucast_frames; /* all unicast frames */
105 u64 rx_too_long; /* # of frames exceeding MTU */
106 u64 rx_jabber; /* # of jabber frames */
107 u64 rx_fcs_err; /* # of received frames with bad FCS */
108 u64 rx_len_err; /* # of received frames with length error */
109 u64 rx_symbol_err; /* symbol errors */
110 u64 rx_runt; /* # of short frames */
111
112 u64 rx_frames_64; /* # of Rx frames in a particular range */
113 u64 rx_frames_65_127;
114 u64 rx_frames_128_255;
115 u64 rx_frames_256_511;
116 u64 rx_frames_512_1023;
117 u64 rx_frames_1024_1518;
118 u64 rx_frames_1519_max;
119
120 u64 rx_pause; /* # of received pause frames */
121 u64 rx_ppp0; /* # of received PPP prio 0 frames */
122 u64 rx_ppp1; /* # of received PPP prio 1 frames */
123 u64 rx_ppp2; /* # of received PPP prio 2 frames */
124 u64 rx_ppp3; /* # of received PPP prio 3 frames */
125 u64 rx_ppp4; /* # of received PPP prio 4 frames */
126 u64 rx_ppp5; /* # of received PPP prio 5 frames */
127 u64 rx_ppp6; /* # of received PPP prio 6 frames */
128 u64 rx_ppp7; /* # of received PPP prio 7 frames */
129
130 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
131 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
132 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
133 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
134 u64 rx_trunc0; /* buffer-group 0 truncated packets */
135 u64 rx_trunc1; /* buffer-group 1 truncated packets */
136 u64 rx_trunc2; /* buffer-group 2 truncated packets */
137 u64 rx_trunc3; /* buffer-group 3 truncated packets */
138 };
139
140 struct lb_port_stats {
141 u64 octets;
142 u64 frames;
143 u64 bcast_frames;
144 u64 mcast_frames;
145 u64 ucast_frames;
146 u64 error_frames;
147
148 u64 frames_64;
149 u64 frames_65_127;
150 u64 frames_128_255;
151 u64 frames_256_511;
152 u64 frames_512_1023;
153 u64 frames_1024_1518;
154 u64 frames_1519_max;
155
156 u64 drop;
157
158 u64 ovflow0;
159 u64 ovflow1;
160 u64 ovflow2;
161 u64 ovflow3;
162 u64 trunc0;
163 u64 trunc1;
164 u64 trunc2;
165 u64 trunc3;
166 };
167
168 struct tp_tcp_stats {
169 u32 tcp_out_rsts;
170 u64 tcp_in_segs;
171 u64 tcp_out_segs;
172 u64 tcp_retrans_segs;
173 };
174
175 struct tp_usm_stats {
176 u32 frames;
177 u32 drops;
178 u64 octets;
179 };
180
181 struct tp_fcoe_stats {
182 u32 frames_ddp;
183 u32 frames_drop;
184 u64 octets_ddp;
185 };
186
187 struct tp_err_stats {
188 u32 mac_in_errs[MAX_NCHAN];
189 u32 hdr_in_errs[MAX_NCHAN];
190 u32 tcp_in_errs[MAX_NCHAN];
191 u32 tnl_cong_drops[MAX_NCHAN];
192 u32 ofld_chan_drops[MAX_NCHAN];
193 u32 tnl_tx_drops[MAX_NCHAN];
194 u32 ofld_vlan_drops[MAX_NCHAN];
195 u32 tcp6_in_errs[MAX_NCHAN];
196 u32 ofld_no_neigh;
197 u32 ofld_cong_defer;
198 };
199
200 struct tp_proxy_stats {
201 u32 proxy[MAX_NCHAN];
202 };
203
204 struct tp_cpl_stats {
205 u32 req[MAX_NCHAN];
206 u32 rsp[MAX_NCHAN];
207 };
208
209 struct tp_rdma_stats {
210 u32 rqe_dfr_pkt;
211 u32 rqe_dfr_mod;
212 };
213
214 struct sge_params {
215 int timer_val[SGE_NTIMERS]; /* final, scaled values */
216 int counter_val[SGE_NCOUNTERS];
217 int fl_starve_threshold;
218 int fl_starve_threshold2;
219 int page_shift;
220 int eq_s_qpp;
221 int iq_s_qpp;
222 int spg_len;
223 int pad_boundary;
224 int pack_boundary;
225 int fl_pktshift;
226 u32 sge_control;
227 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES];
228 };
229
230 struct tp_params {
231 unsigned int tre; /* log2 of core clocks per TP tick */
232 unsigned int dack_re; /* DACK timer resolution */
233 unsigned int la_mask; /* what events are recorded by TP LA */
234 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
235
236 uint32_t vlan_pri_map;
237 uint32_t ingress_config;
238 uint64_t hash_filter_mask;
239 __be16 err_vec_mask;
240
241 int8_t fcoe_shift;
242 int8_t port_shift;
243 int8_t vnic_shift;
244 int8_t vlan_shift;
245 int8_t tos_shift;
246 int8_t protocol_shift;
247 int8_t ethertype_shift;
248 int8_t macmatch_shift;
249 int8_t matchtype_shift;
250 int8_t frag_shift;
251 };
252
253 struct vpd_params {
254 unsigned int cclk;
255 u8 ec[EC_LEN + 1];
256 u8 sn[SERNUM_LEN + 1];
257 u8 id[ID_LEN + 1];
258 u8 pn[PN_LEN + 1];
259 u8 na[MACADDR_LEN + 1];
260 u8 md[MD_LEN + 1];
261 };
262
263 struct pci_params {
264 unsigned int vpd_cap_addr;
265 unsigned int mps;
266 unsigned short speed;
267 unsigned short width;
268 };
269
270 /*
271 * Firmware device log.
272 */
273 struct devlog_params {
274 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
275 u32 start; /* start of log in firmware memory */
276 u32 size; /* size of log */
277 u32 addr; /* start address in flat addr space */
278 };
279
280 /* Stores chip specific parameters */
281 struct chip_params {
282 u8 nchan;
283 u8 pm_stats_cnt;
284 u8 cng_ch_bits_log; /* congestion channel map bits width */
285 u8 nsched_cls;
286 u8 cim_num_obq;
287 u16 mps_rplc_size;
288 u16 vfcount;
289 u32 sge_fl_db;
290 u16 mps_tcam_size;
291 };
292
293 /* VF-only parameters. */
294
295 /*
296 * Global Receive Side Scaling (RSS) parameters in host-native format.
297 */
298 struct rss_params {
299 unsigned int mode; /* RSS mode */
300 union {
301 struct {
302 u_int synmapen:1; /* SYN Map Enable */
303 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
304 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
305 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
306 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
307 u_int ofdmapen:1; /* Offload Map Enable */
308 u_int tnlmapen:1; /* Tunnel Map Enable */
309 u_int tnlalllookup:1; /* Tunnel All Lookup */
310 u_int hashtoeplitz:1; /* use Toeplitz hash */
311 } basicvirtual;
312 } u;
313 };
314
315 /*
316 * Maximum resources provisioned for a PCI VF.
317 */
318 struct vf_resources {
319 unsigned int nvi; /* N virtual interfaces */
320 unsigned int neq; /* N egress Qs */
321 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
322 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
323 unsigned int niq; /* N ingress Qs */
324 unsigned int tc; /* PCI-E traffic class */
325 unsigned int pmask; /* port access rights mask */
326 unsigned int nexactf; /* N exact MPS filters */
327 unsigned int r_caps; /* read capabilities */
328 unsigned int wx_caps; /* write/execute capabilities */
329 };
330
331 struct adapter_params {
332 struct sge_params sge;
333 struct tp_params tp; /* PF-only */
334 struct vpd_params vpd;
335 struct pci_params pci;
336 struct devlog_params devlog; /* PF-only */
337 struct rss_params rss; /* VF-only */
338 struct vf_resources vfres; /* VF-only */
339 unsigned int core_vdd;
340
341 unsigned int sf_size; /* serial flash size in bytes */
342 unsigned int sf_nsec; /* # of flash sectors */
343
344 unsigned int fw_vers; /* firmware version */
345 unsigned int bs_vers; /* bootstrap version */
346 unsigned int tp_vers; /* TP microcode version */
347 unsigned int er_vers; /* expansion ROM version */
348 unsigned int scfg_vers; /* Serial Configuration version */
349 unsigned int vpd_vers; /* VPD version */
350
351 unsigned short mtus[NMTUS];
352 unsigned short a_wnd[NCCTRL_WIN];
353 unsigned short b_wnd[NCCTRL_WIN];
354
355 unsigned int cim_la_size;
356
357 uint8_t nports; /* # of ethernet ports */
358 uint8_t portvec;
359 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
360 unsigned int rev:4; /* chip revision */
361 unsigned int fpga:1; /* this is an FPGA */
362 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
363 resources for TOE operation. */
364 unsigned int bypass:1; /* this is a bypass card */
365 unsigned int ethoffload:1;
366 unsigned int hash_filter:1;
367 unsigned int filter2_wr_support:1;
368 unsigned int port_caps32:1;
369
370 unsigned int ofldq_wr_cred;
371 unsigned int eo_wr_cred;
372
373 unsigned int max_ordird_qp;
374 unsigned int max_ird_adapter;
375
376 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */
377
378 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
379 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
380 bool viid_smt_extn_support; /* FW returns vin, vfvld & smt index? */
381 };
382
383 #define CHELSIO_T4 0x4
384 #define CHELSIO_T5 0x5
385 #define CHELSIO_T6 0x6
386
387 /*
388 * State needed to monitor the forward progress of SGE Ingress DMA activities
389 * and possible hangs.
390 */
391 struct sge_idma_monitor_state {
392 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
393 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
394 unsigned int idma_state[2]; /* IDMA Hang detect state */
395 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
396 unsigned int idma_warn[2]; /* time to warning in HZ */
397 };
398
399 struct trace_params {
400 u32 data[TRACE_LEN / 4];
401 u32 mask[TRACE_LEN / 4];
402 unsigned short snap_len;
403 unsigned short min_len;
404 unsigned char skip_ofst;
405 unsigned char skip_len;
406 unsigned char invert;
407 unsigned char port;
408 };
409
410 struct link_config {
411 /* OS-specific code owns all the requested_* fields. */
412 int8_t requested_aneg; /* link autonegotiation */
413 int8_t requested_fc; /* flow control */
414 int8_t requested_fec; /* FEC */
415 u_int requested_speed; /* speed (Mbps) */
416
417 uint32_t supported; /* link capabilities */
418 uint32_t advertising; /* advertised capabilities */
419 uint32_t lp_advertising; /* peer advertised capabilities */
420 uint32_t fec_hint; /* use this fec */
421 u_int speed; /* actual link speed (Mbps) */
422 int8_t fc; /* actual link flow control */
423 int8_t fec; /* actual FEC */
424 bool link_ok; /* link up? */
425 uint8_t link_down_rc; /* link down reason */
426 };
427
428 #include "adapter.h"
429
430 #ifndef PCI_VENDOR_ID_CHELSIO
431 # define PCI_VENDOR_ID_CHELSIO 0x1425
432 #endif
433
434 #define for_each_port(adapter, iter) \
435 for (iter = 0; iter < (adapter)->params.nports; ++iter)
436
is_ftid(const struct adapter * sc,u_int tid)437 static inline int is_ftid(const struct adapter *sc, u_int tid)
438 {
439
440 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base &&
441 tid <= sc->tids.ftid_end);
442 }
443
is_hpftid(const struct adapter * sc,u_int tid)444 static inline int is_hpftid(const struct adapter *sc, u_int tid)
445 {
446
447 return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base &&
448 tid <= sc->tids.hpftid_end);
449 }
450
is_etid(const struct adapter * sc,u_int tid)451 static inline int is_etid(const struct adapter *sc, u_int tid)
452 {
453
454 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base &&
455 tid <= sc->tids.etid_end);
456 }
457
is_offload(const struct adapter * adap)458 static inline int is_offload(const struct adapter *adap)
459 {
460 return adap->params.offload;
461 }
462
is_ethoffload(const struct adapter * adap)463 static inline int is_ethoffload(const struct adapter *adap)
464 {
465 return adap->params.ethoffload;
466 }
467
is_hashfilter(const struct adapter * adap)468 static inline int is_hashfilter(const struct adapter *adap)
469 {
470 return adap->params.hash_filter;
471 }
472
chip_id(struct adapter * adap)473 static inline int chip_id(struct adapter *adap)
474 {
475 return adap->params.chipid;
476 }
477
chip_rev(struct adapter * adap)478 static inline int chip_rev(struct adapter *adap)
479 {
480 return adap->params.rev;
481 }
482
is_t4(struct adapter * adap)483 static inline int is_t4(struct adapter *adap)
484 {
485 return adap->params.chipid == CHELSIO_T4;
486 }
487
is_t5(struct adapter * adap)488 static inline int is_t5(struct adapter *adap)
489 {
490 return adap->params.chipid == CHELSIO_T5;
491 }
492
is_t6(struct adapter * adap)493 static inline int is_t6(struct adapter *adap)
494 {
495 return adap->params.chipid == CHELSIO_T6;
496 }
497
is_fpga(struct adapter * adap)498 static inline int is_fpga(struct adapter *adap)
499 {
500 return adap->params.fpga;
501 }
502
core_ticks_per_usec(const struct adapter * adap)503 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
504 {
505 return adap->params.vpd.cclk / 1000;
506 }
507
us_to_core_ticks(const struct adapter * adap,unsigned int us)508 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
509 unsigned int us)
510 {
511 return (us * adap->params.vpd.cclk) / 1000;
512 }
513
core_ticks_to_us(const struct adapter * adapter,unsigned int ticks)514 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
515 unsigned int ticks)
516 {
517 /* add Core Clock / 2 to round ticks to nearest uS */
518 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
519 adapter->params.vpd.cclk);
520 }
521
dack_ticks_to_usec(const struct adapter * adap,unsigned int ticks)522 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
523 unsigned int ticks)
524 {
525 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
526 }
527
us_to_tcp_ticks(const struct adapter * adap,u_long us)528 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us)
529 {
530
531 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre);
532 }
533
tcp_ticks_to_us(const struct adapter * adap,u_int ticks)534 static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks)
535 {
536 return ((uint64_t)ticks << adap->params.tp.tre) /
537 core_ticks_per_usec(adap);
538 }
539
540 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
541
542 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
543 int size, void *rpl, bool sleep_ok, int timeout);
544 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
545 void *rpl, bool sleep_ok);
546
t4_wr_mbox_timeout(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,int timeout)547 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
548 const void *cmd, int size, void *rpl,
549 int timeout)
550 {
551 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
552 timeout);
553 }
554
t4_wr_mbox(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl)555 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
556 int size, void *rpl)
557 {
558 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
559 }
560
t4_wr_mbox_ns(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl)561 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
562 int size, void *rpl)
563 {
564 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
565 }
566
567 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
568 unsigned int data_reg, u32 *vals, unsigned int nregs,
569 unsigned int start_idx);
570 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
571 unsigned int data_reg, const u32 *vals,
572 unsigned int nregs, unsigned int start_idx);
573
574 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
575
576 struct fw_filter_wr;
577
578 void t4_intr_enable(struct adapter *adapter);
579 void t4_intr_disable(struct adapter *adapter);
580 void t4_intr_clear(struct adapter *adapter);
581 int t4_slow_intr_handler(struct adapter *adapter, bool verbose);
582
583 int t4_hash_mac_addr(const u8 *addr);
584 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
585 struct link_config *lc);
586 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
587 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
588 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
589 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
590 int t4_seeprom_wp(struct adapter *adapter, int enable);
591 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
592 u32 *data, int byte_oriented);
593 int t4_write_flash(struct adapter *adapter, unsigned int addr,
594 unsigned int n, const u8 *data, int byte_oriented);
595 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
596 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
597 int t5_fw_init_extern_mem(struct adapter *adap);
598 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
599 int t4_load_boot(struct adapter *adap, u8 *boot_data,
600 unsigned int boot_addr, unsigned int size);
601 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
602 int t4_flash_cfg_addr(struct adapter *adapter);
603 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
604 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
605 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr);
606 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
607 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
608 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
609 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
610 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
611 int t4_get_version_info(struct adapter *adapter);
612 int t4_init_hw(struct adapter *adapter, u32 fw_params);
613 const struct chip_params *t4_get_chip_params(int chipid);
614 int t4_prep_adapter(struct adapter *adapter, u32 *buf);
615 int t4_shutdown_adapter(struct adapter *adapter);
616 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
617 int t4_init_sge_params(struct adapter *adapter);
618 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
619 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
620 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
621 void t4_fatal_err(struct adapter *adapter, bool fw_error);
622 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
623 int filter_index, int enable);
624 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
625 int filter_index, int *enabled);
626 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
627 int start, int n, const u16 *rspq, unsigned int nrspq);
628 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
629 unsigned int flags);
630 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
631 unsigned int flags, unsigned int defq, unsigned int skeyidx,
632 unsigned int skey);
633 int t4_read_rss(struct adapter *adapter, u16 *entries);
634 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
635 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
636 bool sleep_ok);
637 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
638 u32 *valp, bool sleep_ok);
639 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
640 u32 val, bool sleep_ok);
641 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
642 u32 *vfl, u32 *vfh, bool sleep_ok);
643 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
644 u32 vfl, u32 vfh, bool sleep_ok);
645 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
646 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok);
647 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
648 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok);
649 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
650 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
651 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
652 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
653 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
654 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
655 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
656 unsigned int *valp);
657 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
658 const unsigned int *valp);
659 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
660 unsigned int *valp);
661 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
662 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
663 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
664 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
665 int t4_get_flash_params(struct adapter *adapter);
666
667 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
668 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
669 __be32 *data, u64 *parity);
670 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
671 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
672 __be32 *data);
673 void t4_idma_monitor_init(struct adapter *adapter,
674 struct sge_idma_monitor_state *idma);
675 void t4_idma_monitor(struct adapter *adapter,
676 struct sge_idma_monitor_state *idma,
677 int hz, int ticks);
678
679 unsigned int t4_get_regs_len(struct adapter *adapter);
680 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
681
682 const char *t4_get_port_type_description(enum fw_port_type port_type);
683 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
684 void t4_get_port_stats_offset(struct adapter *adap, int idx,
685 struct port_stats *stats,
686 struct port_stats *offset);
687 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
688 void t4_clr_port_stats(struct adapter *adap, int idx);
689
690 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
691 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
692 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
693 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
694 unsigned int *ipg, bool sleep_ok);
695 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
696 unsigned int mask, unsigned int val);
697 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
698 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
699 bool sleep_ok);
700 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
701 bool sleep_ok);
702 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
703 bool sleep_ok);
704 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
705 bool sleep_ok);
706 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
707 bool sleep_ok);
708 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
709 struct tp_tcp_stats *v6, bool sleep_ok);
710 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
711 struct tp_fcoe_stats *st, bool sleep_ok);
712 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
713 const unsigned short *alpha, const unsigned short *beta);
714
715 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
716
717 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
718 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
719 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
720 unsigned int start, unsigned int n);
721 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
722 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
723 bool sleep_ok);
724 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
725
726 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
727 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
728 u64 mask0, u64 mask1, unsigned int crc, bool enable);
729
730 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
731 enum dev_master master, enum dev_state *state);
732 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
733 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
734 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
735 int t4_fw_restart(struct adapter *adap, unsigned int mbox);
736 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
737 const u8 *fw_data, unsigned int size, int force);
738 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
739 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
740 unsigned int vf, unsigned int nparams, const u32 *params,
741 u32 *val);
742 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
743 unsigned int vf, unsigned int nparams, const u32 *params,
744 u32 *val, int rw);
745 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
746 unsigned int pf, unsigned int vf,
747 unsigned int nparams, const u32 *params,
748 const u32 *val, int timeout);
749 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
750 unsigned int vf, unsigned int nparams, const u32 *params,
751 const u32 *val);
752 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
753 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
754 unsigned int rxqi, unsigned int rxq, unsigned int tc,
755 unsigned int vi, unsigned int cmask, unsigned int pmask,
756 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
757 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
758 unsigned int port, unsigned int pf, unsigned int vf,
759 unsigned int nmac, u8 *mac, u16 *rss_size,
760 uint8_t *vfvld, uint16_t *vin,
761 unsigned int portfunc, unsigned int idstype);
762 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
763 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
764 u16 *rss_size, uint8_t *vfvld, uint16_t *vin);
765 int t4_free_vi(struct adapter *adap, unsigned int mbox,
766 unsigned int pf, unsigned int vf,
767 unsigned int viid);
768 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
769 int mtu, int promisc, int all_multi, int bcast, int vlanex,
770 bool sleep_ok);
771 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
772 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
773 u64 *hash, bool sleep_ok);
774 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
775 int idx, const u8 *addr, bool persist, uint16_t *smt_idx);
776 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
777 bool ucast, u64 vec, bool sleep_ok);
778 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
779 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
780 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
781 bool rx_en, bool tx_en);
782 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
783 unsigned int nblinks);
784 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
785 unsigned int mmd, unsigned int reg, unsigned int *valp);
786 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
787 unsigned int mmd, unsigned int reg, unsigned int val);
788 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
789 int port, unsigned int devid,
790 unsigned int offset, unsigned int len,
791 u8 *buf);
792 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
793 int port, unsigned int devid,
794 unsigned int offset, unsigned int len,
795 u8 *buf);
796 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
797 unsigned int vf, unsigned int iqtype, unsigned int iqid,
798 unsigned int fl0id, unsigned int fl1id);
799 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
800 unsigned int vf, unsigned int iqtype, unsigned int iqid,
801 unsigned int fl0id, unsigned int fl1id);
802 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
803 unsigned int vf, unsigned int eqid);
804 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
805 unsigned int vf, unsigned int eqid);
806 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
807 unsigned int vf, unsigned int eqid);
808 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
809 enum ctxt_type ctype, u32 *data);
810 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
811 u32 *data);
812 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
813 const char *t4_link_down_rc_str(unsigned char link_down_rc);
814 int t4_update_port_info(struct port_info *pi);
815 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
816 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
817 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
818 int sleep_ok);
819 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
820 int rateunit, int ratemode, int channel, int cl,
821 int minrate, int maxrate, int weight, int pktsize,
822 int burstsize, int sleep_ok);
823 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
824 unsigned int maxrate, int sleep_ok);
825 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
826 int weight, int sleep_ok);
827 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
828 int mode, unsigned int maxrate, int pktsize,
829 int sleep_ok);
830 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
831 unsigned int pf, unsigned int vf,
832 unsigned int timeout, unsigned int action);
833 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
834 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
835 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
836
837 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
838 u32 start_index, bool sleep_ok);
839 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
840 u32 start_index, bool sleep_ok);
841 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
842 u32 start_index, bool sleep_ok);
843 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
844 u32 start_index, bool sleep_ok);
845
t4vf_query_params(struct adapter * adapter,unsigned int nparams,const u32 * params,u32 * vals)846 static inline int t4vf_query_params(struct adapter *adapter,
847 unsigned int nparams, const u32 *params,
848 u32 *vals)
849 {
850 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals);
851 }
852
t4vf_set_params(struct adapter * adapter,unsigned int nparams,const u32 * params,const u32 * vals)853 static inline int t4vf_set_params(struct adapter *adapter,
854 unsigned int nparams, const u32 *params,
855 const u32 *vals)
856 {
857 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals);
858 }
859
t4vf_wr_mbox(struct adapter * adap,const void * cmd,int size,void * rpl)860 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd,
861 int size, void *rpl)
862 {
863 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
864 }
865
866 int t4vf_wait_dev_ready(struct adapter *adapter);
867 int t4vf_fw_reset(struct adapter *adapter);
868 int t4vf_get_sge_params(struct adapter *adapter);
869 int t4vf_get_rss_glb_config(struct adapter *adapter);
870 int t4vf_get_vfres(struct adapter *adapter);
871 int t4vf_prep_adapter(struct adapter *adapter);
872 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
873 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset,
874 unsigned int *pbar2_qid);
875 unsigned int fwcap_to_speed(uint32_t caps);
876 uint32_t speed_to_fwcap(unsigned int speed);
877 uint32_t fwcap_top_speed(uint32_t caps);
878
879 static inline int
port_top_speed(const struct port_info * pi)880 port_top_speed(const struct port_info *pi)
881 {
882
883 /* Mbps -> Gbps */
884 return (fwcap_to_speed(pi->link_cfg.supported) / 1000);
885 }
886
887 #endif /* __CHELSIO_COMMON_H */
888