1 /* 2 * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 3 * 4 * $FreeBSD$ 5 * 6 * Obtained from: 7 * 8 * Copyright (c) 1995-1998 Advanced System Products, Inc. 9 * All Rights Reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that redistributions of source 13 * code retain the above copyright notice and this comment without 14 * modification. 15 */ 16 17 #ifndef _ADMCODE_H_ 18 #define _ADMCODE_H_ 19 20 extern u_int16_t adw_mcode[]; 21 extern u_int16_t adw_mcode_size; 22 extern u_int32_t adw_mcode_chksum; 23 24 /* 25 * Fixed LRAM locations of microcode operating variables. 26 */ 27 #define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 28 #define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 29 #define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 30 #define ADW_MC_STACK_BEGIN 0x002E /* microcode stack begin */ 31 #define ADW_MC_STACK_END 0x0030 /* microcode stack end */ 32 #define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 33 #define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 34 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 35 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 36 #define ADW_MC_HALTCODE 0x0094 /* microcode halt code */ 37 #define ADW_MC_CALLERPC 0x0096 /* microcode halt caller PC */ 38 #define ADW_MC_ADAPTER_SCSI_ID 0x0098 /* one ID byte + reserved */ 39 #define ADW_MC_ULTRA_ABLE 0x009C 40 #define ADW_MC_SDTR_ABLE 0x009E 41 #define ADW_MC_TAGQNG_ABLE 0x00A0 42 #define ADW_MC_DISC_ENABLE 0x00A2 43 #define ADW_MC_IDLE_CMD 0x00A6 44 #define ADW_MC_IDLE_PARA_STAT 0x00A8 45 #define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 46 #define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 47 #define ADW_MC_DEFAULT_MEM_CFG 0x00B0 48 #define ADW_MC_DEFAULT_SEL_MASK 0x00B2 49 #define ADW_MC_RISC_NEXT_READY 0x00B4 50 #define ADW_MC_RISC_NEXT_DONE 0x00B5 51 #define ADW_MC_SDTR_DONE 0x00B6 52 #define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 53 #define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 54 #define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 55 #define ADW_HSHK_CFG_WIDE_XFR 0x8000 56 #define ADW_HSHK_CFG_RATE_MASK 0x0F00 57 #define ADW_HSHK_CFG_RATE_SHIFT 8 58 #define ADW_HSHK_CFG_PERIOD_FACTOR(cfg_val) \ 59 ((((((cfg_val) & ADW_HSHK_CFG_RATE_MASK) >> ADW_HSHK_CFG_RATE_SHIFT) \ 60 * 25) + 50)/4) 61 #define ADW_HSHK_CFG_OFFSET 0x001F 62 #define ADW_MC_WDTR_ABLE 0x0120 /* Wide Transfer TID bitmask. */ 63 #define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 64 #define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 65 #define ADW_MC_WDTR_DONE 0x0124 66 #define ADW_MC_HOST_NEXT_READY 0x0128 /* Host Next Ready RQL Entry. */ 67 #define ADW_MC_HOST_NEXT_DONE 0x0129 /* Host Next Done RQL Entry. */ 68 69 /* 70 * LRAM RISC Queue Lists (LRAM addresses 0x1200 - 0x19FF) 71 * 72 * Each of the 255 Adv Library/Microcode RISC queue lists or mailboxes 73 * starting at LRAM address 0x1200 is 8 bytes and has the following 74 * structure. Only 253 of these are actually used for command queues. 75 */ 76 #define ADW_MC_RISC_Q_LIST_BASE 0x1200 77 #define ADW_MC_RISC_Q_LIST_SIZE 0x0008 78 #define ADW_MC_RISC_Q_TOTAL_CNT 0x00FF /* Num. queue slots in LRAM. */ 79 #define ADW_MC_RISC_Q_FIRST 0x0001 80 #define ADW_MC_RISC_Q_LAST 0x00FF 81 82 /* RISC Queue List structure - 8 bytes */ 83 #define RQL_FWD 0 /* forward pointer (1 byte) */ 84 #define RQL_BWD 1 /* backward pointer (1 byte) */ 85 #define RQL_STATE 2 /* state byte - free, ready, done, aborted (1 byte) */ 86 #define RQL_TID 3 /* request target id (1 byte) */ 87 #define RQL_PHYADDR 4 /* request physical pointer (4 bytes) */ 88 89 /* RISC Queue List state values */ 90 #define ADW_MC_QS_FREE 0x00 91 #define ADW_MC_QS_READY 0x01 92 #define ADW_MC_QS_DONE 0x40 93 #define ADW_MC_QS_ABORTED 0x80 94 95 /* RISC Queue List pointer values */ 96 #define ADW_MC_NULL_Q 0x00 97 #define ADW_MC_BIOS_Q 0xFF 98 99 /* ADW_SCSI_REQ_Q 'cntl' field values */ 100 #define ADW_MC_QC_START_MOTOR 0x02 /* Issue start motor. */ 101 #define ADW_MC_QC_NO_OVERRUN 0x04 /* Don't report overrun. */ 102 #define ADW_MC_QC_FIRST_DMA 0x08 /* Internal microcode flag. */ 103 #define ADW_MC_QC_ABORTED 0x10 /* Request aborted by host. */ 104 #define ADW_MC_QC_REQ_SENSE 0x20 /* Auto-Request Sense. */ 105 #define ADW_MC_QC_DOS_REQ 0x80 /* Request issued by DOS. */ 106 107 /* 108 * Microcode idle loop commands 109 */ 110 typedef enum { 111 ADW_IDLE_CMD_COMPLETED = 0x0000, 112 ADW_IDLE_CMD_STOP_CHIP = 0x0001, 113 ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 114 ADW_IDLE_CMD_SEND_INT = 0x0004, 115 ADW_IDLE_CMD_ABORT = 0x0008, 116 ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 117 ADW_IDLE_CMD_SCSI_RESET = 0x0020 118 } adw_idle_cmd_t; 119 120 typedef enum { 121 ADW_IDLE_CMD_FAILURE = 0x0000, 122 ADW_IDLE_CMD_SUCCESS = 0x0001 123 } adw_idle_cmd_status_t; 124 125 126 #endif /* _ADMCODE_H_ */ 127