1 /*- 2 * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 3 * 4 * $FreeBSD$ 5 * 6 * Obtained from: 7 * 8 * Copyright (c) 1995-1999 Advanced System Products, Inc. 9 * All Rights Reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that redistributions of source 13 * code retain the above copyright notice and this comment without 14 * modification. 15 */ 16 17 #ifndef _ADMCODE_H_ 18 #define _ADMCODE_H_ 19 20 struct adw_mcode 21 { 22 const u_int8_t* mcode_buf; 23 const u_int32_t mcode_chksum; 24 const u_int16_t mcode_size; 25 }; 26 27 extern const struct adw_mcode adw_asc3550_mcode_data; 28 extern const struct adw_mcode adw_asc38C0800_mcode_data; 29 30 /* 31 * Fixed LRAM locations of microcode operating variables. 32 */ 33 #define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 34 #define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 35 #define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 36 #define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 37 #define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 38 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 39 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 40 #define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 41 #define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */ 42 #define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 43 #define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 44 #define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 45 #define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 46 #define ADW_MC_CHIP_TYPE 0x009A 47 #define ADW_MC_INTRB_CODE 0x009B 48 #define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 49 #define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */ 50 #define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/ 51 #define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /* 52 * Host Initiated 53 * SCSI Bus Reset. 54 */ 55 #define ADW_MC_WDTR_ABLE_BIOS_31 0x0120 56 #define ADW_MC_WDTR_ABLE 0x009C 57 #define ADW_MC_SDTR_ABLE 0x009E 58 #define ADW_MC_TAGQNG_ABLE 0x00A0 59 #define ADW_MC_DISC_ENABLE 0x00A2 60 #define ADW_MC_IDLE_CMD_STATUS 0x00A4 61 #define ADW_MC_IDLE_CMD 0x00A6 62 #define ADW_MC_IDLE_CMD_PARAMETER 0x00A8 63 #define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 64 #define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 65 #define ADW_MC_DEFAULT_MEM_CFG 0x00B0 66 #define ADW_MC_DEFAULT_SEL_MASK 0x00B2 67 #define ADW_MC_RISC_NEXT_READY 0x00B4 68 #define ADW_MC_RISC_NEXT_DONE 0x00B5 69 #define ADW_MC_SDTR_DONE 0x00B6 70 #define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 71 #define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 72 #define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 73 #define ADW_HSHK_CFG_WIDE_XFR 0x8000 74 #define ADW_HSHK_CFG_RATE_MASK 0x7F00 75 #define ADW_HSHK_CFG_RATE_SHIFT 8 76 #define ADW_HSHK_CFG_OFFSET 0x001F 77 #define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 78 #define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 79 #define ADW_MC_WDTR_DONE 0x0124 80 #define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 81 #define ADW_MC_ICQ 0x0160 82 #define ADW_MC_IRQ 0x0164 83 84 /* ADW_SCSI_REQ_Q 'cntl' field values */ 85 #define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */ 86 #define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 87 #define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 88 #define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 89 #define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */ 90 91 #define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 92 #define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 93 #define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/ 94 #define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 95 #define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/ 96 /* 97 * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or 98 * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 99 */ 100 #define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 101 #define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 102 103 struct adw_carrier 104 { 105 u_int32_t carr_offset; /* Carrier byte offset into our array */ 106 u_int32_t carr_ba; /* Carrier Bus Address */ 107 u_int32_t areq_ba; /* SCSI Req Queue Bus Address */ 108 u_int32_t next_ba; 109 #define ADW_RQ_DONE 0x00000001 110 #define ADW_CQ_STOPPER 0x00000000 111 #define ADW_NEXT_BA_MASK 0xFFFFFFF0 112 }; 113 114 /* 115 * Microcode idle loop commands 116 */ 117 typedef enum { 118 ADW_IDLE_CMD_COMPLETED = 0x0000, 119 ADW_IDLE_CMD_STOP_CHIP = 0x0001, 120 ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 121 ADW_IDLE_CMD_SEND_INT = 0x0004, 122 ADW_IDLE_CMD_ABORT = 0x0008, 123 ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 124 ADW_IDLE_CMD_SCSI_RESET_START = 0x0020, 125 ADW_IDLE_CMD_SCSI_RESET_END = 0x0040, 126 ADW_IDLE_CMD_SCSIREQ = 0x0080 127 } adw_idle_cmd_t; 128 129 typedef enum { 130 ADW_IDLE_CMD_FAILURE = 0x0000, 131 ADW_IDLE_CMD_SUCCESS = 0x0001 132 } adw_idle_cmd_status_t; 133 134 135 #endif /* _ADMCODE_H_ */ 136