1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "OutputSections.h" 12 #include "Symbols.h" 13 #include "SyntheticSections.h" 14 #include "Target.h" 15 #include "Thunks.h" 16 #include "lld/Common/ErrorHandler.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 uint32_t calcEFlags() const override; 32 RelExpr getRelExpr(RelType Type, const Symbol &S, 33 const uint8_t *Loc) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 bool isPicRel(RelType Type) const override; 36 RelType getDynRel(RelType Type) const override; 37 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 38 void writePltHeader(uint8_t *Buf) const override; 39 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 40 int32_t Index, unsigned RelOff) const override; 41 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 42 uint64_t BranchAddr, const Symbol &S) const override; 43 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 44 bool usesOnlyLowPageBits(RelType Type) const override; 45 }; 46 } // namespace 47 48 template <class ELFT> MIPS<ELFT>::MIPS() { 49 GotPltHeaderEntriesNum = 2; 50 DefaultMaxPageSize = 65536; 51 GotEntrySize = sizeof(typename ELFT::uint); 52 GotPltEntrySize = sizeof(typename ELFT::uint); 53 PltEntrySize = 16; 54 PltHeaderSize = 32; 55 CopyRel = R_MIPS_COPY; 56 PltRel = R_MIPS_JUMP_SLOT; 57 NeedsThunks = true; 58 TrapInstr = 0xefefefef; 59 60 if (ELFT::Is64Bits) { 61 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 TlsGotRel = R_MIPS_TLS_TPREL64; 63 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 64 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 65 } else { 66 RelativeRel = R_MIPS_REL32; 67 TlsGotRel = R_MIPS_TLS_TPREL32; 68 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 69 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 70 } 71 } 72 73 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 74 return calcMipsEFlags<ELFT>(); 75 } 76 77 template <class ELFT> 78 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S, 79 const uint8_t *Loc) const { 80 // See comment in the calculateMipsRelChain. 81 if (ELFT::Is64Bits || Config->MipsN32Abi) 82 Type &= 0xff; 83 84 switch (Type) { 85 case R_MIPS_JALR: 86 case R_MICROMIPS_JALR: 87 return R_HINT; 88 case R_MIPS_GPREL16: 89 case R_MIPS_GPREL32: 90 case R_MICROMIPS_GPREL16: 91 case R_MICROMIPS_GPREL7_S2: 92 return R_MIPS_GOTREL; 93 case R_MIPS_26: 94 case R_MICROMIPS_26_S1: 95 return R_PLT; 96 case R_MICROMIPS_PC26_S1: 97 return R_PLT_PC; 98 case R_MIPS_HI16: 99 case R_MIPS_LO16: 100 case R_MIPS_HIGHER: 101 case R_MIPS_HIGHEST: 102 case R_MICROMIPS_HI16: 103 case R_MICROMIPS_LO16: 104 case R_MICROMIPS_HIGHER: 105 case R_MICROMIPS_HIGHEST: 106 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 107 // offset between start of function and 'gp' value which by default 108 // equal to the start of .got section. In that case we consider these 109 // relocations as relative. 110 if (&S == ElfSym::MipsGpDisp) 111 return R_MIPS_GOT_GP_PC; 112 if (&S == ElfSym::MipsLocalGp) 113 return R_MIPS_GOT_GP; 114 LLVM_FALLTHROUGH; 115 case R_MIPS_32: 116 case R_MIPS_64: 117 case R_MIPS_GOT_OFST: 118 case R_MIPS_SUB: 119 case R_MIPS_TLS_DTPREL_HI16: 120 case R_MIPS_TLS_DTPREL_LO16: 121 case R_MIPS_TLS_DTPREL32: 122 case R_MIPS_TLS_DTPREL64: 123 case R_MIPS_TLS_TPREL_HI16: 124 case R_MIPS_TLS_TPREL_LO16: 125 case R_MIPS_TLS_TPREL32: 126 case R_MIPS_TLS_TPREL64: 127 case R_MICROMIPS_GOT_OFST: 128 case R_MICROMIPS_SUB: 129 case R_MICROMIPS_TLS_DTPREL_HI16: 130 case R_MICROMIPS_TLS_DTPREL_LO16: 131 case R_MICROMIPS_TLS_TPREL_HI16: 132 case R_MICROMIPS_TLS_TPREL_LO16: 133 return R_ABS; 134 case R_MIPS_PC32: 135 case R_MIPS_PC16: 136 case R_MIPS_PC19_S2: 137 case R_MIPS_PC21_S2: 138 case R_MIPS_PC26_S2: 139 case R_MIPS_PCHI16: 140 case R_MIPS_PCLO16: 141 case R_MICROMIPS_PC7_S1: 142 case R_MICROMIPS_PC10_S1: 143 case R_MICROMIPS_PC16_S1: 144 case R_MICROMIPS_PC18_S3: 145 case R_MICROMIPS_PC19_S2: 146 case R_MICROMIPS_PC23_S2: 147 case R_MICROMIPS_PC21_S1: 148 return R_PC; 149 case R_MIPS_GOT16: 150 case R_MICROMIPS_GOT16: 151 if (S.isLocal()) 152 return R_MIPS_GOT_LOCAL_PAGE; 153 LLVM_FALLTHROUGH; 154 case R_MIPS_CALL16: 155 case R_MIPS_GOT_DISP: 156 case R_MIPS_TLS_GOTTPREL: 157 case R_MICROMIPS_CALL16: 158 case R_MICROMIPS_GOT_DISP: 159 case R_MICROMIPS_TLS_GOTTPREL: 160 return R_MIPS_GOT_OFF; 161 case R_MIPS_CALL_HI16: 162 case R_MIPS_CALL_LO16: 163 case R_MIPS_GOT_HI16: 164 case R_MIPS_GOT_LO16: 165 case R_MICROMIPS_CALL_HI16: 166 case R_MICROMIPS_CALL_LO16: 167 case R_MICROMIPS_GOT_HI16: 168 case R_MICROMIPS_GOT_LO16: 169 return R_MIPS_GOT_OFF32; 170 case R_MIPS_GOT_PAGE: 171 case R_MICROMIPS_GOT_PAGE: 172 return R_MIPS_GOT_LOCAL_PAGE; 173 case R_MIPS_TLS_GD: 174 case R_MICROMIPS_TLS_GD: 175 return R_MIPS_TLSGD; 176 case R_MIPS_TLS_LDM: 177 case R_MICROMIPS_TLS_LDM: 178 return R_MIPS_TLSLD; 179 case R_MIPS_NONE: 180 return R_NONE; 181 default: 182 return R_INVALID; 183 } 184 } 185 186 template <class ELFT> bool MIPS<ELFT>::isPicRel(RelType Type) const { 187 return Type == R_MIPS_32 || Type == R_MIPS_64; 188 } 189 190 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 191 return RelativeRel; 192 } 193 194 template <class ELFT> 195 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const { 196 uint64_t VA = InX::Plt->getVA(); 197 if (isMicroMips()) 198 VA |= 1; 199 write32<ELFT::TargetEndianness>(Buf, VA); 200 } 201 202 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 203 // The major opcode of a microMIPS instruction needs to appear 204 // in the first 16-bit word (lowest address) for efficient hardware 205 // decode so that it knows if the instruction is 16-bit or 32-bit 206 // as early as possible. To do so, little-endian binaries keep 16-bit 207 // words in a big-endian order. That is why we have to swap these 208 // words to get a correct value. 209 uint32_t V = read32<E>(Loc); 210 if (E == support::little) 211 return (V << 16) | (V >> 16); 212 return V; 213 } 214 215 template <endianness E> 216 static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 217 uint8_t Shift) { 218 uint32_t Instr = read32<E>(Loc); 219 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 220 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 221 write32<E>(Loc, Data); 222 } 223 224 template <endianness E> 225 static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 226 uint8_t Shift) { 227 // See comments in readShuffle for purpose of this code. 228 uint16_t *Words = (uint16_t *)Loc; 229 if (E == support::little) 230 std::swap(Words[0], Words[1]); 231 232 writeRelocation<E>(Loc, V, BitsSize, Shift); 233 234 if (E == support::little) 235 std::swap(Words[0], Words[1]); 236 } 237 238 template <endianness E> 239 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 240 uint8_t Shift) { 241 uint16_t Instr = read16<E>(Loc); 242 uint16_t Mask = 0xffff >> (16 - BitsSize); 243 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 244 write16<E>(Loc, Data); 245 } 246 247 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 248 const endianness E = ELFT::TargetEndianness; 249 if (isMicroMips()) { 250 uint64_t GotPlt = InX::GotPlt->getVA(); 251 uint64_t Plt = InX::Plt->getVA(); 252 // Overwrite trap instructions written by Writer::writeTrapInstr. 253 memset(Buf, 0, PltHeaderSize); 254 255 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 256 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 257 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 258 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 259 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 260 write16<E>(Buf + 14, 0xfffe); 261 write16<E>(Buf + 16, 0x0dff); // move $15, $31 262 if (isMipsR6()) { 263 write16<E>(Buf + 18, 0x0f83); // move $28, $3 264 write16<E>(Buf + 20, 0x472b); // jalrc $25 265 write16<E>(Buf + 22, 0x0c00); // nop 266 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 267 } else { 268 write16<E>(Buf + 18, 0x45f9); // jalrc $25 269 write16<E>(Buf + 20, 0x0f83); // move $28, $3 270 write16<E>(Buf + 22, 0x0c00); // nop 271 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 272 } 273 return; 274 } 275 276 if (Config->MipsN32Abi) { 277 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 278 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 279 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 280 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 281 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 282 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 283 } else if (ELFT::Is64Bits) { 284 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 285 write32<E>(Buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 286 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 287 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 288 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 289 write32<E>(Buf + 20, 0x0018c0c2); // srl $24, $24, 3 290 } else { 291 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 292 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 293 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 294 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 295 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 296 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 297 } 298 299 uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809; 300 write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25 301 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 302 303 uint64_t GotPlt = InX::GotPlt->getVA(); 304 writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16); 305 writeRelocation<E>(Buf + 4, GotPlt, 16, 0); 306 writeRelocation<E>(Buf + 8, GotPlt, 16, 0); 307 } 308 309 template <class ELFT> 310 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 311 uint64_t PltEntryAddr, int32_t Index, 312 unsigned RelOff) const { 313 const endianness E = ELFT::TargetEndianness; 314 if (isMicroMips()) { 315 // Overwrite trap instructions written by Writer::writeTrapInstr. 316 memset(Buf, 0, PltEntrySize); 317 318 if (isMipsR6()) { 319 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 320 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 321 write16<E>(Buf + 8, 0x0f02); // move $24, $2 322 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 323 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 324 } else { 325 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 326 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 327 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 328 write16<E>(Buf + 10, 0x0f02); // move $24, $2 329 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 330 } 331 return; 332 } 333 334 uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009) 335 : (Config->ZHazardplt ? 0x03200408 : 0x03200008); 336 337 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 338 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 339 write32<E>(Buf + 8, JrInst); // jr $25 / jr.hb $25 340 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 341 writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 342 writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0); 343 writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0); 344 } 345 346 template <class ELFT> 347 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 348 uint64_t BranchAddr, const Symbol &S) const { 349 // Any MIPS PIC code function is invoked with its address in register $t9. 350 // So if we have a branch instruction from non-PIC code to the PIC one 351 // we cannot make the jump directly and need to create a small stubs 352 // to save the target function address. 353 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 354 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 355 Type != R_MICROMIPS_PC26_S1) 356 return false; 357 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 358 if (!F) 359 return false; 360 // If current file has PIC code, LA25 stub is not required. 361 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 362 return false; 363 auto *D = dyn_cast<Defined>(&S); 364 // LA25 is required if target file has PIC code 365 // or target symbol is a PIC symbol. 366 return D && isMipsPIC<ELFT>(D); 367 } 368 369 template <class ELFT> 370 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 371 const endianness E = ELFT::TargetEndianness; 372 switch (Type) { 373 case R_MIPS_32: 374 case R_MIPS_GPREL32: 375 case R_MIPS_TLS_DTPREL32: 376 case R_MIPS_TLS_TPREL32: 377 return SignExtend64<32>(read32<E>(Buf)); 378 case R_MIPS_26: 379 // FIXME (simon): If the relocation target symbol is not a PLT entry 380 // we should use another expression for calculation: 381 // ((A << 2) | (P & 0xf0000000)) >> 2 382 return SignExtend64<28>(read32<E>(Buf) << 2); 383 case R_MIPS_GOT16: 384 case R_MIPS_HI16: 385 case R_MIPS_PCHI16: 386 return SignExtend64<16>(read32<E>(Buf)) << 16; 387 case R_MIPS_GPREL16: 388 case R_MIPS_LO16: 389 case R_MIPS_PCLO16: 390 case R_MIPS_TLS_DTPREL_HI16: 391 case R_MIPS_TLS_DTPREL_LO16: 392 case R_MIPS_TLS_TPREL_HI16: 393 case R_MIPS_TLS_TPREL_LO16: 394 return SignExtend64<16>(read32<E>(Buf)); 395 case R_MICROMIPS_GOT16: 396 case R_MICROMIPS_HI16: 397 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 398 case R_MICROMIPS_GPREL16: 399 case R_MICROMIPS_LO16: 400 case R_MICROMIPS_TLS_DTPREL_HI16: 401 case R_MICROMIPS_TLS_DTPREL_LO16: 402 case R_MICROMIPS_TLS_TPREL_HI16: 403 case R_MICROMIPS_TLS_TPREL_LO16: 404 return SignExtend64<16>(readShuffle<E>(Buf)); 405 case R_MICROMIPS_GPREL7_S2: 406 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 407 case R_MIPS_PC16: 408 return SignExtend64<18>(read32<E>(Buf) << 2); 409 case R_MIPS_PC19_S2: 410 return SignExtend64<21>(read32<E>(Buf) << 2); 411 case R_MIPS_PC21_S2: 412 return SignExtend64<23>(read32<E>(Buf) << 2); 413 case R_MIPS_PC26_S2: 414 return SignExtend64<28>(read32<E>(Buf) << 2); 415 case R_MIPS_PC32: 416 return SignExtend64<32>(read32<E>(Buf)); 417 case R_MICROMIPS_26_S1: 418 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 419 case R_MICROMIPS_PC7_S1: 420 return SignExtend64<8>(read16<E>(Buf) << 1); 421 case R_MICROMIPS_PC10_S1: 422 return SignExtend64<11>(read16<E>(Buf) << 1); 423 case R_MICROMIPS_PC16_S1: 424 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 425 case R_MICROMIPS_PC18_S3: 426 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 427 case R_MICROMIPS_PC19_S2: 428 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 429 case R_MICROMIPS_PC21_S1: 430 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 431 case R_MICROMIPS_PC23_S2: 432 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 433 case R_MICROMIPS_PC26_S1: 434 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 435 default: 436 return 0; 437 } 438 } 439 440 static std::pair<uint32_t, uint64_t> 441 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 442 // MIPS N64 ABI packs multiple relocations into the single relocation 443 // record. In general, all up to three relocations can have arbitrary 444 // types. In fact, Clang and GCC uses only a few combinations. For now, 445 // we support two of them. That is allow to pass at least all LLVM 446 // test suite cases. 447 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 448 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 449 // The first relocation is a 'real' relocation which is calculated 450 // using the corresponding symbol's value. The second and the third 451 // relocations used to modify result of the first one: extend it to 452 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 453 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 454 RelType Type2 = (Type >> 8) & 0xff; 455 RelType Type3 = (Type >> 16) & 0xff; 456 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 457 return std::make_pair(Type, Val); 458 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 459 return std::make_pair(Type2, Val); 460 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 461 return std::make_pair(Type3, -Val); 462 if (Type2 == R_MICROMIPS_SUB && 463 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 464 return std::make_pair(Type3, -Val); 465 error(getErrorLocation(Loc) + "unsupported relocations combination " + 466 Twine(Type)); 467 return std::make_pair(Type & 0xff, Val); 468 } 469 470 template <class ELFT> 471 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 472 const endianness E = ELFT::TargetEndianness; 473 474 // Thread pointer and DRP offsets from the start of TLS data area. 475 // https://www.linux-mips.org/wiki/NPTL 476 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 477 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 478 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 479 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 480 Val -= 0x8000; 481 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 482 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 483 Type == R_MICROMIPS_TLS_TPREL_HI16 || 484 Type == R_MICROMIPS_TLS_TPREL_LO16) { 485 Val -= 0x7000; 486 } 487 488 if (ELFT::Is64Bits || Config->MipsN32Abi) 489 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 490 491 switch (Type) { 492 case R_MIPS_32: 493 case R_MIPS_GPREL32: 494 case R_MIPS_TLS_DTPREL32: 495 case R_MIPS_TLS_TPREL32: 496 write32<E>(Loc, Val); 497 break; 498 case R_MIPS_64: 499 case R_MIPS_TLS_DTPREL64: 500 case R_MIPS_TLS_TPREL64: 501 write64<E>(Loc, Val); 502 break; 503 case R_MIPS_26: 504 writeRelocation<E>(Loc, Val, 26, 2); 505 break; 506 case R_MIPS_GOT16: 507 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 508 // is updated addend (not a GOT index). In that case write high 16 bits 509 // to store a correct addend value. 510 if (Config->Relocatable) { 511 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 512 } else { 513 checkInt<16>(Loc, Val, Type); 514 writeRelocation<E>(Loc, Val, 16, 0); 515 } 516 break; 517 case R_MICROMIPS_GOT16: 518 if (Config->Relocatable) { 519 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 520 } else { 521 checkInt<16>(Loc, Val, Type); 522 writeMicroRelocation32<E>(Loc, Val, 16, 0); 523 } 524 break; 525 case R_MIPS_CALL16: 526 case R_MIPS_GOT_DISP: 527 case R_MIPS_GOT_PAGE: 528 case R_MIPS_GPREL16: 529 case R_MIPS_TLS_GD: 530 case R_MIPS_TLS_GOTTPREL: 531 case R_MIPS_TLS_LDM: 532 checkInt<16>(Loc, Val, Type); 533 LLVM_FALLTHROUGH; 534 case R_MIPS_CALL_LO16: 535 case R_MIPS_GOT_LO16: 536 case R_MIPS_GOT_OFST: 537 case R_MIPS_LO16: 538 case R_MIPS_PCLO16: 539 case R_MIPS_TLS_DTPREL_LO16: 540 case R_MIPS_TLS_TPREL_LO16: 541 writeRelocation<E>(Loc, Val, 16, 0); 542 break; 543 case R_MICROMIPS_GOT_DISP: 544 case R_MICROMIPS_GOT_PAGE: 545 case R_MICROMIPS_GPREL16: 546 case R_MICROMIPS_TLS_GD: 547 case R_MICROMIPS_TLS_LDM: 548 checkInt<16>(Loc, Val, Type); 549 writeMicroRelocation32<E>(Loc, Val, 16, 0); 550 break; 551 case R_MICROMIPS_CALL16: 552 case R_MICROMIPS_CALL_LO16: 553 case R_MICROMIPS_GOT_OFST: 554 case R_MICROMIPS_LO16: 555 case R_MICROMIPS_TLS_DTPREL_LO16: 556 case R_MICROMIPS_TLS_GOTTPREL: 557 case R_MICROMIPS_TLS_TPREL_LO16: 558 writeMicroRelocation32<E>(Loc, Val, 16, 0); 559 break; 560 case R_MICROMIPS_GPREL7_S2: 561 checkInt<7>(Loc, Val, Type); 562 writeMicroRelocation32<E>(Loc, Val, 7, 2); 563 break; 564 case R_MIPS_CALL_HI16: 565 case R_MIPS_GOT_HI16: 566 case R_MIPS_HI16: 567 case R_MIPS_PCHI16: 568 case R_MIPS_TLS_DTPREL_HI16: 569 case R_MIPS_TLS_TPREL_HI16: 570 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 571 break; 572 case R_MICROMIPS_CALL_HI16: 573 case R_MICROMIPS_GOT_HI16: 574 case R_MICROMIPS_HI16: 575 case R_MICROMIPS_TLS_DTPREL_HI16: 576 case R_MICROMIPS_TLS_TPREL_HI16: 577 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 578 break; 579 case R_MIPS_HIGHER: 580 writeRelocation<E>(Loc, Val + 0x80008000, 16, 32); 581 break; 582 case R_MIPS_HIGHEST: 583 writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48); 584 break; 585 case R_MICROMIPS_HIGHER: 586 writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32); 587 break; 588 case R_MICROMIPS_HIGHEST: 589 writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48); 590 break; 591 case R_MIPS_JALR: 592 case R_MICROMIPS_JALR: 593 // Ignore this optimization relocation for now 594 break; 595 case R_MIPS_PC16: 596 checkAlignment<4>(Loc, Val, Type); 597 checkInt<18>(Loc, Val, Type); 598 writeRelocation<E>(Loc, Val, 16, 2); 599 break; 600 case R_MIPS_PC19_S2: 601 checkAlignment<4>(Loc, Val, Type); 602 checkInt<21>(Loc, Val, Type); 603 writeRelocation<E>(Loc, Val, 19, 2); 604 break; 605 case R_MIPS_PC21_S2: 606 checkAlignment<4>(Loc, Val, Type); 607 checkInt<23>(Loc, Val, Type); 608 writeRelocation<E>(Loc, Val, 21, 2); 609 break; 610 case R_MIPS_PC26_S2: 611 checkAlignment<4>(Loc, Val, Type); 612 checkInt<28>(Loc, Val, Type); 613 writeRelocation<E>(Loc, Val, 26, 2); 614 break; 615 case R_MIPS_PC32: 616 writeRelocation<E>(Loc, Val, 32, 0); 617 break; 618 case R_MICROMIPS_26_S1: 619 case R_MICROMIPS_PC26_S1: 620 checkInt<27>(Loc, Val, Type); 621 writeMicroRelocation32<E>(Loc, Val, 26, 1); 622 break; 623 case R_MICROMIPS_PC7_S1: 624 checkInt<8>(Loc, Val, Type); 625 writeMicroRelocation16<E>(Loc, Val, 7, 1); 626 break; 627 case R_MICROMIPS_PC10_S1: 628 checkInt<11>(Loc, Val, Type); 629 writeMicroRelocation16<E>(Loc, Val, 10, 1); 630 break; 631 case R_MICROMIPS_PC16_S1: 632 checkInt<17>(Loc, Val, Type); 633 writeMicroRelocation32<E>(Loc, Val, 16, 1); 634 break; 635 case R_MICROMIPS_PC18_S3: 636 checkInt<21>(Loc, Val, Type); 637 writeMicroRelocation32<E>(Loc, Val, 18, 3); 638 break; 639 case R_MICROMIPS_PC19_S2: 640 checkInt<21>(Loc, Val, Type); 641 writeMicroRelocation32<E>(Loc, Val, 19, 2); 642 break; 643 case R_MICROMIPS_PC21_S1: 644 checkInt<22>(Loc, Val, Type); 645 writeMicroRelocation32<E>(Loc, Val, 21, 1); 646 break; 647 case R_MICROMIPS_PC23_S2: 648 checkInt<25>(Loc, Val, Type); 649 writeMicroRelocation32<E>(Loc, Val, 23, 2); 650 break; 651 default: 652 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 653 } 654 } 655 656 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 657 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 658 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 659 } 660 661 // Return true if the symbol is a PIC function. 662 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) { 663 typedef typename ELFT::Ehdr Elf_Ehdr; 664 if (!Sym->Section || !Sym->isFunc()) 665 return false; 666 667 auto *Sec = cast<InputSectionBase>(Sym->Section); 668 const Elf_Ehdr *Hdr = Sec->template getFile<ELFT>()->getObj().getHeader(); 669 return (Sym->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC || 670 (Hdr->e_flags & EF_MIPS_PIC); 671 } 672 673 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 674 static MIPS<ELFT> Target; 675 return &Target; 676 } 677 678 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 679 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 680 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 681 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 682 683 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 684 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 685 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 686 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 687