1 //===- MIPS.cpp -----------------------------------------------------------===//
2 //
3 // The LLVM Linker
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "InputFiles.h"
11 #include "OutputSections.h"
12 #include "Symbols.h"
13 #include "SyntheticSections.h"
14 #include "Target.h"
15 #include "Thunks.h"
16 #include "lld/Common/ErrorHandler.h"
17 #include "llvm/Object/ELF.h"
18 #include "llvm/Support/Endian.h"
19
20 using namespace llvm;
21 using namespace llvm::object;
22 using namespace llvm::support::endian;
23 using namespace llvm::ELF;
24 using namespace lld;
25 using namespace lld::elf;
26
27 namespace {
28 template <class ELFT> class MIPS final : public TargetInfo {
29 public:
30 MIPS();
31 uint32_t calcEFlags() const override;
32 RelExpr getRelExpr(RelType Type, const Symbol &S,
33 const uint8_t *Loc) const override;
34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
35 RelType getDynRel(RelType Type) const override;
36 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
37 void writePltHeader(uint8_t *Buf) const override;
38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
39 int32_t Index, unsigned RelOff) const override;
40 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
41 uint64_t BranchAddr, const Symbol &S) const override;
42 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
43 bool usesOnlyLowPageBits(RelType Type) const override;
44 };
45 } // namespace
46
MIPS()47 template <class ELFT> MIPS<ELFT>::MIPS() {
48 GotPltHeaderEntriesNum = 2;
49 DefaultMaxPageSize = 65536;
50 GotEntrySize = sizeof(typename ELFT::uint);
51 GotPltEntrySize = sizeof(typename ELFT::uint);
52 GotBaseSymInGotPlt = false;
53 PltEntrySize = 16;
54 PltHeaderSize = 32;
55 CopyRel = R_MIPS_COPY;
56 NoneRel = R_MIPS_NONE;
57 PltRel = R_MIPS_JUMP_SLOT;
58 NeedsThunks = true;
59
60 // Set `sigrie 1` as a trap instruction.
61 write32(TrapInstr.data(), 0x04170001);
62
63 if (ELFT::Is64Bits) {
64 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65 TlsGotRel = R_MIPS_TLS_TPREL64;
66 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67 TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68 } else {
69 RelativeRel = R_MIPS_REL32;
70 TlsGotRel = R_MIPS_TLS_TPREL32;
71 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
72 TlsOffsetRel = R_MIPS_TLS_DTPREL32;
73 }
74 }
75
calcEFlags() const76 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77 return calcMipsEFlags<ELFT>();
78 }
79
80 template <class ELFT>
getRelExpr(RelType Type,const Symbol & S,const uint8_t * Loc) const81 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S,
82 const uint8_t *Loc) const {
83 // See comment in the calculateMipsRelChain.
84 if (ELFT::Is64Bits || Config->MipsN32Abi)
85 Type &= 0xff;
86
87 switch (Type) {
88 case R_MIPS_JALR:
89 case R_MICROMIPS_JALR:
90 return R_HINT;
91 case R_MIPS_GPREL16:
92 case R_MIPS_GPREL32:
93 case R_MICROMIPS_GPREL16:
94 case R_MICROMIPS_GPREL7_S2:
95 return R_MIPS_GOTREL;
96 case R_MIPS_26:
97 case R_MICROMIPS_26_S1:
98 return R_PLT;
99 case R_MICROMIPS_PC26_S1:
100 return R_PLT_PC;
101 case R_MIPS_HI16:
102 case R_MIPS_LO16:
103 case R_MIPS_HIGHER:
104 case R_MIPS_HIGHEST:
105 case R_MICROMIPS_HI16:
106 case R_MICROMIPS_LO16:
107 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
108 // offset between start of function and 'gp' value which by default
109 // equal to the start of .got section. In that case we consider these
110 // relocations as relative.
111 if (&S == ElfSym::MipsGpDisp)
112 return R_MIPS_GOT_GP_PC;
113 if (&S == ElfSym::MipsLocalGp)
114 return R_MIPS_GOT_GP;
115 LLVM_FALLTHROUGH;
116 case R_MIPS_32:
117 case R_MIPS_64:
118 case R_MIPS_GOT_OFST:
119 case R_MIPS_SUB:
120 case R_MIPS_TLS_DTPREL_HI16:
121 case R_MIPS_TLS_DTPREL_LO16:
122 case R_MIPS_TLS_DTPREL32:
123 case R_MIPS_TLS_DTPREL64:
124 case R_MIPS_TLS_TPREL_HI16:
125 case R_MIPS_TLS_TPREL_LO16:
126 case R_MIPS_TLS_TPREL32:
127 case R_MIPS_TLS_TPREL64:
128 case R_MICROMIPS_TLS_DTPREL_HI16:
129 case R_MICROMIPS_TLS_DTPREL_LO16:
130 case R_MICROMIPS_TLS_TPREL_HI16:
131 case R_MICROMIPS_TLS_TPREL_LO16:
132 return R_ABS;
133 case R_MIPS_PC32:
134 case R_MIPS_PC16:
135 case R_MIPS_PC19_S2:
136 case R_MIPS_PC21_S2:
137 case R_MIPS_PC26_S2:
138 case R_MIPS_PCHI16:
139 case R_MIPS_PCLO16:
140 case R_MICROMIPS_PC7_S1:
141 case R_MICROMIPS_PC10_S1:
142 case R_MICROMIPS_PC16_S1:
143 case R_MICROMIPS_PC18_S3:
144 case R_MICROMIPS_PC19_S2:
145 case R_MICROMIPS_PC23_S2:
146 case R_MICROMIPS_PC21_S1:
147 return R_PC;
148 case R_MIPS_GOT16:
149 case R_MICROMIPS_GOT16:
150 if (S.isLocal())
151 return R_MIPS_GOT_LOCAL_PAGE;
152 LLVM_FALLTHROUGH;
153 case R_MIPS_CALL16:
154 case R_MIPS_GOT_DISP:
155 case R_MIPS_TLS_GOTTPREL:
156 case R_MICROMIPS_CALL16:
157 case R_MICROMIPS_TLS_GOTTPREL:
158 return R_MIPS_GOT_OFF;
159 case R_MIPS_CALL_HI16:
160 case R_MIPS_CALL_LO16:
161 case R_MIPS_GOT_HI16:
162 case R_MIPS_GOT_LO16:
163 case R_MICROMIPS_CALL_HI16:
164 case R_MICROMIPS_CALL_LO16:
165 case R_MICROMIPS_GOT_HI16:
166 case R_MICROMIPS_GOT_LO16:
167 return R_MIPS_GOT_OFF32;
168 case R_MIPS_GOT_PAGE:
169 return R_MIPS_GOT_LOCAL_PAGE;
170 case R_MIPS_TLS_GD:
171 case R_MICROMIPS_TLS_GD:
172 return R_MIPS_TLSGD;
173 case R_MIPS_TLS_LDM:
174 case R_MICROMIPS_TLS_LDM:
175 return R_MIPS_TLSLD;
176 case R_MIPS_NONE:
177 return R_NONE;
178 default:
179 return R_INVALID;
180 }
181 }
182
getDynRel(RelType Type) const183 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
184 if (Type == R_MIPS_32 || Type == R_MIPS_64)
185 return RelativeRel;
186 return R_MIPS_NONE;
187 }
188
189 template <class ELFT>
writeGotPlt(uint8_t * Buf,const Symbol &) const190 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
191 uint64_t VA = In.Plt->getVA();
192 if (isMicroMips())
193 VA |= 1;
194 write32<ELFT::TargetEndianness>(Buf, VA);
195 }
196
readShuffle(const uint8_t * Loc)197 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
198 // The major opcode of a microMIPS instruction needs to appear
199 // in the first 16-bit word (lowest address) for efficient hardware
200 // decode so that it knows if the instruction is 16-bit or 32-bit
201 // as early as possible. To do so, little-endian binaries keep 16-bit
202 // words in a big-endian order. That is why we have to swap these
203 // words to get a correct value.
204 uint32_t V = read32<E>(Loc);
205 if (E == support::little)
206 return (V << 16) | (V >> 16);
207 return V;
208 }
209
210 template <endianness E>
writeValue(uint8_t * Loc,uint64_t V,uint8_t BitsSize,uint8_t Shift)211 static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
212 uint8_t Shift) {
213 uint32_t Instr = read32<E>(Loc);
214 uint32_t Mask = 0xffffffff >> (32 - BitsSize);
215 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
216 write32<E>(Loc, Data);
217 }
218
219 template <endianness E>
writeShuffleValue(uint8_t * Loc,uint64_t V,uint8_t BitsSize,uint8_t Shift)220 static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
221 uint8_t Shift) {
222 // See comments in readShuffle for purpose of this code.
223 uint16_t *Words = (uint16_t *)Loc;
224 if (E == support::little)
225 std::swap(Words[0], Words[1]);
226
227 writeValue<E>(Loc, V, BitsSize, Shift);
228
229 if (E == support::little)
230 std::swap(Words[0], Words[1]);
231 }
232
233 template <endianness E>
writeMicroRelocation16(uint8_t * Loc,uint64_t V,uint8_t BitsSize,uint8_t Shift)234 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
235 uint8_t Shift) {
236 uint16_t Instr = read16<E>(Loc);
237 uint16_t Mask = 0xffff >> (16 - BitsSize);
238 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
239 write16<E>(Loc, Data);
240 }
241
writePltHeader(uint8_t * Buf) const242 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
243 const endianness E = ELFT::TargetEndianness;
244 if (isMicroMips()) {
245 uint64_t GotPlt = In.GotPlt->getVA();
246 uint64_t Plt = In.Plt->getVA();
247 // Overwrite trap instructions written by Writer::writeTrapInstr.
248 memset(Buf, 0, PltHeaderSize);
249
250 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - .
251 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3)
252 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3
253 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2
254 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2
255 write16<E>(Buf + 14, 0xfffe);
256 write16<E>(Buf + 16, 0x0dff); // move $15, $31
257 if (isMipsR6()) {
258 write16<E>(Buf + 18, 0x0f83); // move $28, $3
259 write16<E>(Buf + 20, 0x472b); // jalrc $25
260 write16<E>(Buf + 22, 0x0c00); // nop
261 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
262 } else {
263 write16<E>(Buf + 18, 0x45f9); // jalrc $25
264 write16<E>(Buf + 20, 0x0f83); // move $28, $3
265 write16<E>(Buf + 22, 0x0c00); // nop
266 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
267 }
268 return;
269 }
270
271 if (Config->MipsN32Abi) {
272 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
273 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
274 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
275 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
276 write32<E>(Buf + 16, 0x03e07825); // move $15, $31
277 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
278 } else if (ELFT::Is64Bits) {
279 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
280 write32<E>(Buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14)
281 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
282 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
283 write32<E>(Buf + 16, 0x03e07825); // move $15, $31
284 write32<E>(Buf + 20, 0x0018c0c2); // srl $24, $24, 3
285 } else {
286 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
287 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
288 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
289 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
290 write32<E>(Buf + 16, 0x03e07825); // move $15, $31
291 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
292 }
293
294 uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
295 write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
296 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
297
298 uint64_t GotPlt = In.GotPlt->getVA();
299 writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
300 writeValue<E>(Buf + 4, GotPlt, 16, 0);
301 writeValue<E>(Buf + 8, GotPlt, 16, 0);
302 }
303
304 template <class ELFT>
writePlt(uint8_t * Buf,uint64_t GotPltEntryAddr,uint64_t PltEntryAddr,int32_t Index,unsigned RelOff) const305 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
306 uint64_t PltEntryAddr, int32_t Index,
307 unsigned RelOff) const {
308 const endianness E = ELFT::TargetEndianness;
309 if (isMicroMips()) {
310 // Overwrite trap instructions written by Writer::writeTrapInstr.
311 memset(Buf, 0, PltEntrySize);
312
313 if (isMipsR6()) {
314 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - .
315 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2)
316 write16<E>(Buf + 8, 0x0f02); // move $24, $2
317 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
318 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
319 } else {
320 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - .
321 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2)
322 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25
323 write16<E>(Buf + 10, 0x0f02); // move $24, $2
324 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
325 }
326 return;
327 }
328
329 uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009)
330 : (Config->ZHazardplt ? 0x03200408 : 0x03200008);
331
332 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
333 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
334 write32<E>(Buf + 8, JrInst); // jr $25 / jr.hb $25
335 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
336 writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
337 writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
338 writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
339 }
340
341 template <class ELFT>
needsThunk(RelExpr Expr,RelType Type,const InputFile * File,uint64_t BranchAddr,const Symbol & S) const342 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
343 uint64_t BranchAddr, const Symbol &S) const {
344 // Any MIPS PIC code function is invoked with its address in register $t9.
345 // So if we have a branch instruction from non-PIC code to the PIC one
346 // we cannot make the jump directly and need to create a small stubs
347 // to save the target function address.
348 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
349 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 &&
350 Type != R_MICROMIPS_PC26_S1)
351 return false;
352 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
353 if (!F)
354 return false;
355 // If current file has PIC code, LA25 stub is not required.
356 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
357 return false;
358 auto *D = dyn_cast<Defined>(&S);
359 // LA25 is required if target file has PIC code
360 // or target symbol is a PIC symbol.
361 return D && isMipsPIC<ELFT>(D);
362 }
363
364 template <class ELFT>
getImplicitAddend(const uint8_t * Buf,RelType Type) const365 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
366 const endianness E = ELFT::TargetEndianness;
367 switch (Type) {
368 case R_MIPS_32:
369 case R_MIPS_GPREL32:
370 case R_MIPS_TLS_DTPREL32:
371 case R_MIPS_TLS_TPREL32:
372 return SignExtend64<32>(read32<E>(Buf));
373 case R_MIPS_26:
374 // FIXME (simon): If the relocation target symbol is not a PLT entry
375 // we should use another expression for calculation:
376 // ((A << 2) | (P & 0xf0000000)) >> 2
377 return SignExtend64<28>(read32<E>(Buf) << 2);
378 case R_MIPS_GOT16:
379 case R_MIPS_HI16:
380 case R_MIPS_PCHI16:
381 return SignExtend64<16>(read32<E>(Buf)) << 16;
382 case R_MIPS_GPREL16:
383 case R_MIPS_LO16:
384 case R_MIPS_PCLO16:
385 case R_MIPS_TLS_DTPREL_HI16:
386 case R_MIPS_TLS_DTPREL_LO16:
387 case R_MIPS_TLS_TPREL_HI16:
388 case R_MIPS_TLS_TPREL_LO16:
389 return SignExtend64<16>(read32<E>(Buf));
390 case R_MICROMIPS_GOT16:
391 case R_MICROMIPS_HI16:
392 return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
393 case R_MICROMIPS_GPREL16:
394 case R_MICROMIPS_LO16:
395 case R_MICROMIPS_TLS_DTPREL_HI16:
396 case R_MICROMIPS_TLS_DTPREL_LO16:
397 case R_MICROMIPS_TLS_TPREL_HI16:
398 case R_MICROMIPS_TLS_TPREL_LO16:
399 return SignExtend64<16>(readShuffle<E>(Buf));
400 case R_MICROMIPS_GPREL7_S2:
401 return SignExtend64<9>(readShuffle<E>(Buf) << 2);
402 case R_MIPS_PC16:
403 return SignExtend64<18>(read32<E>(Buf) << 2);
404 case R_MIPS_PC19_S2:
405 return SignExtend64<21>(read32<E>(Buf) << 2);
406 case R_MIPS_PC21_S2:
407 return SignExtend64<23>(read32<E>(Buf) << 2);
408 case R_MIPS_PC26_S2:
409 return SignExtend64<28>(read32<E>(Buf) << 2);
410 case R_MIPS_PC32:
411 return SignExtend64<32>(read32<E>(Buf));
412 case R_MICROMIPS_26_S1:
413 return SignExtend64<27>(readShuffle<E>(Buf) << 1);
414 case R_MICROMIPS_PC7_S1:
415 return SignExtend64<8>(read16<E>(Buf) << 1);
416 case R_MICROMIPS_PC10_S1:
417 return SignExtend64<11>(read16<E>(Buf) << 1);
418 case R_MICROMIPS_PC16_S1:
419 return SignExtend64<17>(readShuffle<E>(Buf) << 1);
420 case R_MICROMIPS_PC18_S3:
421 return SignExtend64<21>(readShuffle<E>(Buf) << 3);
422 case R_MICROMIPS_PC19_S2:
423 return SignExtend64<21>(readShuffle<E>(Buf) << 2);
424 case R_MICROMIPS_PC21_S1:
425 return SignExtend64<22>(readShuffle<E>(Buf) << 1);
426 case R_MICROMIPS_PC23_S2:
427 return SignExtend64<25>(readShuffle<E>(Buf) << 2);
428 case R_MICROMIPS_PC26_S1:
429 return SignExtend64<27>(readShuffle<E>(Buf) << 1);
430 default:
431 return 0;
432 }
433 }
434
435 static std::pair<uint32_t, uint64_t>
calculateMipsRelChain(uint8_t * Loc,RelType Type,uint64_t Val)436 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
437 // MIPS N64 ABI packs multiple relocations into the single relocation
438 // record. In general, all up to three relocations can have arbitrary
439 // types. In fact, Clang and GCC uses only a few combinations. For now,
440 // we support two of them. That is allow to pass at least all LLVM
441 // test suite cases.
442 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
443 // <any relocation> / R_MIPS_64 / R_MIPS_NONE
444 // The first relocation is a 'real' relocation which is calculated
445 // using the corresponding symbol's value. The second and the third
446 // relocations used to modify result of the first one: extend it to
447 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
448 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
449 RelType Type2 = (Type >> 8) & 0xff;
450 RelType Type3 = (Type >> 16) & 0xff;
451 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
452 return std::make_pair(Type, Val);
453 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
454 return std::make_pair(Type2, Val);
455 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
456 return std::make_pair(Type3, -Val);
457 error(getErrorLocation(Loc) + "unsupported relocations combination " +
458 Twine(Type));
459 return std::make_pair(Type & 0xff, Val);
460 }
461
462 template <class ELFT>
relocateOne(uint8_t * Loc,RelType Type,uint64_t Val) const463 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
464 const endianness E = ELFT::TargetEndianness;
465
466 if (ELFT::Is64Bits || Config->MipsN32Abi)
467 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
468
469 // Thread pointer and DRP offsets from the start of TLS data area.
470 // https://www.linux-mips.org/wiki/NPTL
471 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
472 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
473 Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
474 Type == R_MICROMIPS_TLS_DTPREL_LO16) {
475 Val -= 0x8000;
476 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
477 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
478 Type == R_MICROMIPS_TLS_TPREL_HI16 ||
479 Type == R_MICROMIPS_TLS_TPREL_LO16) {
480 Val -= 0x7000;
481 }
482
483 switch (Type) {
484 case R_MIPS_32:
485 case R_MIPS_GPREL32:
486 case R_MIPS_TLS_DTPREL32:
487 case R_MIPS_TLS_TPREL32:
488 write32<E>(Loc, Val);
489 break;
490 case R_MIPS_64:
491 case R_MIPS_TLS_DTPREL64:
492 case R_MIPS_TLS_TPREL64:
493 write64<E>(Loc, Val);
494 break;
495 case R_MIPS_26:
496 writeValue<E>(Loc, Val, 26, 2);
497 break;
498 case R_MIPS_GOT16:
499 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
500 // is updated addend (not a GOT index). In that case write high 16 bits
501 // to store a correct addend value.
502 if (Config->Relocatable) {
503 writeValue<E>(Loc, Val + 0x8000, 16, 16);
504 } else {
505 checkInt(Loc, Val, 16, Type);
506 writeValue<E>(Loc, Val, 16, 0);
507 }
508 break;
509 case R_MICROMIPS_GOT16:
510 if (Config->Relocatable) {
511 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
512 } else {
513 checkInt(Loc, Val, 16, Type);
514 writeShuffleValue<E>(Loc, Val, 16, 0);
515 }
516 break;
517 case R_MIPS_CALL16:
518 case R_MIPS_GOT_DISP:
519 case R_MIPS_GOT_PAGE:
520 case R_MIPS_GPREL16:
521 case R_MIPS_TLS_GD:
522 case R_MIPS_TLS_GOTTPREL:
523 case R_MIPS_TLS_LDM:
524 checkInt(Loc, Val, 16, Type);
525 LLVM_FALLTHROUGH;
526 case R_MIPS_CALL_LO16:
527 case R_MIPS_GOT_LO16:
528 case R_MIPS_GOT_OFST:
529 case R_MIPS_LO16:
530 case R_MIPS_PCLO16:
531 case R_MIPS_TLS_DTPREL_LO16:
532 case R_MIPS_TLS_TPREL_LO16:
533 writeValue<E>(Loc, Val, 16, 0);
534 break;
535 case R_MICROMIPS_GPREL16:
536 case R_MICROMIPS_TLS_GD:
537 case R_MICROMIPS_TLS_LDM:
538 checkInt(Loc, Val, 16, Type);
539 writeShuffleValue<E>(Loc, Val, 16, 0);
540 break;
541 case R_MICROMIPS_CALL16:
542 case R_MICROMIPS_CALL_LO16:
543 case R_MICROMIPS_LO16:
544 case R_MICROMIPS_TLS_DTPREL_LO16:
545 case R_MICROMIPS_TLS_GOTTPREL:
546 case R_MICROMIPS_TLS_TPREL_LO16:
547 writeShuffleValue<E>(Loc, Val, 16, 0);
548 break;
549 case R_MICROMIPS_GPREL7_S2:
550 checkInt(Loc, Val, 7, Type);
551 writeShuffleValue<E>(Loc, Val, 7, 2);
552 break;
553 case R_MIPS_CALL_HI16:
554 case R_MIPS_GOT_HI16:
555 case R_MIPS_HI16:
556 case R_MIPS_PCHI16:
557 case R_MIPS_TLS_DTPREL_HI16:
558 case R_MIPS_TLS_TPREL_HI16:
559 writeValue<E>(Loc, Val + 0x8000, 16, 16);
560 break;
561 case R_MICROMIPS_CALL_HI16:
562 case R_MICROMIPS_GOT_HI16:
563 case R_MICROMIPS_HI16:
564 case R_MICROMIPS_TLS_DTPREL_HI16:
565 case R_MICROMIPS_TLS_TPREL_HI16:
566 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
567 break;
568 case R_MIPS_HIGHER:
569 writeValue<E>(Loc, Val + 0x80008000, 16, 32);
570 break;
571 case R_MIPS_HIGHEST:
572 writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
573 break;
574 case R_MIPS_JALR:
575 case R_MICROMIPS_JALR:
576 // Ignore this optimization relocation for now
577 break;
578 case R_MIPS_PC16:
579 checkAlignment(Loc, Val, 4, Type);
580 checkInt(Loc, Val, 18, Type);
581 writeValue<E>(Loc, Val, 16, 2);
582 break;
583 case R_MIPS_PC19_S2:
584 checkAlignment(Loc, Val, 4, Type);
585 checkInt(Loc, Val, 21, Type);
586 writeValue<E>(Loc, Val, 19, 2);
587 break;
588 case R_MIPS_PC21_S2:
589 checkAlignment(Loc, Val, 4, Type);
590 checkInt(Loc, Val, 23, Type);
591 writeValue<E>(Loc, Val, 21, 2);
592 break;
593 case R_MIPS_PC26_S2:
594 checkAlignment(Loc, Val, 4, Type);
595 checkInt(Loc, Val, 28, Type);
596 writeValue<E>(Loc, Val, 26, 2);
597 break;
598 case R_MIPS_PC32:
599 writeValue<E>(Loc, Val, 32, 0);
600 break;
601 case R_MICROMIPS_26_S1:
602 case R_MICROMIPS_PC26_S1:
603 checkInt(Loc, Val, 27, Type);
604 writeShuffleValue<E>(Loc, Val, 26, 1);
605 break;
606 case R_MICROMIPS_PC7_S1:
607 checkInt(Loc, Val, 8, Type);
608 writeMicroRelocation16<E>(Loc, Val, 7, 1);
609 break;
610 case R_MICROMIPS_PC10_S1:
611 checkInt(Loc, Val, 11, Type);
612 writeMicroRelocation16<E>(Loc, Val, 10, 1);
613 break;
614 case R_MICROMIPS_PC16_S1:
615 checkInt(Loc, Val, 17, Type);
616 writeShuffleValue<E>(Loc, Val, 16, 1);
617 break;
618 case R_MICROMIPS_PC18_S3:
619 checkInt(Loc, Val, 21, Type);
620 writeShuffleValue<E>(Loc, Val, 18, 3);
621 break;
622 case R_MICROMIPS_PC19_S2:
623 checkInt(Loc, Val, 21, Type);
624 writeShuffleValue<E>(Loc, Val, 19, 2);
625 break;
626 case R_MICROMIPS_PC21_S1:
627 checkInt(Loc, Val, 22, Type);
628 writeShuffleValue<E>(Loc, Val, 21, 1);
629 break;
630 case R_MICROMIPS_PC23_S2:
631 checkInt(Loc, Val, 25, Type);
632 writeShuffleValue<E>(Loc, Val, 23, 2);
633 break;
634 default:
635 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
636 }
637 }
638
usesOnlyLowPageBits(RelType Type) const639 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
640 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
641 Type == R_MICROMIPS_LO16;
642 }
643
644 // Return true if the symbol is a PIC function.
isMipsPIC(const Defined * Sym)645 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
646 if (!Sym->isFunc())
647 return false;
648
649 if (Sym->StOther & STO_MIPS_PIC)
650 return true;
651
652 if (!Sym->Section)
653 return false;
654
655 ObjFile<ELFT> *File =
656 cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
657 if (!File)
658 return false;
659
660 return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
661 }
662
getMipsTargetInfo()663 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664 static MIPS<ELFT> Target;
665 return &Target;
666 }
667
668 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
669 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
670 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
671 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
672
673 template bool elf::isMipsPIC<ELF32LE>(const Defined *);
674 template bool elf::isMipsPIC<ELF32BE>(const Defined *);
675 template bool elf::isMipsPIC<ELF64LE>(const Defined *);
676 template bool elf::isMipsPIC<ELF64BE>(const Defined *);
677