1 //===- ARM.cpp ------------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/ErrorHandler.h" 16 #include "llvm/Object/ELF.h" 17 #include "llvm/Support/Endian.h" 18 19 using namespace llvm; 20 using namespace llvm::support::endian; 21 using namespace llvm::ELF; 22 using namespace lld; 23 using namespace lld::elf; 24 25 namespace { 26 class ARM final : public TargetInfo { 27 public: 28 ARM(); 29 uint32_t calcEFlags() const override; 30 RelExpr getRelExpr(RelType Type, const Symbol &S, 31 const uint8_t *Loc) const override; 32 bool isPicRel(RelType Type) const override; 33 RelType getDynRel(RelType Type) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 36 void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 void addPltSymbols(InputSection &IS, uint64_t Off) const override; 41 void addPltHeaderSymbols(InputSection &ISD) const override; 42 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 43 uint64_t BranchAddr, const Symbol &S) const override; 44 bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override; 45 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 46 }; 47 } // namespace 48 49 ARM::ARM() { 50 CopyRel = R_ARM_COPY; 51 RelativeRel = R_ARM_RELATIVE; 52 IRelativeRel = R_ARM_IRELATIVE; 53 GotRel = R_ARM_GLOB_DAT; 54 PltRel = R_ARM_JUMP_SLOT; 55 TlsGotRel = R_ARM_TLS_TPOFF32; 56 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 57 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 58 GotEntrySize = 4; 59 GotPltEntrySize = 4; 60 PltEntrySize = 16; 61 PltHeaderSize = 32; 62 TrapInstr = 0xd4d4d4d4; 63 // ARM uses Variant 1 TLS 64 TcbSize = 8; 65 NeedsThunks = true; 66 67 // The placing of pre-created ThunkSections is controlled by the 68 // ThunkSectionSpacing parameter. The aim is to place the 69 // ThunkSection such that all branches from the InputSections prior to the 70 // ThunkSection can reach a Thunk placed at the end of the ThunkSection. 71 // Graphically: 72 // | up to ThunkSectionSpacing .text input sections | 73 // | ThunkSection | 74 // | up to ThunkSectionSpacing .text input sections | 75 // | ThunkSection | 76 77 // Pre-created ThunkSections are spaced roughly 16MiB apart on ARM. This is to 78 // match the most common expected case of a Thumb 2 encoded BL, BLX or B.W 79 // ARM B, BL, BLX range +/- 32MiB 80 // Thumb B.W, BL, BLX range +/- 16MiB 81 // Thumb B<cc>.W range +/- 1MiB 82 // If a branch cannot reach a pre-created ThunkSection a new one will be 83 // created so we can handle the rare cases of a Thumb 2 conditional branch. 84 // We intentionally use a lower size for ThunkSectionSpacing than the maximum 85 // branch range so the end of the ThunkSection is more likely to be within 86 // range of the branch instruction that is furthest away. The value we shorten 87 // ThunkSectionSpacing by is set conservatively to allow us to create 16,384 88 // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to 89 // one of the Thunks going out of range. 90 91 // FIXME: lld assumes that the Thumb BL and BLX encoding permits the J1 and 92 // J2 bits to be used to extend the branch range. On earlier Architectures 93 // such as ARMv4, ARMv5 and ARMv6 (except ARMv6T2) the range is +/- 4MiB. If 94 // support for the earlier encodings is added then when they are used the 95 // ThunkSectionSpacing will need lowering. 96 ThunkSectionSpacing = 0x1000000 - 0x30000; 97 } 98 99 uint32_t ARM::calcEFlags() const { 100 // The ABIFloatType is used by loaders to detect the floating point calling 101 // convention. 102 uint32_t ABIFloatType = 0; 103 if (Config->ARMVFPArgs == ARMVFPArgKind::Base || 104 Config->ARMVFPArgs == ARMVFPArgKind::Default) 105 ABIFloatType = EF_ARM_ABI_FLOAT_SOFT; 106 else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP) 107 ABIFloatType = EF_ARM_ABI_FLOAT_HARD; 108 109 // We don't currently use any features incompatible with EF_ARM_EABI_VER5, 110 // but we don't have any firm guarantees of conformance. Linux AArch64 111 // kernels (as of 2016) require an EABI version to be set. 112 return EF_ARM_EABI_VER5 | ABIFloatType; 113 } 114 115 RelExpr ARM::getRelExpr(RelType Type, const Symbol &S, 116 const uint8_t *Loc) const { 117 switch (Type) { 118 case R_ARM_THM_JUMP11: 119 return R_PC; 120 case R_ARM_CALL: 121 case R_ARM_JUMP24: 122 case R_ARM_PC24: 123 case R_ARM_PLT32: 124 case R_ARM_PREL31: 125 case R_ARM_THM_JUMP19: 126 case R_ARM_THM_JUMP24: 127 case R_ARM_THM_CALL: 128 return R_PLT_PC; 129 case R_ARM_GOTOFF32: 130 // (S + A) - GOT_ORG 131 return R_GOTREL; 132 case R_ARM_GOT_BREL: 133 // GOT(S) + A - GOT_ORG 134 return R_GOT_OFF; 135 case R_ARM_GOT_PREL: 136 case R_ARM_TLS_IE32: 137 // GOT(S) + A - P 138 return R_GOT_PC; 139 case R_ARM_SBREL32: 140 return R_ARM_SBREL; 141 case R_ARM_TARGET1: 142 return Config->Target1Rel ? R_PC : R_ABS; 143 case R_ARM_TARGET2: 144 if (Config->Target2 == Target2Policy::Rel) 145 return R_PC; 146 if (Config->Target2 == Target2Policy::Abs) 147 return R_ABS; 148 return R_GOT_PC; 149 case R_ARM_TLS_GD32: 150 return R_TLSGD_PC; 151 case R_ARM_TLS_LDM32: 152 return R_TLSLD_PC; 153 case R_ARM_BASE_PREL: 154 // B(S) + A - P 155 // FIXME: currently B(S) assumed to be .got, this may not hold for all 156 // platforms. 157 return R_GOTONLY_PC; 158 case R_ARM_MOVW_PREL_NC: 159 case R_ARM_MOVT_PREL: 160 case R_ARM_REL32: 161 case R_ARM_THM_MOVW_PREL_NC: 162 case R_ARM_THM_MOVT_PREL: 163 return R_PC; 164 case R_ARM_NONE: 165 return R_NONE; 166 case R_ARM_TLS_LE32: 167 return R_TLS; 168 default: 169 return R_ABS; 170 } 171 } 172 173 bool ARM::isPicRel(RelType Type) const { 174 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 175 (Type == R_ARM_ABS32); 176 } 177 178 RelType ARM::getDynRel(RelType Type) const { 179 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 180 return R_ARM_ABS32; 181 if (Type == R_ARM_ABS32) 182 return Type; 183 // Keep it going with a dummy value so that we can find more reloc errors. 184 return R_ARM_ABS32; 185 } 186 187 void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const { 188 write32le(Buf, InX::Plt->getVA()); 189 } 190 191 void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const { 192 // An ARM entry is the address of the ifunc resolver function. 193 write32le(Buf, S.getVA()); 194 } 195 196 // Long form PLT Header that does not have any restrictions on the displacement 197 // of the .plt from the .plt.got. 198 static void writePltHeaderLong(uint8_t *Buf) { 199 const uint8_t PltData[] = { 200 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 201 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 202 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 203 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 204 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 205 0xd4, 0xd4, 0xd4, 0xd4, // Pad to 32-byte boundary 206 0xd4, 0xd4, 0xd4, 0xd4, // Pad to 32-byte boundary 207 0xd4, 0xd4, 0xd4, 0xd4}; 208 memcpy(Buf, PltData, sizeof(PltData)); 209 uint64_t GotPlt = InX::GotPlt->getVA(); 210 uint64_t L1 = InX::Plt->getVA() + 8; 211 write32le(Buf + 16, GotPlt - L1 - 8); 212 } 213 214 // The default PLT header requires the .plt.got to be within 128 Mb of the 215 // .plt in the positive direction. 216 void ARM::writePltHeader(uint8_t *Buf) const { 217 // Use a similar sequence to that in writePlt(), the difference is the calling 218 // conventions mean we use lr instead of ip. The PLT entry is responsible for 219 // saving lr on the stack, the dynamic loader is responsible for reloading 220 // it. 221 const uint32_t PltData[] = { 222 0xe52de004, // L1: str lr, [sp,#-4]! 223 0xe28fe600, // add lr, pc, #0x0NN00000 &(.got.plt - L1 - 4) 224 0xe28eea00, // add lr, lr, #0x000NN000 &(.got.plt - L1 - 4) 225 0xe5bef000, // ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4) 226 }; 227 228 uint64_t Offset = InX::GotPlt->getVA() - InX::Plt->getVA() - 4; 229 if (!llvm::isUInt<27>(Offset)) { 230 // We cannot encode the Offset, use the long form. 231 writePltHeaderLong(Buf); 232 return; 233 } 234 write32le(Buf + 0, PltData[0]); 235 write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff)); 236 write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff)); 237 write32le(Buf + 12, PltData[3] | (Offset & 0xfff)); 238 write32le(Buf + 16, TrapInstr); // Pad to 32-byte boundary 239 write32le(Buf + 20, TrapInstr); 240 write32le(Buf + 24, TrapInstr); 241 write32le(Buf + 28, TrapInstr); 242 } 243 244 void ARM::addPltHeaderSymbols(InputSection &IS) const { 245 addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS); 246 addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS); 247 } 248 249 // Long form PLT entries that do not have any restrictions on the displacement 250 // of the .plt from the .plt.got. 251 static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr, 252 uint64_t PltEntryAddr, int32_t Index, 253 unsigned RelOff) { 254 const uint8_t PltData[] = { 255 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 256 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 257 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 258 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 259 }; 260 memcpy(Buf, PltData, sizeof(PltData)); 261 uint64_t L1 = PltEntryAddr + 4; 262 write32le(Buf + 12, GotPltEntryAddr - L1 - 8); 263 } 264 265 // The default PLT entries require the .plt.got to be within 128 Mb of the 266 // .plt in the positive direction. 267 void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 268 uint64_t PltEntryAddr, int32_t Index, 269 unsigned RelOff) const { 270 // The PLT entry is similar to the example given in Appendix A of ELF for 271 // the Arm Architecture. Instead of using the Group Relocations to find the 272 // optimal rotation for the 8-bit immediate used in the add instructions we 273 // hard code the most compact rotations for simplicity. This saves a load 274 // instruction over the long plt sequences. 275 const uint32_t PltData[] = { 276 0xe28fc600, // L1: add ip, pc, #0x0NN00000 Offset(&(.plt.got) - L1 - 8 277 0xe28cca00, // add ip, ip, #0x000NN000 Offset(&(.plt.got) - L1 - 8 278 0xe5bcf000, // ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8 279 }; 280 281 uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8; 282 if (!llvm::isUInt<27>(Offset)) { 283 // We cannot encode the Offset, use the long form. 284 writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff); 285 return; 286 } 287 write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff)); 288 write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff)); 289 write32le(Buf + 8, PltData[2] | (Offset & 0xfff)); 290 write32le(Buf + 12, TrapInstr); // Pad to 16-byte boundary 291 } 292 293 void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const { 294 addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS); 295 addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS); 296 } 297 298 bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 299 uint64_t BranchAddr, const Symbol &S) const { 300 // If S is an undefined weak symbol and does not have a PLT entry then it 301 // will be resolved as a branch to the next instruction. 302 if (S.isUndefWeak() && !S.isInPlt()) 303 return false; 304 // A state change from ARM to Thumb and vice versa must go through an 305 // interworking thunk if the relocation type is not R_ARM_CALL or 306 // R_ARM_THM_CALL. 307 switch (Type) { 308 case R_ARM_PC24: 309 case R_ARM_PLT32: 310 case R_ARM_JUMP24: 311 // Source is ARM, all PLT entries are ARM so no interworking required. 312 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 313 if (Expr == R_PC && ((S.getVA() & 1) == 1)) 314 return true; 315 LLVM_FALLTHROUGH; 316 case R_ARM_CALL: { 317 uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA(); 318 return !inBranchRange(Type, BranchAddr, Dst); 319 } 320 case R_ARM_THM_JUMP19: 321 case R_ARM_THM_JUMP24: 322 // Source is Thumb, all PLT entries are ARM so interworking is required. 323 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 324 if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0)) 325 return true; 326 LLVM_FALLTHROUGH; 327 case R_ARM_THM_CALL: { 328 uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA(); 329 return !inBranchRange(Type, BranchAddr, Dst); 330 } 331 } 332 return false; 333 } 334 335 bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const { 336 uint64_t Range; 337 uint64_t InstrSize; 338 339 switch (Type) { 340 case R_ARM_PC24: 341 case R_ARM_PLT32: 342 case R_ARM_JUMP24: 343 case R_ARM_CALL: 344 Range = 0x2000000; 345 InstrSize = 4; 346 break; 347 case R_ARM_THM_JUMP19: 348 Range = 0x100000; 349 InstrSize = 2; 350 break; 351 case R_ARM_THM_JUMP24: 352 case R_ARM_THM_CALL: 353 Range = 0x1000000; 354 InstrSize = 2; 355 break; 356 default: 357 return true; 358 } 359 // PC at Src is 2 instructions ahead, immediate of branch is signed 360 if (Src > Dst) 361 Range -= 2 * InstrSize; 362 else 363 Range += InstrSize; 364 365 if ((Dst & 0x1) == 0) 366 // Destination is ARM, if ARM caller then Src is already 4-byte aligned. 367 // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure 368 // destination will be 4 byte aligned. 369 Src &= ~0x3; 370 else 371 // Bit 0 == 1 denotes Thumb state, it is not part of the range 372 Dst &= ~0x1; 373 374 uint64_t Distance = (Src > Dst) ? Src - Dst : Dst - Src; 375 return Distance <= Range; 376 } 377 378 void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 379 switch (Type) { 380 case R_ARM_ABS32: 381 case R_ARM_BASE_PREL: 382 case R_ARM_GLOB_DAT: 383 case R_ARM_GOTOFF32: 384 case R_ARM_GOT_BREL: 385 case R_ARM_GOT_PREL: 386 case R_ARM_REL32: 387 case R_ARM_RELATIVE: 388 case R_ARM_SBREL32: 389 case R_ARM_TARGET1: 390 case R_ARM_TARGET2: 391 case R_ARM_TLS_GD32: 392 case R_ARM_TLS_IE32: 393 case R_ARM_TLS_LDM32: 394 case R_ARM_TLS_LDO32: 395 case R_ARM_TLS_LE32: 396 case R_ARM_TLS_TPOFF32: 397 case R_ARM_TLS_DTPOFF32: 398 write32le(Loc, Val); 399 break; 400 case R_ARM_TLS_DTPMOD32: 401 write32le(Loc, 1); 402 break; 403 case R_ARM_PREL31: 404 checkInt<31>(Loc, Val, Type); 405 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 406 break; 407 case R_ARM_CALL: 408 // R_ARM_CALL is used for BL and BLX instructions, depending on the 409 // value of bit 0 of Val, we must select a BL or BLX instruction 410 if (Val & 1) { 411 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 412 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 413 checkInt<26>(Loc, Val, Type); 414 write32le(Loc, 0xfa000000 | // opcode 415 ((Val & 2) << 23) | // H 416 ((Val >> 2) & 0x00ffffff)); // imm24 417 break; 418 } 419 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 420 // BLX (always unconditional) instruction to an ARM Target, select an 421 // unconditional BL. 422 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 423 // fall through as BL encoding is shared with B 424 LLVM_FALLTHROUGH; 425 case R_ARM_JUMP24: 426 case R_ARM_PC24: 427 case R_ARM_PLT32: 428 checkInt<26>(Loc, Val, Type); 429 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 430 break; 431 case R_ARM_THM_JUMP11: 432 checkInt<12>(Loc, Val, Type); 433 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 434 break; 435 case R_ARM_THM_JUMP19: 436 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 437 checkInt<21>(Loc, Val, Type); 438 write16le(Loc, 439 (read16le(Loc) & 0xfbc0) | // opcode cond 440 ((Val >> 10) & 0x0400) | // S 441 ((Val >> 12) & 0x003f)); // imm6 442 write16le(Loc + 2, 443 0x8000 | // opcode 444 ((Val >> 8) & 0x0800) | // J2 445 ((Val >> 5) & 0x2000) | // J1 446 ((Val >> 1) & 0x07ff)); // imm11 447 break; 448 case R_ARM_THM_CALL: 449 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 450 // value of bit 0 of Val, we must select a BL or BLX instruction 451 if ((Val & 1) == 0) { 452 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 453 // only be two byte aligned. This must be done before overflow check 454 Val = alignTo(Val, 4); 455 } 456 // Bit 12 is 0 for BLX, 1 for BL 457 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 458 // Fall through as rest of encoding is the same as B.W 459 LLVM_FALLTHROUGH; 460 case R_ARM_THM_JUMP24: 461 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 462 // FIXME: Use of I1 and I2 require v6T2ops 463 checkInt<25>(Loc, Val, Type); 464 write16le(Loc, 465 0xf000 | // opcode 466 ((Val >> 14) & 0x0400) | // S 467 ((Val >> 12) & 0x03ff)); // imm10 468 write16le(Loc + 2, 469 (read16le(Loc + 2) & 0xd000) | // opcode 470 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 471 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 472 ((Val >> 1) & 0x07ff)); // imm11 473 break; 474 case R_ARM_MOVW_ABS_NC: 475 case R_ARM_MOVW_PREL_NC: 476 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 477 (Val & 0x0fff)); 478 break; 479 case R_ARM_MOVT_ABS: 480 case R_ARM_MOVT_PREL: 481 checkInt<32>(Loc, Val, Type); 482 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 483 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 484 break; 485 case R_ARM_THM_MOVT_ABS: 486 case R_ARM_THM_MOVT_PREL: 487 // Encoding T1: A = imm4:i:imm3:imm8 488 checkInt<32>(Loc, Val, Type); 489 write16le(Loc, 490 0xf2c0 | // opcode 491 ((Val >> 17) & 0x0400) | // i 492 ((Val >> 28) & 0x000f)); // imm4 493 write16le(Loc + 2, 494 (read16le(Loc + 2) & 0x8f00) | // opcode 495 ((Val >> 12) & 0x7000) | // imm3 496 ((Val >> 16) & 0x00ff)); // imm8 497 break; 498 case R_ARM_THM_MOVW_ABS_NC: 499 case R_ARM_THM_MOVW_PREL_NC: 500 // Encoding T3: A = imm4:i:imm3:imm8 501 write16le(Loc, 502 0xf240 | // opcode 503 ((Val >> 1) & 0x0400) | // i 504 ((Val >> 12) & 0x000f)); // imm4 505 write16le(Loc + 2, 506 (read16le(Loc + 2) & 0x8f00) | // opcode 507 ((Val << 4) & 0x7000) | // imm3 508 (Val & 0x00ff)); // imm8 509 break; 510 default: 511 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 512 } 513 } 514 515 int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 516 switch (Type) { 517 default: 518 return 0; 519 case R_ARM_ABS32: 520 case R_ARM_BASE_PREL: 521 case R_ARM_GOTOFF32: 522 case R_ARM_GOT_BREL: 523 case R_ARM_GOT_PREL: 524 case R_ARM_REL32: 525 case R_ARM_TARGET1: 526 case R_ARM_TARGET2: 527 case R_ARM_TLS_GD32: 528 case R_ARM_TLS_LDM32: 529 case R_ARM_TLS_LDO32: 530 case R_ARM_TLS_IE32: 531 case R_ARM_TLS_LE32: 532 return SignExtend64<32>(read32le(Buf)); 533 case R_ARM_PREL31: 534 return SignExtend64<31>(read32le(Buf)); 535 case R_ARM_CALL: 536 case R_ARM_JUMP24: 537 case R_ARM_PC24: 538 case R_ARM_PLT32: 539 return SignExtend64<26>(read32le(Buf) << 2); 540 case R_ARM_THM_JUMP11: 541 return SignExtend64<12>(read16le(Buf) << 1); 542 case R_ARM_THM_JUMP19: { 543 // Encoding T3: A = S:J2:J1:imm10:imm6:0 544 uint16_t Hi = read16le(Buf); 545 uint16_t Lo = read16le(Buf + 2); 546 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 547 ((Lo & 0x0800) << 8) | // J2 548 ((Lo & 0x2000) << 5) | // J1 549 ((Hi & 0x003f) << 12) | // imm6 550 ((Lo & 0x07ff) << 1)); // imm11:0 551 } 552 case R_ARM_THM_CALL: 553 case R_ARM_THM_JUMP24: { 554 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 555 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 556 // FIXME: I1 and I2 require v6T2ops 557 uint16_t Hi = read16le(Buf); 558 uint16_t Lo = read16le(Buf + 2); 559 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 560 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 561 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 562 ((Hi & 0x003ff) << 12) | // imm0 563 ((Lo & 0x007ff) << 1)); // imm11:0 564 } 565 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 566 // MOVT is in the range -32768 <= A < 32768 567 case R_ARM_MOVW_ABS_NC: 568 case R_ARM_MOVT_ABS: 569 case R_ARM_MOVW_PREL_NC: 570 case R_ARM_MOVT_PREL: { 571 uint64_t Val = read32le(Buf) & 0x000f0fff; 572 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 573 } 574 case R_ARM_THM_MOVW_ABS_NC: 575 case R_ARM_THM_MOVT_ABS: 576 case R_ARM_THM_MOVW_PREL_NC: 577 case R_ARM_THM_MOVT_PREL: { 578 // Encoding T3: A = imm4:i:imm3:imm8 579 uint16_t Hi = read16le(Buf); 580 uint16_t Lo = read16le(Buf + 2); 581 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 582 ((Hi & 0x0400) << 1) | // i 583 ((Lo & 0x7000) >> 4) | // imm3 584 (Lo & 0x00ff)); // imm8 585 } 586 } 587 } 588 589 TargetInfo *elf::getARMTargetInfo() { 590 static ARM Target; 591 return &Target; 592 } 593