1 //===--- Mips.cpp - Implement Mips target feature support -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements Mips TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Mips.h"
15 #include "Targets.h"
16 #include "clang/Basic/Diagnostic.h"
17 #include "clang/Basic/MacroBuilder.h"
18 #include "clang/Basic/TargetBuiltins.h"
19 #include "llvm/ADT/StringSwitch.h"
20
21 using namespace clang;
22 using namespace clang::targets;
23
24 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
25 #define BUILTIN(ID, TYPE, ATTRS) \
26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
27 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
28 {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
29 #include "clang/Basic/BuiltinsMips.def"
30 };
31
processorSupportsGPR64() const32 bool MipsTargetInfo::processorSupportsGPR64() const {
33 return llvm::StringSwitch<bool>(CPU)
34 .Case("mips3", true)
35 .Case("mips4", true)
36 .Case("mips5", true)
37 .Case("mips64", true)
38 .Case("mips64r2", true)
39 .Case("mips64r3", true)
40 .Case("mips64r5", true)
41 .Case("mips64r6", true)
42 .Case("octeon", true)
43 .Default(false);
44 return false;
45 }
46
47 static constexpr llvm::StringLiteral ValidCPUNames[] = {
48 {"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
49 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
50 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
51 {"octeon"}, {"p5600"}};
52
isValidCPUName(StringRef Name) const53 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
54 return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
55 }
56
fillValidCPUList(SmallVectorImpl<StringRef> & Values) const57 void MipsTargetInfo::fillValidCPUList(
58 SmallVectorImpl<StringRef> &Values) const {
59 Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
60 }
61
getISARev() const62 unsigned MipsTargetInfo::getISARev() const {
63 return llvm::StringSwitch<unsigned>(getCPU())
64 .Cases("mips32", "mips64", 1)
65 .Cases("mips32r2", "mips64r2", 2)
66 .Cases("mips32r3", "mips64r3", 3)
67 .Cases("mips32r5", "mips64r5", 5)
68 .Cases("mips32r6", "mips64r6", 6)
69 .Default(0);
70 }
71
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const72 void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
73 MacroBuilder &Builder) const {
74 if (BigEndian) {
75 DefineStd(Builder, "MIPSEB", Opts);
76 Builder.defineMacro("_MIPSEB");
77 } else {
78 DefineStd(Builder, "MIPSEL", Opts);
79 Builder.defineMacro("_MIPSEL");
80 }
81
82 Builder.defineMacro("__mips__");
83 Builder.defineMacro("_mips");
84 if (Opts.GNUMode)
85 Builder.defineMacro("mips");
86
87 if (ABI == "o32") {
88 Builder.defineMacro("__mips", "32");
89 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
90 } else {
91 Builder.defineMacro("__mips", "64");
92 Builder.defineMacro("__mips64");
93 Builder.defineMacro("__mips64__");
94 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
95 }
96
97 const std::string ISARev = std::to_string(getISARev());
98
99 if (!ISARev.empty())
100 Builder.defineMacro("__mips_isa_rev", ISARev);
101
102 if (ABI == "o32") {
103 Builder.defineMacro("__mips_o32");
104 Builder.defineMacro("_ABIO32", "1");
105 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
106 } else if (ABI == "n32") {
107 Builder.defineMacro("__mips_n32");
108 Builder.defineMacro("_ABIN32", "2");
109 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
110 } else if (ABI == "n64") {
111 Builder.defineMacro("__mips_n64");
112 Builder.defineMacro("_ABI64", "3");
113 Builder.defineMacro("_MIPS_SIM", "_ABI64");
114 } else
115 llvm_unreachable("Invalid ABI.");
116
117 if (!IsNoABICalls) {
118 Builder.defineMacro("__mips_abicalls");
119 if (CanUseBSDABICalls)
120 Builder.defineMacro("__ABICALLS__");
121 }
122
123 Builder.defineMacro("__REGISTER_PREFIX__", "");
124
125 switch (FloatABI) {
126 case HardFloat:
127 Builder.defineMacro("__mips_hard_float", Twine(1));
128 break;
129 case SoftFloat:
130 Builder.defineMacro("__mips_soft_float", Twine(1));
131 break;
132 }
133
134 if (IsSingleFloat)
135 Builder.defineMacro("__mips_single_float", Twine(1));
136
137 switch (FPMode) {
138 case FPXX:
139 Builder.defineMacro("__mips_fpr", Twine(0));
140 break;
141 case FP32:
142 Builder.defineMacro("__mips_fpr", Twine(32));
143 break;
144 case FP64:
145 Builder.defineMacro("__mips_fpr", Twine(64));
146 break;
147 }
148
149 if (FPMode == FP64 || IsSingleFloat)
150 Builder.defineMacro("_MIPS_FPSET", Twine(32));
151 else
152 Builder.defineMacro("_MIPS_FPSET", Twine(16));
153
154 if (IsMips16)
155 Builder.defineMacro("__mips16", Twine(1));
156
157 if (IsMicromips)
158 Builder.defineMacro("__mips_micromips", Twine(1));
159
160 if (IsNan2008)
161 Builder.defineMacro("__mips_nan2008", Twine(1));
162
163 if (IsAbs2008)
164 Builder.defineMacro("__mips_abs2008", Twine(1));
165
166 switch (DspRev) {
167 default:
168 break;
169 case DSP1:
170 Builder.defineMacro("__mips_dsp_rev", Twine(1));
171 Builder.defineMacro("__mips_dsp", Twine(1));
172 break;
173 case DSP2:
174 Builder.defineMacro("__mips_dsp_rev", Twine(2));
175 Builder.defineMacro("__mips_dspr2", Twine(1));
176 Builder.defineMacro("__mips_dsp", Twine(1));
177 break;
178 }
179
180 if (HasMSA)
181 Builder.defineMacro("__mips_msa", Twine(1));
182
183 if (DisableMadd4)
184 Builder.defineMacro("__mips_no_madd4", Twine(1));
185
186 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
187 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
188 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
189
190 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
191 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
192
193 // These shouldn't be defined for MIPS-I but there's no need to check
194 // for that since MIPS-I isn't supported.
195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
198
199 // 32-bit MIPS processors don't have the necessary lld/scd instructions
200 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
201 // the instructions exist but using them violates the ABI since they
202 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
203 if (ABI == "n32" || ABI == "n64")
204 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
205 }
206
hasFeature(StringRef Feature) const207 bool MipsTargetInfo::hasFeature(StringRef Feature) const {
208 return llvm::StringSwitch<bool>(Feature)
209 .Case("mips", true)
210 .Case("fp64", FPMode == FP64)
211 .Default(false);
212 }
213
getTargetBuiltins() const214 ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
215 return llvm::makeArrayRef(BuiltinInfo, clang::Mips::LastTSBuiltin -
216 Builtin::FirstTSBuiltin);
217 }
218
validateTarget(DiagnosticsEngine & Diags) const219 bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
220 // microMIPS64R6 backend was removed.
221 if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
222 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
223 return false;
224 }
225 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
226 // this yet. It's better to fail here than on the backend assertion.
227 if (processorSupportsGPR64() && ABI == "o32") {
228 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
229 return false;
230 }
231
232 // 64-bit ABI's require 64-bit CPU's.
233 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
234 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
235 return false;
236 }
237
238 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
239 // can't handle this yet. It's better to fail here than on the
240 // backend assertion.
241 if (getTriple().isMIPS64() && ABI == "o32") {
242 Diags.Report(diag::err_target_unsupported_abi_for_triple)
243 << ABI << getTriple().str();
244 return false;
245 }
246
247 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
248 // can't handle this yet. It's better to fail here than on the
249 // backend assertion.
250 if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
251 Diags.Report(diag::err_target_unsupported_abi_for_triple)
252 << ABI << getTriple().str();
253 return false;
254 }
255
256 // -fpxx is valid only for the o32 ABI
257 if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
258 Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
259 return false;
260 }
261
262 // -mfp32 and n32/n64 ABIs are incompatible
263 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
264 (ABI == "n32" || ABI == "n64")) {
265 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
266 return false;
267 }
268 // Mips revision 6 and -mfp32 are incompatible
269 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
270 CPU == "mips64r6")) {
271 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
272 return false;
273 }
274 // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
275 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
276 getISARev() < 2) && ABI == "o32") {
277 Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
278 return false;
279 }
280
281 return true;
282 }
283