1//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// This is a target description file for the WebAssembly architecture, 12/// which is also known as "wasm". 13/// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Target-independent interfaces which we are implementing 18//===----------------------------------------------------------------------===// 19 20include "llvm/Target/Target.td" 21 22//===----------------------------------------------------------------------===// 23// WebAssembly Subtarget features. 24//===----------------------------------------------------------------------===// 25 26def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128", 27 "Enable 128-bit SIMD">; 28 29def FeatureUnimplementedSIMD128 : 30 SubtargetFeature<"unimplemented-simd128", 31 "SIMDLevel", "UnimplementedSIMD128", 32 "Enable 128-bit SIMD not yet implemented in engines", 33 [FeatureSIMD128]>; 34 35def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", 36 "Enable Atomics">; 37def FeatureNontrappingFPToInt : 38 SubtargetFeature<"nontrapping-fptoint", 39 "HasNontrappingFPToInt", "true", 40 "Enable non-trapping float-to-int conversion operators">; 41 42def FeatureSignExt : 43 SubtargetFeature<"sign-ext", 44 "HasSignExt", "true", 45 "Enable sign extension operators">; 46 47def FeatureExceptionHandling : 48 SubtargetFeature<"exception-handling", "HasExceptionHandling", "true", 49 "Enable Wasm exception handling">; 50 51//===----------------------------------------------------------------------===// 52// Architectures. 53//===----------------------------------------------------------------------===// 54 55//===----------------------------------------------------------------------===// 56// Register File Description 57//===----------------------------------------------------------------------===// 58 59include "WebAssemblyRegisterInfo.td" 60 61//===----------------------------------------------------------------------===// 62// Instruction Descriptions 63//===----------------------------------------------------------------------===// 64 65include "WebAssemblyInstrInfo.td" 66 67def WebAssemblyInstrInfo : InstrInfo; 68 69//===----------------------------------------------------------------------===// 70// WebAssembly Processors supported. 71//===----------------------------------------------------------------------===// 72 73// Minimal Viable Product. 74def : ProcessorModel<"mvp", NoSchedModel, []>; 75 76// Generic processor: latest stable version. 77def : ProcessorModel<"generic", NoSchedModel, []>; 78 79// Latest and greatest experimental version of WebAssembly. Bugs included! 80def : ProcessorModel<"bleeding-edge", NoSchedModel, 81 [FeatureSIMD128, FeatureAtomics, 82 FeatureNontrappingFPToInt, FeatureSignExt]>; 83 84//===----------------------------------------------------------------------===// 85// Target Declaration 86//===----------------------------------------------------------------------===// 87 88def WebAssemblyAsmParser : AsmParser { 89 // The physical register names are not in the binary format or asm text 90 let ShouldEmitMatchRegisterName = 0; 91} 92 93def WebAssemblyAsmWriter : AsmWriter { 94 string AsmWriterClassName = "InstPrinter"; 95 int PassSubtarget = 0; 96 int Variant = 0; 97 bit isMCAsmWriter = 1; 98} 99 100def WebAssembly : Target { 101 let InstructionSet = WebAssemblyInstrInfo; 102 let AssemblyParsers = [WebAssemblyAsmParser]; 103 let AssemblyWriters = [WebAssemblyAsmWriter]; 104} 105