1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This file provides RISCV-specific target descriptions.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "RISCVMCTargetDesc.h"
15 #include "InstPrinter/RISCVInstPrinter.h"
16 #include "RISCVELFStreamer.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVTargetStreamer.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27
28 #define GET_INSTRINFO_MC_DESC
29 #include "RISCVGenInstrInfo.inc"
30
31 #define GET_REGINFO_MC_DESC
32 #include "RISCVGenRegisterInfo.inc"
33
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "RISCVGenSubtargetInfo.inc"
36
37 using namespace llvm;
38
createRISCVMCInstrInfo()39 static MCInstrInfo *createRISCVMCInstrInfo() {
40 MCInstrInfo *X = new MCInstrInfo();
41 InitRISCVMCInstrInfo(X);
42 return X;
43 }
44
createRISCVMCRegisterInfo(const Triple & TT)45 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
46 MCRegisterInfo *X = new MCRegisterInfo();
47 InitRISCVMCRegisterInfo(X, RISCV::X1);
48 return X;
49 }
50
createRISCVMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT)51 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
52 const Triple &TT) {
53 return new RISCVMCAsmInfo(TT);
54 }
55
createRISCVMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)56 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
57 StringRef CPU, StringRef FS) {
58 std::string CPUName = CPU;
59 if (CPUName.empty())
60 CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
61 return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
62 }
63
createRISCVMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)64 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
65 unsigned SyntaxVariant,
66 const MCAsmInfo &MAI,
67 const MCInstrInfo &MII,
68 const MCRegisterInfo &MRI) {
69 return new RISCVInstPrinter(MAI, MII, MRI);
70 }
71
72 static MCTargetStreamer *
createRISCVObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)73 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
74 const Triple &TT = STI.getTargetTriple();
75 if (TT.isOSBinFormatELF())
76 return new RISCVTargetELFStreamer(S, STI);
77 return nullptr;
78 }
79
createRISCVAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint,bool isVerboseAsm)80 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
81 formatted_raw_ostream &OS,
82 MCInstPrinter *InstPrint,
83 bool isVerboseAsm) {
84 return new RISCVTargetAsmStreamer(S, OS);
85 }
86
LLVMInitializeRISCVTargetMC()87 extern "C" void LLVMInitializeRISCVTargetMC() {
88 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
89 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
90 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
91 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
92 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
93 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
94 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
95 TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
96 TargetRegistry::RegisterObjectTargetStreamer(
97 *T, createRISCVObjectTargetStreamer);
98
99 // Register the asm target streamer.
100 TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
101 }
102 }
103