1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Transforms/Scalar.h"
26 using namespace llvm;
27 
28 static cl::
29 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
30                         cl::desc("Disable CTR loops for PPC"));
31 
32 static cl::opt<bool>
33 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
34   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
35 
36 static cl::opt<bool>
37 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
38              cl::desc("Enable optimizations on complex GEPs"),
39              cl::init(true));
40 
41 extern "C" void LLVMInitializePowerPCTarget() {
42   // Register the targets
43   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
44   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
45   RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
46 }
47 
48 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
49   std::string FullFS = FS;
50   Triple TargetTriple(TT);
51 
52   // Make sure 64-bit features are available when CPUname is generic
53   if (TargetTriple.getArch() == Triple::ppc64 ||
54       TargetTriple.getArch() == Triple::ppc64le) {
55     if (!FullFS.empty())
56       FullFS = "+64bit," + FullFS;
57     else
58       FullFS = "+64bit";
59   }
60 
61   if (OL >= CodeGenOpt::Default) {
62     if (!FullFS.empty())
63       FullFS = "+crbits," + FullFS;
64     else
65       FullFS = "+crbits";
66   }
67   return FullFS;
68 }
69 
70 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
71   // If it isn't a Mach-O file then it's going to be a linux ELF
72   // object file.
73   if (TT.isOSDarwin())
74     return make_unique<TargetLoweringObjectFileMachO>();
75 
76   return make_unique<PPC64LinuxTargetObjectFile>();
77 }
78 
79 // The FeatureString here is a little subtle. We are modifying the feature string
80 // with what are (currently) non-function specific overrides as it goes into the
81 // LLVMTargetMachine constructor and then using the stored value in the
82 // Subtarget constructor below it.
83 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
84                                    StringRef FS, const TargetOptions &Options,
85                                    Reloc::Model RM, CodeModel::Model CM,
86                                    CodeGenOpt::Level OL)
87     : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
88                         CM, OL),
89       TLOF(createTLOF(Triple(getTargetTriple()))),
90       Subtarget(TT, CPU, TargetFS, *this) {
91   initAsmInfo();
92 }
93 
94 PPCTargetMachine::~PPCTargetMachine() {}
95 
96 void PPC32TargetMachine::anchor() { }
97 
98 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
99                                        StringRef CPU, StringRef FS,
100                                        const TargetOptions &Options,
101                                        Reloc::Model RM, CodeModel::Model CM,
102                                        CodeGenOpt::Level OL)
103   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
104 }
105 
106 void PPC64TargetMachine::anchor() { }
107 
108 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
109                                        StringRef CPU,  StringRef FS,
110                                        const TargetOptions &Options,
111                                        Reloc::Model RM, CodeModel::Model CM,
112                                        CodeGenOpt::Level OL)
113   : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
114 }
115 
116 const PPCSubtarget *
117 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
118   AttributeSet FnAttrs = F.getAttributes();
119   Attribute CPUAttr =
120       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
121   Attribute FSAttr =
122       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
123 
124   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
125                         ? CPUAttr.getValueAsString().str()
126                         : TargetCPU;
127   std::string FS = !FSAttr.hasAttribute(Attribute::None)
128                        ? FSAttr.getValueAsString().str()
129                        : TargetFS;
130 
131   auto &I = SubtargetMap[CPU + FS];
132   if (!I) {
133     // This needs to be done before we create a new subtarget since any
134     // creation will depend on the TM and the code generation flags on the
135     // function that reside in TargetOptions.
136     resetTargetOptions(F);
137     I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
138   }
139   return I.get();
140 }
141 
142 //===----------------------------------------------------------------------===//
143 // Pass Pipeline Configuration
144 //===----------------------------------------------------------------------===//
145 
146 namespace {
147 /// PPC Code Generator Pass Configuration Options.
148 class PPCPassConfig : public TargetPassConfig {
149 public:
150   PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
151     : TargetPassConfig(TM, PM) {}
152 
153   PPCTargetMachine &getPPCTargetMachine() const {
154     return getTM<PPCTargetMachine>();
155   }
156 
157   const PPCSubtarget &getPPCSubtarget() const {
158     return *getPPCTargetMachine().getSubtargetImpl();
159   }
160 
161   void addIRPasses() override;
162   bool addPreISel() override;
163   bool addILPOpts() override;
164   bool addInstSelector() override;
165   void addPreRegAlloc() override;
166   void addPreSched2() override;
167   void addPreEmitPass() override;
168 };
169 } // namespace
170 
171 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
172   return new PPCPassConfig(this, PM);
173 }
174 
175 void PPCPassConfig::addIRPasses() {
176   addPass(createAtomicExpandPass(&getPPCTargetMachine()));
177 
178   if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
179     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
180     // and lower a GEP with multiple indices to either arithmetic operations or
181     // multiple GEPs with single index.
182     addPass(createSeparateConstOffsetFromGEPPass(TM, true));
183     // Call EarlyCSE pass to find and remove subexpressions in the lowered
184     // result.
185     addPass(createEarlyCSEPass());
186     // Do loop invariant code motion in case part of the lowered result is
187     // invariant.
188     addPass(createLICMPass());
189   }
190 
191   TargetPassConfig::addIRPasses();
192 }
193 
194 bool PPCPassConfig::addPreISel() {
195   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
196     addPass(createPPCCTRLoops(getPPCTargetMachine()));
197 
198   return false;
199 }
200 
201 bool PPCPassConfig::addILPOpts() {
202   addPass(&EarlyIfConverterID);
203   return true;
204 }
205 
206 bool PPCPassConfig::addInstSelector() {
207   // Install an instruction selector.
208   addPass(createPPCISelDag(getPPCTargetMachine()));
209 
210 #ifndef NDEBUG
211   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
212     addPass(createPPCCTRLoopsVerify());
213 #endif
214 
215   addPass(createPPCVSXCopyPass());
216   return false;
217 }
218 
219 void PPCPassConfig::addPreRegAlloc() {
220   initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
221   insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
222              &PPCVSXFMAMutateID);
223 }
224 
225 void PPCPassConfig::addPreSched2() {
226   addPass(createPPCVSXCopyCleanupPass(), false);
227 
228   if (getOptLevel() != CodeGenOpt::None)
229     addPass(&IfConverterID);
230 }
231 
232 void PPCPassConfig::addPreEmitPass() {
233   if (getOptLevel() != CodeGenOpt::None)
234     addPass(createPPCEarlyReturnPass(), false);
235   // Must run branch selection immediately preceding the asm printer.
236   addPass(createPPCBranchSelectionPass(), false);
237 }
238 
239 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
240   // Add first the target-independent BasicTTI pass, then our PPC pass. This
241   // allows the PPC pass to delegate to the target independent layer when
242   // appropriate.
243   PM.add(createBasicTargetTransformInfoPass(this));
244   PM.add(createPPCTargetTransformInfoPass(this));
245 }
246 
247