1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCTargetMachine.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "PPC.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/CodeGen/MachineScheduler.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <memory>
40 #include <string>
41
42 using namespace llvm;
43
44
45 static cl::opt<bool>
46 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
47 cl::desc("enable coalescing of duplicate branches for PPC"));
48 static cl::
49 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
50 cl::desc("Disable CTR loops for PPC"));
51
52 static cl::
53 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
54 cl::desc("Disable PPC loop preinc prep"));
55
56 static cl::opt<bool>
57 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
58 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
59
60 static cl::
61 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
62 cl::desc("Disable VSX Swap Removal for PPC"));
63
64 static cl::
65 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
66 cl::desc("Disable QPX load splat simplification"));
67
68 static cl::
69 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
70 cl::desc("Disable machine peepholes for PPC"));
71
72 static cl::opt<bool>
73 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
74 cl::desc("Enable optimizations on complex GEPs"),
75 cl::init(true));
76
77 static cl::opt<bool>
78 EnablePrefetch("enable-ppc-prefetching",
79 cl::desc("disable software prefetching on PPC"),
80 cl::init(false), cl::Hidden);
81
82 static cl::opt<bool>
83 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
84 cl::desc("Add extra TOC register dependencies"),
85 cl::init(true), cl::Hidden);
86
87 static cl::opt<bool>
88 EnableMachineCombinerPass("ppc-machine-combiner",
89 cl::desc("Enable the machine combiner pass"),
90 cl::init(true), cl::Hidden);
91
92 static cl::opt<bool>
93 ReduceCRLogical("ppc-reduce-cr-logicals",
94 cl::desc("Expand eligible cr-logical binary ops to branches"),
95 cl::init(false), cl::Hidden);
LLVMInitializePowerPCTarget()96 extern "C" void LLVMInitializePowerPCTarget() {
97 // Register the targets
98 RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
99 RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
100 RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
101
102 PassRegistry &PR = *PassRegistry::getPassRegistry();
103 initializePPCBoolRetToIntPass(PR);
104 initializePPCExpandISELPass(PR);
105 initializePPCPreEmitPeepholePass(PR);
106 initializePPCTLSDynamicCallPass(PR);
107 initializePPCMIPeepholePass(PR);
108 }
109
110 /// Return the datalayout string of a subtarget.
getDataLayoutString(const Triple & T)111 static std::string getDataLayoutString(const Triple &T) {
112 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
113 std::string Ret;
114
115 // Most PPC* platforms are big endian, PPC64LE is little endian.
116 if (T.getArch() == Triple::ppc64le)
117 Ret = "e";
118 else
119 Ret = "E";
120
121 Ret += DataLayout::getManglingComponent(T);
122
123 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
124 // pointers.
125 if (!is64Bit || T.getOS() == Triple::Lv2)
126 Ret += "-p:32:32";
127
128 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
129 // documentation are wrong; these are correct (i.e. "what gcc does").
130 if (is64Bit || !T.isOSDarwin())
131 Ret += "-i64:64";
132 else
133 Ret += "-f64:32:64";
134
135 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
136 if (is64Bit)
137 Ret += "-n32:64";
138 else
139 Ret += "-n32";
140
141 return Ret;
142 }
143
computeFSAdditions(StringRef FS,CodeGenOpt::Level OL,const Triple & TT)144 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
145 const Triple &TT) {
146 std::string FullFS = FS;
147
148 // Make sure 64-bit features are available when CPUname is generic
149 if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
150 if (!FullFS.empty())
151 FullFS = "+64bit," + FullFS;
152 else
153 FullFS = "+64bit";
154 }
155
156 if (OL >= CodeGenOpt::Default) {
157 if (!FullFS.empty())
158 FullFS = "+crbits," + FullFS;
159 else
160 FullFS = "+crbits";
161 }
162
163 if (OL != CodeGenOpt::None) {
164 if (!FullFS.empty())
165 FullFS = "+invariant-function-descriptors," + FullFS;
166 else
167 FullFS = "+invariant-function-descriptors";
168 }
169
170 return FullFS;
171 }
172
createTLOF(const Triple & TT)173 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
174 // If it isn't a Mach-O file then it's going to be a linux ELF
175 // object file.
176 if (TT.isOSDarwin())
177 return llvm::make_unique<TargetLoweringObjectFileMachO>();
178
179 return llvm::make_unique<PPC64LinuxTargetObjectFile>();
180 }
181
computeTargetABI(const Triple & TT,const TargetOptions & Options)182 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
183 const TargetOptions &Options) {
184 if (TT.isOSDarwin())
185 report_fatal_error("Darwin is no longer supported for PowerPC");
186
187 if (Options.MCOptions.getABIName().startswith("elfv1"))
188 return PPCTargetMachine::PPC_ABI_ELFv1;
189 else if (Options.MCOptions.getABIName().startswith("elfv2"))
190 return PPCTargetMachine::PPC_ABI_ELFv2;
191
192 assert(Options.MCOptions.getABIName().empty() &&
193 "Unknown target-abi option!");
194
195 if (TT.isMacOSX())
196 return PPCTargetMachine::PPC_ABI_UNKNOWN;
197
198 switch (TT.getArch()) {
199 case Triple::ppc64le:
200 return PPCTargetMachine::PPC_ABI_ELFv2;
201 case Triple::ppc64:
202 return PPCTargetMachine::PPC_ABI_ELFv1;
203 default:
204 return PPCTargetMachine::PPC_ABI_UNKNOWN;
205 }
206 }
207
getEffectiveRelocModel(const Triple & TT,Optional<Reloc::Model> RM)208 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
209 Optional<Reloc::Model> RM) {
210 if (RM.hasValue())
211 return *RM;
212
213 // Darwin defaults to dynamic-no-pic.
214 if (TT.isOSDarwin())
215 return Reloc::DynamicNoPIC;
216
217 // Big Endian PPC is PIC by default.
218 if (TT.getArch() == Triple::ppc64)
219 return Reloc::PIC_;
220
221 // Rest are static by default.
222 return Reloc::Static;
223 }
224
getEffectivePPCCodeModel(const Triple & TT,Optional<CodeModel::Model> CM,bool JIT)225 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
226 Optional<CodeModel::Model> CM,
227 bool JIT) {
228 if (CM) {
229 if (*CM == CodeModel::Tiny)
230 report_fatal_error("Target does not support the tiny CodeModel");
231 if (*CM == CodeModel::Kernel)
232 report_fatal_error("Target does not support the kernel CodeModel");
233 return *CM;
234 }
235 if (!TT.isOSDarwin() && !JIT &&
236 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
237 return CodeModel::Medium;
238 return CodeModel::Small;
239 }
240
241 // The FeatureString here is a little subtle. We are modifying the feature
242 // string with what are (currently) non-function specific overrides as it goes
243 // into the LLVMTargetMachine constructor and then using the stored value in the
244 // Subtarget constructor below it.
PPCTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)245 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
246 StringRef CPU, StringRef FS,
247 const TargetOptions &Options,
248 Optional<Reloc::Model> RM,
249 Optional<CodeModel::Model> CM,
250 CodeGenOpt::Level OL, bool JIT)
251 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
252 computeFSAdditions(FS, OL, TT), Options,
253 getEffectiveRelocModel(TT, RM),
254 getEffectivePPCCodeModel(TT, CM, JIT), OL),
255 TLOF(createTLOF(getTargetTriple())),
256 TargetABI(computeTargetABI(TT, Options)) {
257 initAsmInfo();
258 }
259
260 PPCTargetMachine::~PPCTargetMachine() = default;
261
262 const PPCSubtarget *
getSubtargetImpl(const Function & F) const263 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
264 Attribute CPUAttr = F.getFnAttribute("target-cpu");
265 Attribute FSAttr = F.getFnAttribute("target-features");
266
267 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
268 ? CPUAttr.getValueAsString().str()
269 : TargetCPU;
270 std::string FS = !FSAttr.hasAttribute(Attribute::None)
271 ? FSAttr.getValueAsString().str()
272 : TargetFS;
273
274 // FIXME: This is related to the code below to reset the target options,
275 // we need to know whether or not the soft float flag is set on the
276 // function before we can generate a subtarget. We also need to use
277 // it as a key for the subtarget since that can be the only difference
278 // between two functions.
279 bool SoftFloat =
280 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
281 // If the soft float attribute is set on the function turn on the soft float
282 // subtarget feature.
283 if (SoftFloat)
284 FS += FS.empty() ? "-hard-float" : ",-hard-float";
285
286 auto &I = SubtargetMap[CPU + FS];
287 if (!I) {
288 // This needs to be done before we create a new subtarget since any
289 // creation will depend on the TM and the code generation flags on the
290 // function that reside in TargetOptions.
291 resetTargetOptions(F);
292 I = llvm::make_unique<PPCSubtarget>(
293 TargetTriple, CPU,
294 // FIXME: It would be good to have the subtarget additions here
295 // not necessary. Anything that turns them on/off (overrides) ends
296 // up being put at the end of the feature string, but the defaults
297 // shouldn't require adding them. Fixing this means pulling Feature64Bit
298 // out of most of the target cpus in the .td file and making it set only
299 // as part of initialization via the TargetTriple.
300 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
301 }
302 return I.get();
303 }
304
305 //===----------------------------------------------------------------------===//
306 // Pass Pipeline Configuration
307 //===----------------------------------------------------------------------===//
308
309 namespace {
310
311 /// PPC Code Generator Pass Configuration Options.
312 class PPCPassConfig : public TargetPassConfig {
313 public:
PPCPassConfig(PPCTargetMachine & TM,PassManagerBase & PM)314 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
315 : TargetPassConfig(TM, PM) {
316 // At any optimization level above -O0 we use the Machine Scheduler and not
317 // the default Post RA List Scheduler.
318 if (TM.getOptLevel() != CodeGenOpt::None)
319 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
320 }
321
getPPCTargetMachine() const322 PPCTargetMachine &getPPCTargetMachine() const {
323 return getTM<PPCTargetMachine>();
324 }
325
326 void addIRPasses() override;
327 bool addPreISel() override;
328 bool addILPOpts() override;
329 bool addInstSelector() override;
330 void addMachineSSAOptimization() override;
331 void addPreRegAlloc() override;
332 void addPreSched2() override;
333 void addPreEmitPass() override;
334 };
335
336 } // end anonymous namespace
337
createPassConfig(PassManagerBase & PM)338 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
339 return new PPCPassConfig(*this, PM);
340 }
341
addIRPasses()342 void PPCPassConfig::addIRPasses() {
343 if (TM->getOptLevel() != CodeGenOpt::None)
344 addPass(createPPCBoolRetToIntPass());
345 addPass(createAtomicExpandPass());
346
347 // For the BG/Q (or if explicitly requested), add explicit data prefetch
348 // intrinsics.
349 bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
350 getOptLevel() != CodeGenOpt::None;
351 if (EnablePrefetch.getNumOccurrences() > 0)
352 UsePrefetching = EnablePrefetch;
353 if (UsePrefetching)
354 addPass(createLoopDataPrefetchPass());
355
356 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
357 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
358 // and lower a GEP with multiple indices to either arithmetic operations or
359 // multiple GEPs with single index.
360 addPass(createSeparateConstOffsetFromGEPPass(true));
361 // Call EarlyCSE pass to find and remove subexpressions in the lowered
362 // result.
363 addPass(createEarlyCSEPass());
364 // Do loop invariant code motion in case part of the lowered result is
365 // invariant.
366 addPass(createLICMPass());
367 }
368
369 TargetPassConfig::addIRPasses();
370 }
371
addPreISel()372 bool PPCPassConfig::addPreISel() {
373 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
374 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
375
376 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
377 addPass(createPPCCTRLoops());
378
379 return false;
380 }
381
addILPOpts()382 bool PPCPassConfig::addILPOpts() {
383 addPass(&EarlyIfConverterID);
384
385 if (EnableMachineCombinerPass)
386 addPass(&MachineCombinerID);
387
388 return true;
389 }
390
addInstSelector()391 bool PPCPassConfig::addInstSelector() {
392 // Install an instruction selector.
393 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
394
395 #ifndef NDEBUG
396 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
397 addPass(createPPCCTRLoopsVerify());
398 #endif
399
400 addPass(createPPCVSXCopyPass());
401 return false;
402 }
403
addMachineSSAOptimization()404 void PPCPassConfig::addMachineSSAOptimization() {
405 // PPCBranchCoalescingPass need to be done before machine sinking
406 // since it merges empty blocks.
407 if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
408 addPass(createPPCBranchCoalescingPass());
409 TargetPassConfig::addMachineSSAOptimization();
410 // For little endian, remove where possible the vector swap instructions
411 // introduced at code generation to normalize vector element order.
412 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
413 !DisableVSXSwapRemoval)
414 addPass(createPPCVSXSwapRemovalPass());
415 // Reduce the number of cr-logical ops.
416 if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
417 addPass(createPPCReduceCRLogicalsPass());
418 // Target-specific peephole cleanups performed after instruction
419 // selection.
420 if (!DisableMIPeephole) {
421 addPass(createPPCMIPeepholePass());
422 addPass(&DeadMachineInstructionElimID);
423 }
424 }
425
addPreRegAlloc()426 void PPCPassConfig::addPreRegAlloc() {
427 if (getOptLevel() != CodeGenOpt::None) {
428 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
429 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
430 &PPCVSXFMAMutateID);
431 }
432
433 // FIXME: We probably don't need to run these for -fPIE.
434 if (getPPCTargetMachine().isPositionIndependent()) {
435 // FIXME: LiveVariables should not be necessary here!
436 // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
437 // LiveVariables. This (unnecessary) dependency has been removed now,
438 // however a stage-2 clang build fails without LiveVariables computed here.
439 addPass(&LiveVariablesID, false);
440 addPass(createPPCTLSDynamicCallPass());
441 }
442 if (EnableExtraTOCRegDeps)
443 addPass(createPPCTOCRegDepsPass());
444 }
445
addPreSched2()446 void PPCPassConfig::addPreSched2() {
447 if (getOptLevel() != CodeGenOpt::None) {
448 addPass(&IfConverterID);
449
450 // This optimization must happen after anything that might do store-to-load
451 // forwarding. Here we're after RA (and, thus, when spills are inserted)
452 // but before post-RA scheduling.
453 if (!DisableQPXLoadSplat)
454 addPass(createPPCQPXLoadSplatPass());
455 }
456 }
457
addPreEmitPass()458 void PPCPassConfig::addPreEmitPass() {
459 addPass(createPPCPreEmitPeepholePass());
460 addPass(createPPCExpandISELPass());
461
462 if (getOptLevel() != CodeGenOpt::None)
463 addPass(createPPCEarlyReturnPass(), false);
464 // Must run branch selection immediately preceding the asm printer.
465 addPass(createPPCBranchSelectionPass(), false);
466 }
467
468 TargetTransformInfo
getTargetTransformInfo(const Function & F)469 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
470 return TargetTransformInfo(PPCTTIImpl(this, F));
471 }
472