1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPC.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
21 using namespace llvm;
22 
23 // This is duplicated code. Refactor this.
24 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
25                                     MCContext &Ctx, TargetAsmBackend &TAB,
26                                     raw_ostream &OS,
27                                     MCCodeEmitter *Emitter,
28                                     bool RelaxAll,
29                                     bool NoExecStack) {
30   if (Triple(TT).isOSDarwin())
31     return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
32 
33   return NULL;
34 }
35 
36 extern "C" void LLVMInitializePowerPCTarget() {
37   // Register the targets
38   RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
39   RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
40 
41   // Register the MC Code Emitter
42   TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
43   TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
44 
45 
46   // Register the asm backend.
47   TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
48   TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
49 
50   // Register the object streamer.
51   TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
52   TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
53 }
54 
55 
56 PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
57                                    const std::string &CPU,
58                                    const std::string &FS, bool is64Bit)
59   : LLVMTargetMachine(T, TT, CPU, FS),
60     Subtarget(TT, CPU, FS, is64Bit),
61     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
62     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
63     TLInfo(*this), TSInfo(*this),
64     InstrItins(Subtarget.getInstrItineraryData()) {
65 
66   if (getRelocationModel() == Reloc::Default) {
67     if (Subtarget.isDarwin())
68       setRelocationModel(Reloc::DynamicNoPIC);
69     else
70       setRelocationModel(Reloc::Static);
71   }
72 }
73 
74 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue
75 /// groups, which typically degrades performance.
76 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
77 
78 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
79                                        const std::string &CPU,
80                                        const std::string &FS)
81   : PPCTargetMachine(T, TT, CPU, FS, false) {
82 }
83 
84 
85 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
86                                        const std::string &CPU,
87                                        const std::string &FS)
88   : PPCTargetMachine(T, TT, CPU, FS, true) {
89 }
90 
91 
92 //===----------------------------------------------------------------------===//
93 // Pass Pipeline Configuration
94 //===----------------------------------------------------------------------===//
95 
96 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
97                                        CodeGenOpt::Level OptLevel) {
98   // Install an instruction selector.
99   PM.add(createPPCISelDag(*this));
100   return false;
101 }
102 
103 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
104                                       CodeGenOpt::Level OptLevel) {
105   // Must run branch selection immediately preceding the asm printer.
106   PM.add(createPPCBranchSelectionPass());
107   return false;
108 }
109 
110 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
111                                       CodeGenOpt::Level OptLevel,
112                                       JITCodeEmitter &JCE) {
113   // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
114   // FIXME: This should be moved to TargetJITInfo!!
115   if (Subtarget.isPPC64()) {
116     // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
117     // instructions to materialize arbitrary global variable + function +
118     // constant pool addresses.
119     setRelocationModel(Reloc::PIC_);
120     // Temporary workaround for the inability of PPC64 JIT to handle jump
121     // tables.
122     DisableJumpTables = true;
123   } else {
124     setRelocationModel(Reloc::Static);
125   }
126 
127   // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
128   // writing?
129   Subtarget.SetJITMode();
130 
131   // Machine code emitter pass for PowerPC.
132   PM.add(createPPCJITCodeEmitterPass(*this, JCE));
133 
134   return false;
135 }
136