1//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the POWER9 processor.
11//
12//===----------------------------------------------------------------------===//
13include "PPCInstrInfo.td"
14
15def P9Model : SchedMachineModel {
16  // The maximum number of instructions to be issued at the same time.
17  // While a value of 8 is technically correct since 8 instructions can be
18  // fetched from the instruction cache. However, only 6 instructions may be
19  // actually dispatched at a time.
20  let IssueWidth = 8;
21
22  // Load latency is 4 or 5 cycles depending on the load. This latency assumes
23  // that we have a cache hit. For a cache miss the load latency will be more.
24  // There are two instructions (lxvl, lxvll) that have a latencty of 6 cycles.
25  // However it is not worth bumping this value up to 6 when the vast majority
26  // of instructions are 4 or 5 cycles.
27  let LoadLatency = 5;
28
29  // A total of 16 cycles to recover from a branch mispredict.
30  let MispredictPenalty = 16;
31
32  // Try to make sure we have at least 10 dispatch groups in a loop.
33  // A dispatch group is 6 instructions.
34  let LoopMicroOpBufferSize = 60;
35
36  // As iops are dispatched to a slice, they are held in an independent slice
37  // issue queue until all register sources and other dependencies have been
38  // resolved and they can be issued. Each of four execution slices has an
39  // 11-entry iop issue queue.
40  let MicroOpBufferSize = 44;
41
42  let CompleteModel = 1;
43
44  // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
45  // Engine) on Power 9.
46  let UnsupportedFeatures = [HasQPX, HasSPE];
47
48}
49
50let SchedModel = P9Model in {
51
52  // ***************** Processor Resources *****************
53
54  //Dispatcher:
55  def DISPATCHER : ProcResource<12>;
56
57  // Issue Ports
58  // An instruction can go down one of two issue queues.
59  // Address Generation (AGEN) mainly for loads and stores.
60  // Execution (EXEC) for most other instructions.
61  // Some instructions cannot be run on just any issue queue and may require an
62  // Even or an Odd queue. The EXECE represents the even queues and the EXECO
63  // represents the odd queues.
64  def IP_AGEN : ProcResource<4>;
65  def IP_EXEC : ProcResource<4>;
66  def IP_EXECE : ProcResource<2> {
67    //Even Exec Ports
68    let Super = IP_EXEC;
69  }
70  def IP_EXECO : ProcResource<2> {
71    //Odd Exec Ports
72    let Super = IP_EXEC;
73  }
74
75  // Pipeline Groups
76  // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
77  def ALU : ProcResource<4>;
78  def ALUE : ProcResource<2> {
79    //Even ALU pipelines
80    let Super = ALU;
81  }
82  def ALUO : ProcResource<2> {
83    //Odd ALU pipelines
84    let Super = ALU;
85  }
86
87  // Two DIV (Fixed Point Divide) units.
88  def DIV : ProcResource<2>;
89
90  // Four DP (Floating Point) units in total. Two even, two Odd.
91  def DP : ProcResource<4>;
92  def DPE : ProcResource<2> {
93    //Even DP pipelines
94    let Super = DP;
95  }
96  def DPO : ProcResource<2> {
97    //Odd DP pipelines
98    let Super = DP;
99  }
100
101  // Four LS (Load or Store) units.
102  def LS : ProcResource<4>;
103
104  // Two PM (Permute) units.
105  def PM : ProcResource<2>;
106
107  // Only one DFU (Decimal Floating Point and Quad Precision) unit.
108  def DFU : ProcResource<1>;
109
110  // Only one Branch unit.
111  def BR : ProcResource<1> {
112    let BufferSize = 16;
113  }
114
115  // Only one CY (Crypto) unit.
116  def CY : ProcResource<1>;
117
118  // ***************** SchedWriteRes Definitions *****************
119
120  //Dispatcher
121  def DISP_1C : SchedWriteRes<[DISPATCHER]> {
122    let NumMicroOps = 0;
123    let Latency = 1;
124  }
125
126  // Issue Ports
127  def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
128    let NumMicroOps = 0;
129    let Latency = 1;
130  }
131
132  def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
133    let NumMicroOps = 0;
134    let Latency = 1;
135  }
136
137  def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
138    let NumMicroOps = 0;
139    let Latency = 1;
140  }
141
142  def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
143    let NumMicroOps = 0;
144    let Latency = 1;
145  }
146
147  //Pipeline Groups
148
149  // ALU Units
150  // An ALU may take either 2 or 3 cycles to complete the operation.
151  // However, the ALU unit is only every busy for 1 cycle at a time and may
152  // receive new instructions each cycle.
153  def P9_ALU_2C : SchedWriteRes<[ALU]> {
154    let Latency = 2;
155  }
156
157  def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
158    let Latency = 2;
159  }
160
161  def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
162    let Latency = 2;
163  }
164
165  def P9_ALU_3C : SchedWriteRes<[ALU]> {
166    let Latency = 3;
167  }
168
169  def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
170    let Latency = 3;
171  }
172
173  def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
174    let Latency = 3;
175  }
176
177  // DIV Unit
178  // A DIV unit may take from 5 to 40 cycles to complete.
179  // Some DIV operations may keep the unit busy for up to 8 cycles.
180  def P9_DIV_5C : SchedWriteRes<[DIV]> {
181    let Latency = 5;
182  }
183
184  def P9_DIV_12C : SchedWriteRes<[DIV]> {
185    let Latency = 12;
186  }
187
188  def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
189    let ResourceCycles = [8];
190    let Latency = 16;
191  }
192
193  def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
194    let ResourceCycles = [8];
195    let Latency = 24;
196  }
197
198  def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
199    let ResourceCycles = [8];
200    let Latency = 40;
201  }
202
203  // DP Unit
204  // A DP unit may take from 2 to 36 cycles to complete.
205  // Some DP operations keep the unit busy for up to 10 cycles.
206  def P9_DP_2C : SchedWriteRes<[DP]> {
207    let Latency = 2;
208  }
209
210  def P9_DP_5C : SchedWriteRes<[DP]> {
211    let Latency = 5;
212  }
213
214  def P9_DP_7C : SchedWriteRes<[DP]> {
215    let Latency = 7;
216  }
217
218  def P9_DPE_7C : SchedWriteRes<[DPE]> {
219    let Latency = 7;
220  }
221
222  def P9_DPO_7C : SchedWriteRes<[DPO]> {
223    let Latency = 7;
224  }
225
226  def P9_DP_22C_5 : SchedWriteRes<[DP]> {
227    let ResourceCycles = [5];
228    let Latency = 22;
229  }
230
231  def P9_DP_24C_8 : SchedWriteRes<[DP]> {
232    let ResourceCycles = [8];
233    let Latency = 24;
234  }
235
236  def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
237    let ResourceCycles = [8];
238    let Latency = 24;
239  }
240
241  def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
242    let ResourceCycles = [8];
243    let Latency = 24;
244  }
245
246  def P9_DP_26C_5 : SchedWriteRes<[DP]> {
247    let ResourceCycles = [5];
248    let Latency = 22;
249  }
250
251  def P9_DP_27C_7 : SchedWriteRes<[DP]> {
252    let ResourceCycles = [7];
253    let Latency = 27;
254  }
255
256  def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
257    let ResourceCycles = [10];
258    let Latency = 27;
259  }
260
261  def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
262    let ResourceCycles = [10];
263    let Latency = 27;
264  }
265
266  def P9_DP_33C_8 : SchedWriteRes<[DP]> {
267    let ResourceCycles = [8];
268    let Latency = 33;
269  }
270
271  def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
272    let ResourceCycles = [8];
273    let Latency = 33;
274  }
275
276  def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
277    let ResourceCycles = [8];
278    let Latency = 33;
279  }
280
281  def P9_DP_36C_10 : SchedWriteRes<[DP]> {
282    let ResourceCycles = [10];
283    let Latency = 36;
284  }
285
286  def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
287    let ResourceCycles = [10];
288    let Latency = 36;
289  }
290
291  def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
292    let ResourceCycles = [10];
293    let Latency = 36;
294  }
295
296  // PM Unit
297  // Three cycle permute operations.
298  def P9_PM_3C : SchedWriteRes<[PM]> {
299    let Latency = 3;
300  }
301
302  // Load and Store Units
303  // Loads can have 4, 5 or 6 cycles of latency.
304  // Stores are listed as having a single cycle of latency. This is not
305  // completely accurate since it takes more than 1 cycle to actually store
306  // the value. However, since the store does not produce a result it can be
307  // considered complete after one cycle.
308  def P9_LS_1C : SchedWriteRes<[LS]> {
309    let Latency = 1;
310  }
311
312  def P9_LS_4C : SchedWriteRes<[LS]> {
313    let Latency = 4;
314  }
315
316  def P9_LS_5C : SchedWriteRes<[LS]> {
317    let Latency = 5;
318  }
319
320  def P9_LS_6C : SchedWriteRes<[LS]> {
321    let Latency = 6;
322  }
323
324  // DFU Unit
325  // Some of the most expensive ops use the DFU.
326  // Can take from 12 cycles to 76 cycles to obtain a result.
327  // The unit may be busy for up to 62 cycles.
328  def P9_DFU_12C : SchedWriteRes<[DFU]> {
329    let Latency = 12;
330  }
331
332  def P9_DFU_23C : SchedWriteRes<[DFU]> {
333    let Latency = 23;
334    let ResourceCycles = [11];
335  }
336
337  def P9_DFU_24C : SchedWriteRes<[DFU]> {
338    let Latency = 24;
339    let ResourceCycles = [12];
340  }
341
342  def P9_DFU_37C : SchedWriteRes<[DFU]> {
343    let Latency = 37;
344    let ResourceCycles = [25];
345  }
346
347  def P9_DFU_58C : SchedWriteRes<[DFU]> {
348    let Latency = 58;
349    let ResourceCycles = [44];
350  }
351
352  def P9_DFU_76C : SchedWriteRes<[DFU]> {
353    let Latency = 76;
354    let ResourceCycles = [62];
355  }
356
357  // 2 or 5 cycle latencies for the branch unit.
358  def P9_BR_2C : SchedWriteRes<[BR]> {
359    let Latency = 2;
360  }
361
362  def P9_BR_5C : SchedWriteRes<[BR]> {
363    let Latency = 5;
364  }
365
366  // 6 cycle latency for the crypto unit
367  def P9_CY_6C : SchedWriteRes<[CY]> {
368    let Latency = 6;
369  }
370
371  // ***************** WriteSeq Definitions *****************
372
373  // These are combinations of the resources listed above.
374  // The idea is that some cracked instructions cannot be done in parallel and
375  // so the latencies for their resources must be added.
376  def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
377  def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
378  def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
379  def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
380  def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
381  def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
382  def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
383  def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
384  def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
385  def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
386  def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
387  def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
388  def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
389  def P9_ALUOpAndALUOpAndALUOp_6C :
390    WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
391  def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
392  def P9_DPOpAndALUOp_9C : WriteSequence<[P9_DP_7C, P9_ALU_2C]>;
393  def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
394  def P9_DPOpAndALUOp_24C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_2C]>;
395  def P9_DPOpAndALUOp_35C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_2C]>;
396  def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
397  def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>;
398  def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
399  def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>;
400  def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
401
402  // Include the resource requirements of individual instructions.
403  include "P9InstrResources.td"
404
405}
406
407