1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 /// Indicate that the VSX instruction is to use VSX numbering/encoding. 42 /// Since ISA 3.0, there are scalar instructions that use the upper 43 /// half of the VSX register set only. Rather than adding further complexity 44 /// to the register class set, the VSX registers just include the Altivec 45 /// registers and this flag decides the numbering to be used for them. 46 bits<1> UseVSXReg = 0; 47 let TSFlags{6} = UseVSXReg; 48 49 // Fields used for relation models. 50 string BaseName = ""; 51 52 // For cases where multiple instruction definitions really represent the 53 // same underlying instruction but with one definition for 64-bit arguments 54 // and one for 32-bit arguments, this bit breaks the degeneracy between 55 // the two forms and allows TableGen to generate mapping tables. 56 bit Interpretation64Bit = 0; 57} 58 59class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 60class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 61class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 62class PPC970_MicroCode; 63 64class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 65class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 66class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 67class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 68class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 69class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 70class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 71class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 72 73class UseVSXReg { bits<1> UseVSXReg = 1; } 74 75// Two joined instructions; used to emit two adjacent instructions as one. 76// The itinerary from the first instruction is used for scheduling and 77// classification. 78class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 79 InstrItinClass itin> 80 : Instruction { 81 field bits<64> Inst; 82 field bits<64> SoftFail = 0; 83 let Size = 8; 84 85 bit PPC64 = 0; // Default value, override with isPPC64 86 87 let Namespace = "PPC"; 88 let Inst{0-5} = opcode1; 89 let Inst{32-37} = opcode2; 90 let OutOperandList = OOL; 91 let InOperandList = IOL; 92 let AsmString = asmstr; 93 let Itinerary = itin; 94 95 bits<1> PPC970_First = 0; 96 bits<1> PPC970_Single = 0; 97 bits<1> PPC970_Cracked = 0; 98 bits<3> PPC970_Unit = 0; 99 100 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 101 /// these must be reflected there! See comments there for what these are. 102 let TSFlags{0} = PPC970_First; 103 let TSFlags{1} = PPC970_Single; 104 let TSFlags{2} = PPC970_Cracked; 105 let TSFlags{5-3} = PPC970_Unit; 106 107 // Fields used for relation models. 108 string BaseName = ""; 109 bit Interpretation64Bit = 0; 110} 111 112// 1.7.1 I-Form 113class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 114 InstrItinClass itin, list<dag> pattern> 115 : I<opcode, OOL, IOL, asmstr, itin> { 116 let Pattern = pattern; 117 bits<24> LI; 118 119 let Inst{6-29} = LI; 120 let Inst{30} = aa; 121 let Inst{31} = lk; 122} 123 124// 1.7.2 B-Form 125class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 128 bits<3> CR; 129 bits<14> BD; 130 131 bits<5> BI; 132 let BI{0-1} = BIBO{5-6}; 133 let BI{2-4} = CR{0-2}; 134 135 let Inst{6-10} = BIBO{4-0}; 136 let Inst{11-15} = BI; 137 let Inst{16-29} = BD; 138 let Inst{30} = aa; 139 let Inst{31} = lk; 140} 141 142class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 143 string asmstr> 144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 145 let BIBO{4-0} = bo; 146 let BIBO{6-5} = 0; 147 let CR = 0; 148} 149 150class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 151 dag OOL, dag IOL, string asmstr> 152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 153 bits<14> BD; 154 155 let Inst{6-10} = bo; 156 let Inst{11-15} = bi; 157 let Inst{16-29} = BD; 158 let Inst{30} = aa; 159 let Inst{31} = lk; 160} 161 162class BForm_3<bits<6> opcode, bit aa, bit lk, 163 dag OOL, dag IOL, string asmstr> 164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 165 bits<5> BO; 166 bits<5> BI; 167 bits<14> BD; 168 169 let Inst{6-10} = BO; 170 let Inst{11-15} = BI; 171 let Inst{16-29} = BD; 172 let Inst{30} = aa; 173 let Inst{31} = lk; 174} 175 176class BForm_3_at<bits<6> opcode, bit aa, bit lk, 177 dag OOL, dag IOL, string asmstr> 178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 179 bits<5> BO; 180 bits<2> at; 181 bits<5> BI; 182 bits<14> BD; 183 184 let Inst{6-8} = BO{4-2}; 185 let Inst{9-10} = at; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BI; 196 bits<14> BD; 197 198 let Inst{6-10} = bo; 199 let Inst{11-15} = BI; 200 let Inst{16-29} = BD; 201 let Inst{30} = aa; 202 let Inst{31} = lk; 203} 204 205// 1.7.3 SC-Form 206class SCForm<bits<6> opcode, bits<1> xo, 207 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 208 list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<7> LEV; 211 212 let Pattern = pattern; 213 214 let Inst{20-26} = LEV; 215 let Inst{30} = xo; 216} 217 218// 1.7.4 D-Form 219class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 220 InstrItinClass itin, list<dag> pattern> 221 : I<opcode, OOL, IOL, asmstr, itin> { 222 bits<5> A; 223 bits<5> B; 224 bits<16> C; 225 226 let Pattern = pattern; 227 228 let Inst{6-10} = A; 229 let Inst{11-15} = B; 230 let Inst{16-31} = C; 231} 232 233class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 234 InstrItinClass itin, list<dag> pattern> 235 : I<opcode, OOL, IOL, asmstr, itin> { 236 bits<5> A; 237 bits<21> Addr; 238 239 let Pattern = pattern; 240 241 let Inst{6-10} = A; 242 let Inst{11-15} = Addr{20-16}; // Base Reg 243 let Inst{16-31} = Addr{15-0}; // Displacement 244} 245 246class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 247 InstrItinClass itin, list<dag> pattern> 248 : I<opcode, OOL, IOL, asmstr, itin> { 249 bits<5> A; 250 bits<16> C; 251 bits<5> B; 252 253 let Pattern = pattern; 254 255 let Inst{6-10} = A; 256 let Inst{11-15} = B; 257 let Inst{16-31} = C; 258} 259 260 261class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 262 InstrItinClass itin, list<dag> pattern> 263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 264 265 // Even though ADDICo does not really have an RC bit, provide 266 // the declaration of one here so that isDOT has something to set. 267 bit RC = 0; 268} 269 270class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 271 InstrItinClass itin, list<dag> pattern> 272 : I<opcode, OOL, IOL, asmstr, itin> { 273 bits<5> A; 274 bits<16> B; 275 276 let Pattern = pattern; 277 278 let Inst{6-10} = A; 279 let Inst{11-15} = 0; 280 let Inst{16-31} = B; 281} 282 283class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 284 InstrItinClass itin, list<dag> pattern> 285 : I<opcode, OOL, IOL, asmstr, itin> { 286 bits<5> B; 287 bits<5> A; 288 bits<16> C; 289 290 let Pattern = pattern; 291 292 let Inst{6-10} = A; 293 let Inst{11-15} = B; 294 let Inst{16-31} = C; 295} 296 297class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin, list<dag> pattern> 299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 300 let A = 0; 301 let Addr = 0; 302} 303 304class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 305 string asmstr, InstrItinClass itin, 306 list<dag> pattern> 307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 308 let A = R; 309 let B = R; 310 let C = 0; 311} 312 313class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 314 dag OOL, dag IOL, string asmstr, 315 InstrItinClass itin, list<dag> pattern> 316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 317 bits<5> A; 318 bits<21> Addr; 319 320 let Pattern = pattern; 321 bits<24> LI; 322 323 let Inst{6-29} = LI; 324 let Inst{30} = aa; 325 let Inst{31} = lk; 326 327 let Inst{38-42} = A; 328 let Inst{43-47} = Addr{20-16}; // Base Reg 329 let Inst{48-63} = Addr{15-0}; // Displacement 330} 331 332// This is used to emit BL8+NOP. 333class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 334 dag OOL, dag IOL, string asmstr, 335 InstrItinClass itin, list<dag> pattern> 336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 337 OOL, IOL, asmstr, itin, pattern> { 338 let A = 0; 339 let Addr = 0; 340} 341 342class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 343 InstrItinClass itin> 344 : I<opcode, OOL, IOL, asmstr, itin> { 345 bits<3> BF; 346 bits<1> L; 347 bits<5> RA; 348 bits<16> I; 349 350 let Inst{6-8} = BF; 351 let Inst{9} = 0; 352 let Inst{10} = L; 353 let Inst{11-15} = RA; 354 let Inst{16-31} = I; 355} 356 357class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 358 InstrItinClass itin> 359 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 360 let L = PPC64; 361} 362 363class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 364 InstrItinClass itin> 365 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 366 367class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 370 let L = PPC64; 371} 372 373 374// 1.7.5 DS-Form 375class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 376 InstrItinClass itin, list<dag> pattern> 377 : I<opcode, OOL, IOL, asmstr, itin> { 378 bits<5> RST; 379 bits<19> DS_RA; 380 381 let Pattern = pattern; 382 383 let Inst{6-10} = RST; 384 let Inst{11-15} = DS_RA{18-14}; // Register # 385 let Inst{16-29} = DS_RA{13-0}; // Displacement. 386 let Inst{30-31} = xo; 387} 388 389// ISA V3.0B 1.6.6 DX-Form 390class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 391 InstrItinClass itin, list<dag> pattern> 392 : I<opcode, OOL, IOL, asmstr, itin> { 393 bits<5> RT; 394 bits<16> D; 395 396 let Pattern = pattern; 397 398 let Inst{6-10} = RT; 399 let Inst{11-15} = D{5-1}; // d1 400 let Inst{16-25} = D{15-6}; // d0 401 let Inst{26-30} = xo; 402 let Inst{31} = D{0}; // d2 403} 404 405// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 406class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 407 string asmstr, InstrItinClass itin, list<dag> pattern> 408 : I<opcode, OOL, IOL, asmstr, itin> { 409 bits<6> XT; 410 bits<17> DS_RA; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = XT{4-0}; 415 let Inst{11-15} = DS_RA{16-12}; // Register # 416 let Inst{16-27} = DS_RA{11-0}; // Displacement. 417 let Inst{28} = XT{5}; 418 let Inst{29-31} = xo; 419} 420 421// 1.7.6 X-Form 422class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 423 InstrItinClass itin, list<dag> pattern> 424 : I<opcode, OOL, IOL, asmstr, itin> { 425 bits<5> RST; 426 bits<5> A; 427 bits<5> B; 428 429 let Pattern = pattern; 430 431 bit RC = 0; // set by isDOT 432 433 let Inst{6-10} = RST; 434 let Inst{11-15} = A; 435 let Inst{16-20} = B; 436 let Inst{21-30} = xo; 437 let Inst{31} = RC; 438} 439 440class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 441 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 442 let RST = 0; 443} 444 445class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 446 InstrItinClass itin> 447 : I<opcode, OOL, IOL, asmstr, itin> { 448 let Inst{21-30} = xo; 449} 450 451// This is the same as XForm_base_r3xo, but the first two operands are swapped 452// when code is emitted. 453class XForm_base_r3xo_swapped 454 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 455 InstrItinClass itin> 456 : I<opcode, OOL, IOL, asmstr, itin> { 457 bits<5> A; 458 bits<5> RST; 459 bits<5> B; 460 461 bit RC = 0; // set by isDOT 462 463 let Inst{6-10} = RST; 464 let Inst{11-15} = A; 465 let Inst{16-20} = B; 466 let Inst{21-30} = xo; 467 let Inst{31} = RC; 468} 469 470 471class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 472 InstrItinClass itin, list<dag> pattern> 473 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 474 475class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 476 InstrItinClass itin, list<dag> pattern> 477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 478 let RST = 0; 479} 480 481class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 482 InstrItinClass itin, list<dag> pattern> 483 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 484 let A = 0; 485 let B = 0; 486} 487 488class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 489 InstrItinClass itin, list<dag> pattern> 490 : I<opcode, OOL, IOL, asmstr, itin> { 491 bits<5> RST; 492 bits<5> A; 493 bits<1> WS; 494 495 let Pattern = pattern; 496 497 let Inst{6-10} = RST; 498 let Inst{11-15} = A; 499 let Inst{20} = WS; 500 let Inst{21-30} = xo; 501 let Inst{31} = 0; 502} 503 504class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 505 InstrItinClass itin, list<dag> pattern> 506 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 507 let Pattern = pattern; 508} 509 510class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 511 InstrItinClass itin, list<dag> pattern> 512 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 513 514class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 515 InstrItinClass itin, list<dag> pattern> 516 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 517 let Pattern = pattern; 518} 519 520class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 521 InstrItinClass itin, list<dag> pattern> 522 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 523 let B = 0; 524 let Pattern = pattern; 525} 526 527class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin> 529 : I<opcode, OOL, IOL, asmstr, itin> { 530 bits<3> BF; 531 bits<1> L; 532 bits<5> RA; 533 bits<5> RB; 534 535 let Inst{6-8} = BF; 536 let Inst{9} = 0; 537 let Inst{10} = L; 538 let Inst{11-15} = RA; 539 let Inst{16-20} = RB; 540 let Inst{21-30} = xo; 541 let Inst{31} = 0; 542} 543 544class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : I<opcode, OOL, IOL, asmstr, itin> { 547 bits<4> CT; 548 bits<5> RA; 549 bits<5> RB; 550 551 let Inst{6} = 0; 552 let Inst{7-10} = CT; 553 let Inst{11-15} = RA; 554 let Inst{16-20} = RB; 555 let Inst{21-30} = xo; 556 let Inst{31} = 0; 557} 558 559class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 560 InstrItinClass itin> 561 : I<opcode, OOL, IOL, asmstr, itin> { 562 bits<5> RS; 563 bits<4> SR; 564 565 let Inst{6-10} = RS; 566 let Inst{12-15} = SR; 567 let Inst{21-30} = xo; 568} 569 570class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 571 InstrItinClass itin> 572 : I<opcode, OOL, IOL, asmstr, itin> { 573 bits<5> MO; 574 575 let Inst{6-10} = MO; 576 let Inst{21-30} = xo; 577} 578 579class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 580 InstrItinClass itin> 581 : I<opcode, OOL, IOL, asmstr, itin> { 582 bits<5> RS; 583 bits<5> RB; 584 585 let Inst{6-10} = RS; 586 let Inst{16-20} = RB; 587 let Inst{21-30} = xo; 588} 589 590class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 591 InstrItinClass itin> 592 : I<opcode, OOL, IOL, asmstr, itin> { 593 bits<5> RS; 594 bits<1> L; 595 596 let Inst{6-10} = RS; 597 let Inst{15} = L; 598 let Inst{21-30} = xo; 599} 600 601class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 602 InstrItinClass itin> 603 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 604 let L = PPC64; 605} 606 607class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin> 609 : I<opcode, OOL, IOL, asmstr, itin> { 610 bits<3> BF; 611 bits<5> FRA; 612 bits<5> FRB; 613 614 let Inst{6-8} = BF; 615 let Inst{9-10} = 0; 616 let Inst{11-15} = FRA; 617 let Inst{16-20} = FRB; 618 let Inst{21-30} = xo; 619 let Inst{31} = 0; 620} 621 622class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 623 InstrItinClass itin> 624 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 625 let FRA = 0; 626} 627 628// Used for QPX 629class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 630 InstrItinClass itin, list<dag> pattern> 631 : I<opcode, OOL, IOL, asmstr, itin> { 632 bits<5> FRT; 633 bits<5> FRA; 634 bits<5> FRB; 635 636 let Pattern = pattern; 637 638 let Inst{6-10} = FRT; 639 let Inst{11-15} = FRA; 640 let Inst{16-20} = FRB; 641 let Inst{21-30} = xo; 642 let Inst{31} = 0; 643} 644 645class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 646 InstrItinClass itin, list<dag> pattern> 647 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 648 let FRA = 0; 649} 650 651class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 652 InstrItinClass itin, list<dag> pattern> 653 : I<opcode, OOL, IOL, asmstr, itin> { 654 bits<5> FRT; 655 bits<5> FRA; 656 bits<5> FRB; 657 bits<4> tttt; 658 659 let Pattern = pattern; 660 661 let Inst{6-10} = FRT; 662 let Inst{11-15} = FRA; 663 let Inst{16-20} = FRB; 664 let Inst{21-24} = tttt; 665 let Inst{25-30} = xo; 666 let Inst{31} = 0; 667} 668 669class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 670 InstrItinClass itin, list<dag> pattern> 671 : I<opcode, OOL, IOL, asmstr, itin> { 672 let Pattern = pattern; 673 let Inst{6-10} = 31; 674 let Inst{11-15} = 0; 675 let Inst{16-20} = 0; 676 let Inst{21-30} = xo; 677 let Inst{31} = 0; 678} 679 680class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 681 string asmstr, InstrItinClass itin, list<dag> pattern> 682 : I<opcode, OOL, IOL, asmstr, itin> { 683 bits<2> L; 684 685 let Pattern = pattern; 686 let Inst{6-8} = 0; 687 let Inst{9-10} = L; 688 let Inst{11-15} = 0; 689 let Inst{16-20} = 0; 690 let Inst{21-30} = xo; 691 let Inst{31} = 0; 692} 693 694class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 695 string asmstr, InstrItinClass itin, list<dag> pattern> 696 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 697 let L = 0; 698} 699 700class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 701 InstrItinClass itin, list<dag> pattern> 702 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 703} 704 705class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 706 InstrItinClass itin, list<dag> pattern> 707 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 708 let A = 0; 709} 710 711class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 712 InstrItinClass itin, list<dag> pattern> 713 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 714} 715 716// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 717// numbers presumably relates to some document, but I haven't found it. 718class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 719 InstrItinClass itin, list<dag> pattern> 720 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 721 let Pattern = pattern; 722 723 bit RC = 0; // set by isDOT 724 725 let Inst{6-10} = RST; 726 let Inst{11-20} = 0; 727 let Inst{21-30} = xo; 728 let Inst{31} = RC; 729} 730class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 731 InstrItinClass itin, list<dag> pattern> 732 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 733 let Pattern = pattern; 734 bits<5> FM; 735 736 bit RC = 0; // set by isDOT 737 738 let Inst{6-10} = FM; 739 let Inst{11-20} = 0; 740 let Inst{21-30} = xo; 741 let Inst{31} = RC; 742} 743 744class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 745 InstrItinClass itin> 746 : I<opcode, OOL, IOL, asmstr, itin> { 747 bits<5> RT; 748 bits<3> BFA; 749 750 let Inst{6-10} = RT; 751 let Inst{11-13} = BFA; 752 let Inst{14-15} = 0; 753 let Inst{16-20} = 0; 754 let Inst{21-30} = xo; 755 let Inst{31} = 0; 756} 757 758class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 759 InstrItinClass itin> 760 : I<opcode, OOL, IOL, asmstr, itin> { 761 bits<5> RT; 762 bits<2> L; 763 764 let Inst{6-10} = RT; 765 let Inst{11-13} = 0; 766 let Inst{14-15} = L; 767 let Inst{16-20} = 0; 768 let Inst{21-30} = xo; 769 let Inst{31} = 0; 770} 771 772class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 773 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 774 list<dag> pattern> 775 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 776 let Pattern = pattern; 777 778 let Inst{6-10} = RST; 779 let Inst{11-12} = xo1; 780 let Inst{13-15} = xo2; 781 let Inst{16-20} = 0; 782 let Inst{21-30} = xo; 783 let Inst{31} = 0; 784} 785 786class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 787 bits<10> xo, dag OOL, dag IOL, string asmstr, 788 InstrItinClass itin, list<dag> pattern> 789 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 790 let Pattern = pattern; 791 bits<5> FRB; 792 793 let Inst{6-10} = RST; 794 let Inst{11-12} = xo1; 795 let Inst{13-15} = xo2; 796 let Inst{16-20} = FRB; 797 let Inst{21-30} = xo; 798 let Inst{31} = 0; 799} 800 801class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 802 bits<10> xo, dag OOL, dag IOL, string asmstr, 803 InstrItinClass itin, list<dag> pattern> 804 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 805 let Pattern = pattern; 806 bits<3> DRM; 807 808 let Inst{6-10} = RST; 809 let Inst{11-12} = xo1; 810 let Inst{13-15} = xo2; 811 let Inst{16-17} = 0; 812 let Inst{18-20} = DRM; 813 let Inst{21-30} = xo; 814 let Inst{31} = 0; 815} 816 817class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 818 bits<10> xo, dag OOL, dag IOL, string asmstr, 819 InstrItinClass itin, list<dag> pattern> 820 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 821 let Pattern = pattern; 822 bits<2> RM; 823 824 let Inst{6-10} = RST; 825 let Inst{11-12} = xo1; 826 let Inst{13-15} = xo2; 827 let Inst{16-18} = 0; 828 let Inst{19-20} = RM; 829 let Inst{21-30} = xo; 830 let Inst{31} = 0; 831} 832 833 834class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 835 InstrItinClass itin, list<dag> pattern> 836 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 837 let RST = 0; 838 let A = 0; 839 let B = 0; 840} 841 842class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 843 InstrItinClass itin, list<dag> pattern> 844 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 845 let RST = 0; 846 let A = 0; 847} 848 849class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 850 string asmstr, InstrItinClass itin, list<dag> pattern> 851 : I<opcode, OOL, IOL, asmstr, itin> { 852 bit R; 853 854 bit RC = 1; 855 856 let Inst{6-9} = 0; 857 let Inst{10} = R; 858 let Inst{11-20} = 0; 859 let Inst{21-30} = xo; 860 let Inst{31} = RC; 861} 862 863class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 864 string asmstr, InstrItinClass itin, list<dag> pattern> 865 : I<opcode, OOL, IOL, asmstr, itin> { 866 bit A; 867 868 bit RC = 1; 869 870 let Inst{6} = A; 871 let Inst{7-20} = 0; 872 let Inst{21-30} = xo; 873 let Inst{31} = RC; 874} 875 876class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 877 InstrItinClass itin, list<dag> pattern> 878 : I<opcode, OOL, IOL, asmstr, itin> { 879 bit L; 880 881 bit RC = 0; // set by isDOT 882 883 let Inst{7-9} = 0; 884 let Inst{10} = L; 885 let Inst{11-20} = 0; 886 let Inst{21-30} = xo; 887 let Inst{31} = RC; 888} 889 890class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 891 InstrItinClass itin, list<dag> pattern> 892 : I<opcode, OOL, IOL, asmstr, itin> { 893 bits<3> BF; 894 895 bit RC = 0; 896 897 let Inst{6-8} = BF; 898 let Inst{9-20} = 0; 899 let Inst{21-30} = xo; 900 let Inst{31} = RC; 901} 902 903// [PO RT RA RB XO /] 904class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 905 string asmstr, InstrItinClass itin, list<dag> pattern> 906 : I<opcode, OOL, IOL, asmstr, itin> { 907 bits<3> BF; 908 bits<1> L; 909 bits<5> RA; 910 bits<5> RB; 911 912 let Pattern = pattern; 913 914 let Inst{6-8} = BF; 915 let Inst{9} = 0; 916 let Inst{10} = L; 917 let Inst{11-15} = RA; 918 let Inst{16-20} = RB; 919 let Inst{21-30} = xo; 920 let Inst{31} = 0; 921} 922 923// Same as XForm_17 but with GPR's and new naming convention 924class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 925 string asmstr, InstrItinClass itin, list<dag> pattern> 926 : I<opcode, OOL, IOL, asmstr, itin> { 927 bits<3> BF; 928 bits<5> RA; 929 bits<5> RB; 930 931 let Pattern = pattern; 932 933 let Inst{6-8} = BF; 934 let Inst{9-10} = 0; 935 let Inst{11-15} = RA; 936 let Inst{16-20} = RB; 937 let Inst{21-30} = xo; 938 let Inst{31} = 0; 939} 940 941// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 942class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 943 string asmstr, InstrItinClass itin, list<dag> pattern> 944 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 945 let A = xo2; 946} 947 948class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 949 string asmstr, InstrItinClass itin, list<dag> pattern> 950 : I<opcode, OOL, IOL, asmstr, itin> { 951 bits<3> BF; 952 bits<7> DCMX; 953 bits<5> VB; 954 955 let Pattern = pattern; 956 957 let Inst{6-8} = BF; 958 let Inst{9-15} = DCMX; 959 let Inst{16-20} = VB; 960 let Inst{21-30} = xo; 961 let Inst{31} = 0; 962} 963 964class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 965 string asmstr, InstrItinClass itin, list<dag> pattern> 966 : I<opcode, OOL, IOL, asmstr, itin> { 967 bits<6> XT; 968 bits<8> IMM8; 969 970 let Pattern = pattern; 971 972 let Inst{6-10} = XT{4-0}; 973 let Inst{11-12} = 0; 974 let Inst{13-20} = IMM8; 975 let Inst{21-30} = xo; 976 let Inst{31} = XT{5}; 977} 978 979// XForm_base_r3xo for instructions such as P9 atomics where we don't want 980// to specify an SDAG pattern for matching. 981class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 982 string asmstr, InstrItinClass itin> 983 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> { 984} 985 986class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 987 InstrItinClass itin> 988 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 989 let FRA = 0; 990 let FRB = 0; 991} 992 993// [PO /// L RA RB XO /] 994class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 995 string asmstr, InstrItinClass itin, list<dag> pattern> 996 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 997 let BF = 0; 998 let Pattern = pattern; 999 1000 bit RC = 0; 1001 let Inst{31} = RC; 1002} 1003 1004// XX*-Form (VSX) 1005class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1006 InstrItinClass itin, list<dag> pattern> 1007 : I<opcode, OOL, IOL, asmstr, itin> { 1008 bits<6> XT; 1009 bits<5> A; 1010 bits<5> B; 1011 1012 let Pattern = pattern; 1013 1014 let Inst{6-10} = XT{4-0}; 1015 let Inst{11-15} = A; 1016 let Inst{16-20} = B; 1017 let Inst{21-30} = xo; 1018 let Inst{31} = XT{5}; 1019} 1020 1021class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1022 string asmstr, InstrItinClass itin, list<dag> pattern> 1023 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1024 let B = 0; 1025} 1026 1027class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1028 InstrItinClass itin, list<dag> pattern> 1029 : I<opcode, OOL, IOL, asmstr, itin> { 1030 bits<6> XT; 1031 bits<6> XB; 1032 1033 let Pattern = pattern; 1034 1035 let Inst{6-10} = XT{4-0}; 1036 let Inst{11-15} = 0; 1037 let Inst{16-20} = XB{4-0}; 1038 let Inst{21-29} = xo; 1039 let Inst{30} = XB{5}; 1040 let Inst{31} = XT{5}; 1041} 1042 1043class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1044 InstrItinClass itin, list<dag> pattern> 1045 : I<opcode, OOL, IOL, asmstr, itin> { 1046 bits<3> CR; 1047 bits<6> XB; 1048 1049 let Pattern = pattern; 1050 1051 let Inst{6-8} = CR; 1052 let Inst{9-15} = 0; 1053 let Inst{16-20} = XB{4-0}; 1054 let Inst{21-29} = xo; 1055 let Inst{30} = XB{5}; 1056 let Inst{31} = 0; 1057} 1058 1059class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1060 InstrItinClass itin, list<dag> pattern> 1061 : I<opcode, OOL, IOL, asmstr, itin> { 1062 bits<6> XT; 1063 bits<6> XB; 1064 bits<2> D; 1065 1066 let Pattern = pattern; 1067 1068 let Inst{6-10} = XT{4-0}; 1069 let Inst{11-13} = 0; 1070 let Inst{14-15} = D; 1071 let Inst{16-20} = XB{4-0}; 1072 let Inst{21-29} = xo; 1073 let Inst{30} = XB{5}; 1074 let Inst{31} = XT{5}; 1075} 1076 1077class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1078 string asmstr, InstrItinClass itin, list<dag> pattern> 1079 : I<opcode, OOL, IOL, asmstr, itin> { 1080 bits<6> XT; 1081 bits<6> XB; 1082 bits<5> UIM5; 1083 1084 let Pattern = pattern; 1085 1086 let Inst{6-10} = XT{4-0}; 1087 let Inst{11-15} = UIM5; 1088 let Inst{16-20} = XB{4-0}; 1089 let Inst{21-29} = xo; 1090 let Inst{30} = XB{5}; 1091 let Inst{31} = XT{5}; 1092} 1093 1094// [PO T XO B XO BX /] 1095class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1096 string asmstr, InstrItinClass itin, list<dag> pattern> 1097 : I<opcode, OOL, IOL, asmstr, itin> { 1098 bits<5> RT; 1099 bits<6> XB; 1100 1101 let Pattern = pattern; 1102 1103 let Inst{6-10} = RT; 1104 let Inst{11-15} = xo2; 1105 let Inst{16-20} = XB{4-0}; 1106 let Inst{21-29} = xo; 1107 let Inst{30} = XB{5}; 1108 let Inst{31} = 0; 1109} 1110 1111// [PO T XO B XO BX TX] 1112class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1113 string asmstr, InstrItinClass itin, list<dag> pattern> 1114 : I<opcode, OOL, IOL, asmstr, itin> { 1115 bits<6> XT; 1116 bits<6> XB; 1117 1118 let Pattern = pattern; 1119 1120 let Inst{6-10} = XT{4-0}; 1121 let Inst{11-15} = xo2; 1122 let Inst{16-20} = XB{4-0}; 1123 let Inst{21-29} = xo; 1124 let Inst{30} = XB{5}; 1125 let Inst{31} = XT{5}; 1126} 1127 1128class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1129 string asmstr, InstrItinClass itin, list<dag> pattern> 1130 : I<opcode, OOL, IOL, asmstr, itin> { 1131 bits<3> BF; 1132 bits<7> DCMX; 1133 bits<6> XB; 1134 1135 let Pattern = pattern; 1136 1137 let Inst{6-8} = BF; 1138 let Inst{9-15} = DCMX; 1139 let Inst{16-20} = XB{4-0}; 1140 let Inst{21-29} = xo; 1141 let Inst{30} = XB{5}; 1142 let Inst{31} = 0; 1143} 1144 1145class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1146 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1147 list<dag> pattern> 1148 : I<opcode, OOL, IOL, asmstr, itin> { 1149 bits<6> XT; 1150 bits<7> DCMX; 1151 bits<6> XB; 1152 1153 let Pattern = pattern; 1154 1155 let Inst{6-10} = XT{4-0}; 1156 let Inst{11-15} = DCMX{4-0}; 1157 let Inst{16-20} = XB{4-0}; 1158 let Inst{21-24} = xo1; 1159 let Inst{25} = DCMX{5}; 1160 let Inst{26-28} = xo2; 1161 let Inst{29} = DCMX{6}; 1162 let Inst{30} = XB{5}; 1163 let Inst{31} = XT{5}; 1164} 1165 1166class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1167 InstrItinClass itin, list<dag> pattern> 1168 : I<opcode, OOL, IOL, asmstr, itin> { 1169 bits<6> XT; 1170 bits<6> XA; 1171 bits<6> XB; 1172 1173 let Pattern = pattern; 1174 1175 let Inst{6-10} = XT{4-0}; 1176 let Inst{11-15} = XA{4-0}; 1177 let Inst{16-20} = XB{4-0}; 1178 let Inst{21-28} = xo; 1179 let Inst{29} = XA{5}; 1180 let Inst{30} = XB{5}; 1181 let Inst{31} = XT{5}; 1182} 1183 1184class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1185 InstrItinClass itin, list<dag> pattern> 1186 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1187 let XA = XT; 1188 let XB = XT; 1189} 1190 1191class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1192 InstrItinClass itin, list<dag> pattern> 1193 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1194 let XB = XT; 1195 let XA = XT; 1196} 1197 1198class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1199 InstrItinClass itin, list<dag> pattern> 1200 : I<opcode, OOL, IOL, asmstr, itin> { 1201 bits<3> CR; 1202 bits<6> XA; 1203 bits<6> XB; 1204 1205 let Pattern = pattern; 1206 1207 let Inst{6-8} = CR; 1208 let Inst{9-10} = 0; 1209 let Inst{11-15} = XA{4-0}; 1210 let Inst{16-20} = XB{4-0}; 1211 let Inst{21-28} = xo; 1212 let Inst{29} = XA{5}; 1213 let Inst{30} = XB{5}; 1214 let Inst{31} = 0; 1215} 1216 1217class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1218 InstrItinClass itin, list<dag> pattern> 1219 : I<opcode, OOL, IOL, asmstr, itin> { 1220 bits<6> XT; 1221 bits<6> XA; 1222 bits<6> XB; 1223 bits<2> D; 1224 1225 let Pattern = pattern; 1226 1227 let Inst{6-10} = XT{4-0}; 1228 let Inst{11-15} = XA{4-0}; 1229 let Inst{16-20} = XB{4-0}; 1230 let Inst{21} = 0; 1231 let Inst{22-23} = D; 1232 let Inst{24-28} = xo; 1233 let Inst{29} = XA{5}; 1234 let Inst{30} = XB{5}; 1235 let Inst{31} = XT{5}; 1236} 1237 1238class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1239 InstrItinClass itin, list<dag> pattern> 1240 : I<opcode, OOL, IOL, asmstr, itin> { 1241 bits<6> XT; 1242 bits<6> XA; 1243 bits<6> XB; 1244 1245 let Pattern = pattern; 1246 1247 bit RC = 0; // set by isDOT 1248 1249 let Inst{6-10} = XT{4-0}; 1250 let Inst{11-15} = XA{4-0}; 1251 let Inst{16-20} = XB{4-0}; 1252 let Inst{21} = RC; 1253 let Inst{22-28} = xo; 1254 let Inst{29} = XA{5}; 1255 let Inst{30} = XB{5}; 1256 let Inst{31} = XT{5}; 1257} 1258 1259class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1260 InstrItinClass itin, list<dag> pattern> 1261 : I<opcode, OOL, IOL, asmstr, itin> { 1262 bits<6> XT; 1263 bits<6> XA; 1264 bits<6> XB; 1265 bits<6> XC; 1266 1267 let Pattern = pattern; 1268 1269 let Inst{6-10} = XT{4-0}; 1270 let Inst{11-15} = XA{4-0}; 1271 let Inst{16-20} = XB{4-0}; 1272 let Inst{21-25} = XC{4-0}; 1273 let Inst{26-27} = xo; 1274 let Inst{28} = XC{5}; 1275 let Inst{29} = XA{5}; 1276 let Inst{30} = XB{5}; 1277 let Inst{31} = XT{5}; 1278} 1279 1280// DCB_Form - Form X instruction, used for dcb* instructions. 1281class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1282 InstrItinClass itin, list<dag> pattern> 1283 : I<31, OOL, IOL, asmstr, itin> { 1284 bits<5> A; 1285 bits<5> B; 1286 1287 let Pattern = pattern; 1288 1289 let Inst{6-10} = immfield; 1290 let Inst{11-15} = A; 1291 let Inst{16-20} = B; 1292 let Inst{21-30} = xo; 1293 let Inst{31} = 0; 1294} 1295 1296class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1297 InstrItinClass itin, list<dag> pattern> 1298 : I<31, OOL, IOL, asmstr, itin> { 1299 bits<5> TH; 1300 bits<5> A; 1301 bits<5> B; 1302 1303 let Pattern = pattern; 1304 1305 let Inst{6-10} = TH; 1306 let Inst{11-15} = A; 1307 let Inst{16-20} = B; 1308 let Inst{21-30} = xo; 1309 let Inst{31} = 0; 1310} 1311 1312// DSS_Form - Form X instruction, used for altivec dss* instructions. 1313class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1314 InstrItinClass itin, list<dag> pattern> 1315 : I<31, OOL, IOL, asmstr, itin> { 1316 bits<2> STRM; 1317 bits<5> A; 1318 bits<5> B; 1319 1320 let Pattern = pattern; 1321 1322 let Inst{6} = T; 1323 let Inst{7-8} = 0; 1324 let Inst{9-10} = STRM; 1325 let Inst{11-15} = A; 1326 let Inst{16-20} = B; 1327 let Inst{21-30} = xo; 1328 let Inst{31} = 0; 1329} 1330 1331// 1.7.7 XL-Form 1332class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1333 InstrItinClass itin, list<dag> pattern> 1334 : I<opcode, OOL, IOL, asmstr, itin> { 1335 bits<5> CRD; 1336 bits<5> CRA; 1337 bits<5> CRB; 1338 1339 let Pattern = pattern; 1340 1341 let Inst{6-10} = CRD; 1342 let Inst{11-15} = CRA; 1343 let Inst{16-20} = CRB; 1344 let Inst{21-30} = xo; 1345 let Inst{31} = 0; 1346} 1347 1348class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1349 InstrItinClass itin, list<dag> pattern> 1350 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1351 let CRD = 0; 1352 let CRA = 0; 1353 let CRB = 0; 1354} 1355 1356class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1357 InstrItinClass itin, list<dag> pattern> 1358 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1359 bits<5> RT; 1360 bits<5> RB; 1361 1362 let CRD = RT; 1363 let CRA = 0; 1364 let CRB = RB; 1365} 1366 1367class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1368 InstrItinClass itin, list<dag> pattern> 1369 : I<opcode, OOL, IOL, asmstr, itin> { 1370 bits<5> CRD; 1371 1372 let Pattern = pattern; 1373 1374 let Inst{6-10} = CRD; 1375 let Inst{11-15} = CRD; 1376 let Inst{16-20} = CRD; 1377 let Inst{21-30} = xo; 1378 let Inst{31} = 0; 1379} 1380 1381class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1382 InstrItinClass itin, list<dag> pattern> 1383 : I<opcode, OOL, IOL, asmstr, itin> { 1384 bits<5> BO; 1385 bits<5> BI; 1386 bits<2> BH; 1387 1388 let Pattern = pattern; 1389 1390 let Inst{6-10} = BO; 1391 let Inst{11-15} = BI; 1392 let Inst{16-18} = 0; 1393 let Inst{19-20} = BH; 1394 let Inst{21-30} = xo; 1395 let Inst{31} = lk; 1396} 1397 1398class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1399 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1400 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1401 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1402 bits<3> CR; 1403 1404 let BO = BIBO{4-0}; 1405 let BI{0-1} = BIBO{5-6}; 1406 let BI{2-4} = CR{0-2}; 1407 let BH = 0; 1408} 1409 1410class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1411 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1412 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1413 let BO = bo; 1414 let BH = 0; 1415} 1416 1417class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1418 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1419 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1420 let BO = bo; 1421 let BI = bi; 1422 let BH = 0; 1423} 1424 1425class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1426 InstrItinClass itin> 1427 : I<opcode, OOL, IOL, asmstr, itin> { 1428 bits<3> BF; 1429 bits<3> BFA; 1430 1431 let Inst{6-8} = BF; 1432 let Inst{9-10} = 0; 1433 let Inst{11-13} = BFA; 1434 let Inst{14-15} = 0; 1435 let Inst{16-20} = 0; 1436 let Inst{21-30} = xo; 1437 let Inst{31} = 0; 1438} 1439 1440class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1441 InstrItinClass itin> 1442 : I<opcode, OOL, IOL, asmstr, itin> { 1443 bits<3> BF; 1444 bit W; 1445 bits<4> U; 1446 1447 bit RC = 0; 1448 1449 let Inst{6-8} = BF; 1450 let Inst{9-10} = 0; 1451 let Inst{11-14} = 0; 1452 let Inst{15} = W; 1453 let Inst{16-19} = U; 1454 let Inst{20} = 0; 1455 let Inst{21-30} = xo; 1456 let Inst{31} = RC; 1457} 1458 1459class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1460 InstrItinClass itin, list<dag> pattern> 1461 : I<opcode, OOL, IOL, asmstr, itin> { 1462 bits<1> S; 1463 1464 let Pattern = pattern; 1465 1466 let Inst{6-19} = 0; 1467 let Inst{20} = S; 1468 let Inst{21-30} = xo; 1469 let Inst{31} = 0; 1470} 1471 1472class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1473 bits<6> opcode2, bits<2> xo2, 1474 dag OOL, dag IOL, string asmstr, 1475 InstrItinClass itin, list<dag> pattern> 1476 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1477 bits<5> BO; 1478 bits<5> BI; 1479 bits<2> BH; 1480 1481 bits<5> RST; 1482 bits<19> DS_RA; 1483 1484 let Pattern = pattern; 1485 1486 let Inst{6-10} = BO; 1487 let Inst{11-15} = BI; 1488 let Inst{16-18} = 0; 1489 let Inst{19-20} = BH; 1490 let Inst{21-30} = xo1; 1491 let Inst{31} = lk; 1492 1493 let Inst{38-42} = RST; 1494 let Inst{43-47} = DS_RA{18-14}; // Register # 1495 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1496 let Inst{62-63} = xo2; 1497} 1498 1499class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1500 bits<5> bo, bits<5> bi, bit lk, 1501 bits<6> opcode2, bits<2> xo2, 1502 dag OOL, dag IOL, string asmstr, 1503 InstrItinClass itin, list<dag> pattern> 1504 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1505 OOL, IOL, asmstr, itin, pattern> { 1506 let BO = bo; 1507 let BI = bi; 1508 let BH = 0; 1509} 1510 1511// 1.7.8 XFX-Form 1512class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1513 InstrItinClass itin> 1514 : I<opcode, OOL, IOL, asmstr, itin> { 1515 bits<5> RT; 1516 bits<10> SPR; 1517 1518 let Inst{6-10} = RT; 1519 let Inst{11} = SPR{4}; 1520 let Inst{12} = SPR{3}; 1521 let Inst{13} = SPR{2}; 1522 let Inst{14} = SPR{1}; 1523 let Inst{15} = SPR{0}; 1524 let Inst{16} = SPR{9}; 1525 let Inst{17} = SPR{8}; 1526 let Inst{18} = SPR{7}; 1527 let Inst{19} = SPR{6}; 1528 let Inst{20} = SPR{5}; 1529 let Inst{21-30} = xo; 1530 let Inst{31} = 0; 1531} 1532 1533class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1534 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1535 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1536 let SPR = spr; 1537} 1538 1539class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1540 InstrItinClass itin> 1541 : I<opcode, OOL, IOL, asmstr, itin> { 1542 bits<5> RT; 1543 1544 let Inst{6-10} = RT; 1545 let Inst{11-20} = 0; 1546 let Inst{21-30} = xo; 1547 let Inst{31} = 0; 1548} 1549 1550class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1551 InstrItinClass itin, list<dag> pattern> 1552 : I<opcode, OOL, IOL, asmstr, itin> { 1553 bits<5> RT; 1554 bits<10> Entry; 1555 let Pattern = pattern; 1556 1557 let Inst{6-10} = RT; 1558 let Inst{11-20} = Entry; 1559 let Inst{21-30} = xo; 1560 let Inst{31} = 0; 1561} 1562 1563class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1564 InstrItinClass itin> 1565 : I<opcode, OOL, IOL, asmstr, itin> { 1566 bits<8> FXM; 1567 bits<5> rS; 1568 1569 let Inst{6-10} = rS; 1570 let Inst{11} = 0; 1571 let Inst{12-19} = FXM; 1572 let Inst{20} = 0; 1573 let Inst{21-30} = xo; 1574 let Inst{31} = 0; 1575} 1576 1577class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1578 InstrItinClass itin> 1579 : I<opcode, OOL, IOL, asmstr, itin> { 1580 bits<5> ST; 1581 bits<8> FXM; 1582 1583 let Inst{6-10} = ST; 1584 let Inst{11} = 1; 1585 let Inst{12-19} = FXM; 1586 let Inst{20} = 0; 1587 let Inst{21-30} = xo; 1588 let Inst{31} = 0; 1589} 1590 1591class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1592 InstrItinClass itin> 1593 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1594 1595class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1596 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1597 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1598 let SPR = spr; 1599} 1600 1601// XFL-Form - MTFSF 1602// This is probably 1.7.9, but I don't have the reference that uses this 1603// numbering scheme... 1604class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1605 InstrItinClass itin, list<dag>pattern> 1606 : I<opcode, OOL, IOL, asmstr, itin> { 1607 bits<8> FM; 1608 bits<5> rT; 1609 1610 bit RC = 0; // set by isDOT 1611 let Pattern = pattern; 1612 1613 let Inst{6} = 0; 1614 let Inst{7-14} = FM; 1615 let Inst{15} = 0; 1616 let Inst{16-20} = rT; 1617 let Inst{21-30} = xo; 1618 let Inst{31} = RC; 1619} 1620 1621class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1622 InstrItinClass itin, list<dag>pattern> 1623 : I<opcode, OOL, IOL, asmstr, itin> { 1624 bit L; 1625 bits<8> FLM; 1626 bit W; 1627 bits<5> FRB; 1628 1629 bit RC = 0; // set by isDOT 1630 let Pattern = pattern; 1631 1632 let Inst{6} = L; 1633 let Inst{7-14} = FLM; 1634 let Inst{15} = W; 1635 let Inst{16-20} = FRB; 1636 let Inst{21-30} = xo; 1637 let Inst{31} = RC; 1638} 1639 1640// 1.7.10 XS-Form - SRADI. 1641class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1642 InstrItinClass itin, list<dag> pattern> 1643 : I<opcode, OOL, IOL, asmstr, itin> { 1644 bits<5> A; 1645 bits<5> RS; 1646 bits<6> SH; 1647 1648 bit RC = 0; // set by isDOT 1649 let Pattern = pattern; 1650 1651 let Inst{6-10} = RS; 1652 let Inst{11-15} = A; 1653 let Inst{16-20} = SH{4,3,2,1,0}; 1654 let Inst{21-29} = xo; 1655 let Inst{30} = SH{5}; 1656 let Inst{31} = RC; 1657} 1658 1659// 1.7.11 XO-Form 1660class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1661 InstrItinClass itin, list<dag> pattern> 1662 : I<opcode, OOL, IOL, asmstr, itin> { 1663 bits<5> RT; 1664 bits<5> RA; 1665 bits<5> RB; 1666 1667 let Pattern = pattern; 1668 1669 bit RC = 0; // set by isDOT 1670 1671 let Inst{6-10} = RT; 1672 let Inst{11-15} = RA; 1673 let Inst{16-20} = RB; 1674 let Inst{21} = oe; 1675 let Inst{22-30} = xo; 1676 let Inst{31} = RC; 1677} 1678 1679class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1680 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1681 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1682 let RB = 0; 1683} 1684 1685// 1.7.12 A-Form 1686class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1687 InstrItinClass itin, list<dag> pattern> 1688 : I<opcode, OOL, IOL, asmstr, itin> { 1689 bits<5> FRT; 1690 bits<5> FRA; 1691 bits<5> FRC; 1692 bits<5> FRB; 1693 1694 let Pattern = pattern; 1695 1696 bit RC = 0; // set by isDOT 1697 1698 let Inst{6-10} = FRT; 1699 let Inst{11-15} = FRA; 1700 let Inst{16-20} = FRB; 1701 let Inst{21-25} = FRC; 1702 let Inst{26-30} = xo; 1703 let Inst{31} = RC; 1704} 1705 1706class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1707 InstrItinClass itin, list<dag> pattern> 1708 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1709 let FRC = 0; 1710} 1711 1712class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1713 InstrItinClass itin, list<dag> pattern> 1714 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1715 let FRB = 0; 1716} 1717 1718class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1719 InstrItinClass itin, list<dag> pattern> 1720 : I<opcode, OOL, IOL, asmstr, itin> { 1721 bits<5> RT; 1722 bits<5> RA; 1723 bits<5> RB; 1724 bits<5> COND; 1725 1726 let Pattern = pattern; 1727 1728 let Inst{6-10} = RT; 1729 let Inst{11-15} = RA; 1730 let Inst{16-20} = RB; 1731 let Inst{21-25} = COND; 1732 let Inst{26-30} = xo; 1733 let Inst{31} = 0; 1734} 1735 1736// Used for QPX 1737class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1738 InstrItinClass itin, list<dag> pattern> 1739 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1740 let FRA = 0; 1741 let FRC = 0; 1742} 1743 1744// 1.7.13 M-Form 1745class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1746 InstrItinClass itin, list<dag> pattern> 1747 : I<opcode, OOL, IOL, asmstr, itin> { 1748 bits<5> RA; 1749 bits<5> RS; 1750 bits<5> RB; 1751 bits<5> MB; 1752 bits<5> ME; 1753 1754 let Pattern = pattern; 1755 1756 bit RC = 0; // set by isDOT 1757 1758 let Inst{6-10} = RS; 1759 let Inst{11-15} = RA; 1760 let Inst{16-20} = RB; 1761 let Inst{21-25} = MB; 1762 let Inst{26-30} = ME; 1763 let Inst{31} = RC; 1764} 1765 1766class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1767 InstrItinClass itin, list<dag> pattern> 1768 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1769} 1770 1771// 1.7.14 MD-Form 1772class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1773 InstrItinClass itin, list<dag> pattern> 1774 : I<opcode, OOL, IOL, asmstr, itin> { 1775 bits<5> RA; 1776 bits<5> RS; 1777 bits<6> SH; 1778 bits<6> MBE; 1779 1780 let Pattern = pattern; 1781 1782 bit RC = 0; // set by isDOT 1783 1784 let Inst{6-10} = RS; 1785 let Inst{11-15} = RA; 1786 let Inst{16-20} = SH{4,3,2,1,0}; 1787 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1788 let Inst{27-29} = xo; 1789 let Inst{30} = SH{5}; 1790 let Inst{31} = RC; 1791} 1792 1793class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1794 InstrItinClass itin, list<dag> pattern> 1795 : I<opcode, OOL, IOL, asmstr, itin> { 1796 bits<5> RA; 1797 bits<5> RS; 1798 bits<5> RB; 1799 bits<6> MBE; 1800 1801 let Pattern = pattern; 1802 1803 bit RC = 0; // set by isDOT 1804 1805 let Inst{6-10} = RS; 1806 let Inst{11-15} = RA; 1807 let Inst{16-20} = RB; 1808 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1809 let Inst{27-30} = xo; 1810 let Inst{31} = RC; 1811} 1812 1813 1814// E-1 VA-Form 1815 1816// VAForm_1 - DACB ordering. 1817class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1818 InstrItinClass itin, list<dag> pattern> 1819 : I<4, OOL, IOL, asmstr, itin> { 1820 bits<5> VD; 1821 bits<5> VA; 1822 bits<5> VC; 1823 bits<5> VB; 1824 1825 let Pattern = pattern; 1826 1827 let Inst{6-10} = VD; 1828 let Inst{11-15} = VA; 1829 let Inst{16-20} = VB; 1830 let Inst{21-25} = VC; 1831 let Inst{26-31} = xo; 1832} 1833 1834// VAForm_1a - DABC ordering. 1835class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1836 InstrItinClass itin, list<dag> pattern> 1837 : I<4, OOL, IOL, asmstr, itin> { 1838 bits<5> VD; 1839 bits<5> VA; 1840 bits<5> VB; 1841 bits<5> VC; 1842 1843 let Pattern = pattern; 1844 1845 let Inst{6-10} = VD; 1846 let Inst{11-15} = VA; 1847 let Inst{16-20} = VB; 1848 let Inst{21-25} = VC; 1849 let Inst{26-31} = xo; 1850} 1851 1852class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1853 InstrItinClass itin, list<dag> pattern> 1854 : I<4, OOL, IOL, asmstr, itin> { 1855 bits<5> VD; 1856 bits<5> VA; 1857 bits<5> VB; 1858 bits<4> SH; 1859 1860 let Pattern = pattern; 1861 1862 let Inst{6-10} = VD; 1863 let Inst{11-15} = VA; 1864 let Inst{16-20} = VB; 1865 let Inst{21} = 0; 1866 let Inst{22-25} = SH; 1867 let Inst{26-31} = xo; 1868} 1869 1870// E-2 VX-Form 1871class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1872 InstrItinClass itin, list<dag> pattern> 1873 : I<4, OOL, IOL, asmstr, itin> { 1874 bits<5> VD; 1875 bits<5> VA; 1876 bits<5> VB; 1877 1878 let Pattern = pattern; 1879 1880 let Inst{6-10} = VD; 1881 let Inst{11-15} = VA; 1882 let Inst{16-20} = VB; 1883 let Inst{21-31} = xo; 1884} 1885 1886class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1887 InstrItinClass itin, list<dag> pattern> 1888 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1889 let VA = VD; 1890 let VB = VD; 1891} 1892 1893 1894class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1895 InstrItinClass itin, list<dag> pattern> 1896 : I<4, OOL, IOL, asmstr, itin> { 1897 bits<5> VD; 1898 bits<5> VB; 1899 1900 let Pattern = pattern; 1901 1902 let Inst{6-10} = VD; 1903 let Inst{11-15} = 0; 1904 let Inst{16-20} = VB; 1905 let Inst{21-31} = xo; 1906} 1907 1908class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1909 InstrItinClass itin, list<dag> pattern> 1910 : I<4, OOL, IOL, asmstr, itin> { 1911 bits<5> VD; 1912 bits<5> IMM; 1913 1914 let Pattern = pattern; 1915 1916 let Inst{6-10} = VD; 1917 let Inst{11-15} = IMM; 1918 let Inst{16-20} = 0; 1919 let Inst{21-31} = xo; 1920} 1921 1922/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1923class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1924 InstrItinClass itin, list<dag> pattern> 1925 : I<4, OOL, IOL, asmstr, itin> { 1926 bits<5> VD; 1927 1928 let Pattern = pattern; 1929 1930 let Inst{6-10} = VD; 1931 let Inst{11-15} = 0; 1932 let Inst{16-20} = 0; 1933 let Inst{21-31} = xo; 1934} 1935 1936/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1937class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1938 InstrItinClass itin, list<dag> pattern> 1939 : I<4, OOL, IOL, asmstr, itin> { 1940 bits<5> VB; 1941 1942 let Pattern = pattern; 1943 1944 let Inst{6-10} = 0; 1945 let Inst{11-15} = 0; 1946 let Inst{16-20} = VB; 1947 let Inst{21-31} = xo; 1948} 1949 1950// e.g. [PO VRT EO VRB XO] 1951class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1952 string asmstr, InstrItinClass itin, list<dag> pattern> 1953 : I<4, OOL, IOL, asmstr, itin> { 1954 bits<5> RD; 1955 bits<5> VB; 1956 1957 let Pattern = pattern; 1958 1959 let Inst{6-10} = RD; 1960 let Inst{11-15} = eo; 1961 let Inst{16-20} = VB; 1962 let Inst{21-31} = xo; 1963} 1964 1965/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 1966class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 1967 InstrItinClass itin, list<dag> pattern> 1968 : I<4, OOL, IOL, asmstr, itin> { 1969 bits<5> VD; 1970 bits<5> VA; 1971 bits<1> ST; 1972 bits<4> SIX; 1973 1974 let Pattern = pattern; 1975 1976 let Inst{6-10} = VD; 1977 let Inst{11-15} = VA; 1978 let Inst{16} = ST; 1979 let Inst{17-20} = SIX; 1980 let Inst{21-31} = xo; 1981} 1982 1983/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 1984class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 1985 InstrItinClass itin, list<dag> pattern> 1986 : I<4, OOL, IOL, asmstr, itin> { 1987 bits<5> VD; 1988 bits<5> VA; 1989 1990 let Pattern = pattern; 1991 1992 let Inst{6-10} = VD; 1993 let Inst{11-15} = VA; 1994 let Inst{16-20} = 0; 1995 let Inst{21-31} = xo; 1996} 1997 1998// E-4 VXR-Form 1999class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2000 InstrItinClass itin, list<dag> pattern> 2001 : I<4, OOL, IOL, asmstr, itin> { 2002 bits<5> VD; 2003 bits<5> VA; 2004 bits<5> VB; 2005 bit RC = 0; 2006 2007 let Pattern = pattern; 2008 2009 let Inst{6-10} = VD; 2010 let Inst{11-15} = VA; 2011 let Inst{16-20} = VB; 2012 let Inst{21} = RC; 2013 let Inst{22-31} = xo; 2014} 2015 2016// VX-Form: [PO VRT EO VRB 1 PS XO] 2017class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2018 dag OOL, dag IOL, string asmstr, 2019 InstrItinClass itin, list<dag> pattern> 2020 : I<4, OOL, IOL, asmstr, itin> { 2021 bits<5> VD; 2022 bits<5> VB; 2023 bit PS; 2024 2025 let Pattern = pattern; 2026 2027 let Inst{6-10} = VD; 2028 let Inst{11-15} = eo; 2029 let Inst{16-20} = VB; 2030 let Inst{21} = 1; 2031 let Inst{22} = PS; 2032 let Inst{23-31} = xo; 2033} 2034 2035// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2036class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2037 InstrItinClass itin, list<dag> pattern> 2038 : I<4, OOL, IOL, asmstr, itin> { 2039 bits<5> VD; 2040 bits<5> VA; 2041 bits<5> VB; 2042 bit PS; 2043 2044 let Pattern = pattern; 2045 2046 let Inst{6-10} = VD; 2047 let Inst{11-15} = VA; 2048 let Inst{16-20} = VB; 2049 let Inst{21} = 1; 2050 let Inst{22} = PS; 2051 let Inst{23-31} = xo; 2052} 2053 2054// Z23-Form (used by QPX) 2055class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2056 InstrItinClass itin, list<dag> pattern> 2057 : I<opcode, OOL, IOL, asmstr, itin> { 2058 bits<5> FRT; 2059 bits<5> FRA; 2060 bits<5> FRB; 2061 bits<2> idx; 2062 2063 let Pattern = pattern; 2064 2065 bit RC = 0; // set by isDOT 2066 2067 let Inst{6-10} = FRT; 2068 let Inst{11-15} = FRA; 2069 let Inst{16-20} = FRB; 2070 let Inst{21-22} = idx; 2071 let Inst{23-30} = xo; 2072 let Inst{31} = RC; 2073} 2074 2075class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2076 InstrItinClass itin, list<dag> pattern> 2077 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 2078 let FRB = 0; 2079} 2080 2081class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2082 InstrItinClass itin, list<dag> pattern> 2083 : I<opcode, OOL, IOL, asmstr, itin> { 2084 bits<5> FRT; 2085 bits<12> idx; 2086 2087 let Pattern = pattern; 2088 2089 bit RC = 0; // set by isDOT 2090 2091 let Inst{6-10} = FRT; 2092 let Inst{11-22} = idx; 2093 let Inst{23-30} = xo; 2094 let Inst{31} = RC; 2095} 2096 2097//===----------------------------------------------------------------------===// 2098class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2099 : I<0, OOL, IOL, asmstr, NoItinerary> { 2100 let isCodeGenOnly = 1; 2101 let PPC64 = 0; 2102 let Pattern = pattern; 2103 let Inst{31-0} = 0; 2104 let hasNoSchedulingInfo = 1; 2105} 2106