1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 /// Indicate that the VSX instruction is to use VSX numbering/encoding. 42 /// Since ISA 3.0, there are scalar instructions that use the upper 43 /// half of the VSX register set only. Rather than adding further complexity 44 /// to the register class set, the VSX registers just include the Altivec 45 /// registers and this flag decides the numbering to be used for them. 46 bits<1> UseVSXReg = 0; 47 let TSFlags{6} = UseVSXReg; 48 49 // Indicate that this instruction is of type X-Form Load or Store 50 bits<1> XFormMemOp = 0; 51 let TSFlags{7} = XFormMemOp; 52 53 // Fields used for relation models. 54 string BaseName = ""; 55 56 // For cases where multiple instruction definitions really represent the 57 // same underlying instruction but with one definition for 64-bit arguments 58 // and one for 32-bit arguments, this bit breaks the degeneracy between 59 // the two forms and allows TableGen to generate mapping tables. 60 bit Interpretation64Bit = 0; 61} 62 63class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 64class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 65class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 66class PPC970_MicroCode; 67 68class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 69class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 70class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 71class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 72class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 73class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 74class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 75class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 76 77class UseVSXReg { bits<1> UseVSXReg = 1; } 78class XFormMemOp { bits<1> XFormMemOp = 1; } 79 80// Two joined instructions; used to emit two adjacent instructions as one. 81// The itinerary from the first instruction is used for scheduling and 82// classification. 83class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 84 InstrItinClass itin> 85 : Instruction { 86 field bits<64> Inst; 87 field bits<64> SoftFail = 0; 88 let Size = 8; 89 90 bit PPC64 = 0; // Default value, override with isPPC64 91 92 let Namespace = "PPC"; 93 let Inst{0-5} = opcode1; 94 let Inst{32-37} = opcode2; 95 let OutOperandList = OOL; 96 let InOperandList = IOL; 97 let AsmString = asmstr; 98 let Itinerary = itin; 99 100 bits<1> PPC970_First = 0; 101 bits<1> PPC970_Single = 0; 102 bits<1> PPC970_Cracked = 0; 103 bits<3> PPC970_Unit = 0; 104 105 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 106 /// these must be reflected there! See comments there for what these are. 107 let TSFlags{0} = PPC970_First; 108 let TSFlags{1} = PPC970_Single; 109 let TSFlags{2} = PPC970_Cracked; 110 let TSFlags{5-3} = PPC970_Unit; 111 112 // Fields used for relation models. 113 string BaseName = ""; 114 bit Interpretation64Bit = 0; 115} 116 117// Base class for all X-Form memory instructions 118class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 119 InstrItinClass itin> 120 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 121 122// 1.7.1 I-Form 123class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 124 InstrItinClass itin, list<dag> pattern> 125 : I<opcode, OOL, IOL, asmstr, itin> { 126 let Pattern = pattern; 127 bits<24> LI; 128 129 let Inst{6-29} = LI; 130 let Inst{30} = aa; 131 let Inst{31} = lk; 132} 133 134// 1.7.2 B-Form 135class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 136 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 137 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 138 bits<3> CR; 139 bits<14> BD; 140 141 bits<5> BI; 142 let BI{0-1} = BIBO{5-6}; 143 let BI{2-4} = CR{0-2}; 144 145 let Inst{6-10} = BIBO{4-0}; 146 let Inst{11-15} = BI; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 153 string asmstr> 154 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 155 let BIBO{4-0} = bo; 156 let BIBO{6-5} = 0; 157 let CR = 0; 158} 159 160class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 161 dag OOL, dag IOL, string asmstr> 162 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 163 bits<14> BD; 164 165 let Inst{6-10} = bo; 166 let Inst{11-15} = bi; 167 let Inst{16-29} = BD; 168 let Inst{30} = aa; 169 let Inst{31} = lk; 170} 171 172class BForm_3<bits<6> opcode, bit aa, bit lk, 173 dag OOL, dag IOL, string asmstr> 174 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 175 bits<5> BO; 176 bits<5> BI; 177 bits<14> BD; 178 179 let Inst{6-10} = BO; 180 let Inst{11-15} = BI; 181 let Inst{16-29} = BD; 182 let Inst{30} = aa; 183 let Inst{31} = lk; 184} 185 186class BForm_3_at<bits<6> opcode, bit aa, bit lk, 187 dag OOL, dag IOL, string asmstr> 188 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 189 bits<5> BO; 190 bits<2> at; 191 bits<5> BI; 192 bits<14> BD; 193 194 let Inst{6-8} = BO{4-2}; 195 let Inst{9-10} = at; 196 let Inst{11-15} = BI; 197 let Inst{16-29} = BD; 198 let Inst{30} = aa; 199 let Inst{31} = lk; 200} 201 202class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 203 dag OOL, dag IOL, string asmstr> 204 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 205 bits<5> BI; 206 bits<14> BD; 207 208 let Inst{6-10} = bo; 209 let Inst{11-15} = BI; 210 let Inst{16-29} = BD; 211 let Inst{30} = aa; 212 let Inst{31} = lk; 213} 214 215// 1.7.3 SC-Form 216class SCForm<bits<6> opcode, bits<1> xo, 217 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 218 list<dag> pattern> 219 : I<opcode, OOL, IOL, asmstr, itin> { 220 bits<7> LEV; 221 222 let Pattern = pattern; 223 224 let Inst{20-26} = LEV; 225 let Inst{30} = xo; 226} 227 228// 1.7.4 D-Form 229class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 230 InstrItinClass itin, list<dag> pattern> 231 : I<opcode, OOL, IOL, asmstr, itin> { 232 bits<5> A; 233 bits<5> B; 234 bits<16> C; 235 236 let Pattern = pattern; 237 238 let Inst{6-10} = A; 239 let Inst{11-15} = B; 240 let Inst{16-31} = C; 241} 242 243class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 244 InstrItinClass itin, list<dag> pattern> 245 : I<opcode, OOL, IOL, asmstr, itin> { 246 bits<5> A; 247 bits<21> Addr; 248 249 let Pattern = pattern; 250 251 let Inst{6-10} = A; 252 let Inst{11-15} = Addr{20-16}; // Base Reg 253 let Inst{16-31} = Addr{15-0}; // Displacement 254} 255 256class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 257 InstrItinClass itin, list<dag> pattern> 258 : I<opcode, OOL, IOL, asmstr, itin> { 259 bits<5> A; 260 bits<16> C; 261 bits<5> B; 262 263 let Pattern = pattern; 264 265 let Inst{6-10} = A; 266 let Inst{11-15} = B; 267 let Inst{16-31} = C; 268} 269 270 271class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 274 275 // Even though ADDICo does not really have an RC bit, provide 276 // the declaration of one here so that isDOT has something to set. 277 bit RC = 0; 278} 279 280class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 281 InstrItinClass itin, list<dag> pattern> 282 : I<opcode, OOL, IOL, asmstr, itin> { 283 bits<5> A; 284 bits<16> B; 285 286 let Pattern = pattern; 287 288 let Inst{6-10} = A; 289 let Inst{11-15} = 0; 290 let Inst{16-31} = B; 291} 292 293class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 294 InstrItinClass itin, list<dag> pattern> 295 : I<opcode, OOL, IOL, asmstr, itin> { 296 bits<5> B; 297 bits<5> A; 298 bits<16> C; 299 300 let Pattern = pattern; 301 302 let Inst{6-10} = A; 303 let Inst{11-15} = B; 304 let Inst{16-31} = C; 305} 306 307class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 308 InstrItinClass itin, list<dag> pattern> 309 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 310 let A = 0; 311 let Addr = 0; 312} 313 314class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 315 string asmstr, InstrItinClass itin, 316 list<dag> pattern> 317 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 318 let A = R; 319 let B = R; 320 let C = 0; 321} 322 323class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 324 dag OOL, dag IOL, string asmstr, 325 InstrItinClass itin, list<dag> pattern> 326 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 327 bits<5> A; 328 bits<21> Addr; 329 330 let Pattern = pattern; 331 bits<24> LI; 332 333 let Inst{6-29} = LI; 334 let Inst{30} = aa; 335 let Inst{31} = lk; 336 337 let Inst{38-42} = A; 338 let Inst{43-47} = Addr{20-16}; // Base Reg 339 let Inst{48-63} = Addr{15-0}; // Displacement 340} 341 342// This is used to emit BL8+NOP. 343class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 344 dag OOL, dag IOL, string asmstr, 345 InstrItinClass itin, list<dag> pattern> 346 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 347 OOL, IOL, asmstr, itin, pattern> { 348 let A = 0; 349 let Addr = 0; 350} 351 352class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 353 InstrItinClass itin> 354 : I<opcode, OOL, IOL, asmstr, itin> { 355 bits<3> BF; 356 bits<1> L; 357 bits<5> RA; 358 bits<16> I; 359 360 let Inst{6-8} = BF; 361 let Inst{9} = 0; 362 let Inst{10} = L; 363 let Inst{11-15} = RA; 364 let Inst{16-31} = I; 365} 366 367class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 370 let L = PPC64; 371} 372 373class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 374 InstrItinClass itin> 375 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 376 377class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 378 InstrItinClass itin> 379 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 380 let L = PPC64; 381} 382 383 384// 1.7.5 DS-Form 385class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 386 InstrItinClass itin, list<dag> pattern> 387 : I<opcode, OOL, IOL, asmstr, itin> { 388 bits<5> RST; 389 bits<19> DS_RA; 390 391 let Pattern = pattern; 392 393 let Inst{6-10} = RST; 394 let Inst{11-15} = DS_RA{18-14}; // Register # 395 let Inst{16-29} = DS_RA{13-0}; // Displacement. 396 let Inst{30-31} = xo; 397} 398 399// ISA V3.0B 1.6.6 DX-Form 400class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 401 InstrItinClass itin, list<dag> pattern> 402 : I<opcode, OOL, IOL, asmstr, itin> { 403 bits<5> RT; 404 bits<16> D; 405 406 let Pattern = pattern; 407 408 let Inst{6-10} = RT; 409 let Inst{11-15} = D{5-1}; // d1 410 let Inst{16-25} = D{15-6}; // d0 411 let Inst{26-30} = xo; 412 let Inst{31} = D{0}; // d2 413} 414 415// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 416class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 417 string asmstr, InstrItinClass itin, list<dag> pattern> 418 : I<opcode, OOL, IOL, asmstr, itin> { 419 bits<6> XT; 420 bits<17> DS_RA; 421 422 let Pattern = pattern; 423 424 let Inst{6-10} = XT{4-0}; 425 let Inst{11-15} = DS_RA{16-12}; // Register # 426 let Inst{16-27} = DS_RA{11-0}; // Displacement. 427 let Inst{28} = XT{5}; 428 let Inst{29-31} = xo; 429} 430 431// 1.7.6 X-Form 432class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 433 InstrItinClass itin, list<dag> pattern> 434 : I<opcode, OOL, IOL, asmstr, itin> { 435 bits<5> RST; 436 bits<5> A; 437 bits<5> B; 438 439 let Pattern = pattern; 440 441 bit RC = 0; // set by isDOT 442 443 let Inst{6-10} = RST; 444 let Inst{11-15} = A; 445 let Inst{16-20} = B; 446 let Inst{21-30} = xo; 447 let Inst{31} = RC; 448} 449 450class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 451 string asmstr, InstrItinClass itin, 452 list<dag> pattern> 453 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 454 455class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 456 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 457 let RST = 0; 458} 459 460class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 461 InstrItinClass itin> 462 : I<opcode, OOL, IOL, asmstr, itin> { 463 let Inst{21-30} = xo; 464} 465 466// This is the same as XForm_base_r3xo, but the first two operands are swapped 467// when code is emitted. 468class XForm_base_r3xo_swapped 469 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 470 InstrItinClass itin> 471 : I<opcode, OOL, IOL, asmstr, itin> { 472 bits<5> A; 473 bits<5> RST; 474 bits<5> B; 475 476 bit RC = 0; // set by isDOT 477 478 let Inst{6-10} = RST; 479 let Inst{11-15} = A; 480 let Inst{16-20} = B; 481 let Inst{21-30} = xo; 482 let Inst{31} = RC; 483} 484 485 486class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 487 InstrItinClass itin, list<dag> pattern> 488 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 489 490class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 491 InstrItinClass itin, list<dag> pattern> 492 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 493 494class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 495 InstrItinClass itin, list<dag> pattern> 496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 497 let RST = 0; 498} 499 500class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 501 InstrItinClass itin, list<dag> pattern> 502 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 503 let A = 0; 504 let B = 0; 505} 506 507class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 508 InstrItinClass itin, list<dag> pattern> 509 : I<opcode, OOL, IOL, asmstr, itin> { 510 bits<5> RST; 511 bits<5> A; 512 bits<1> WS; 513 514 let Pattern = pattern; 515 516 let Inst{6-10} = RST; 517 let Inst{11-15} = A; 518 let Inst{20} = WS; 519 let Inst{21-30} = xo; 520 let Inst{31} = 0; 521} 522 523class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 526 let Pattern = pattern; 527} 528 529class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 530 InstrItinClass itin, list<dag> pattern> 531 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 532 533class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin, list<dag> pattern> 535 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 536 537class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin, list<dag> pattern> 539 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 540 let Pattern = pattern; 541} 542 543class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 544 InstrItinClass itin, list<dag> pattern> 545 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 546 let B = 0; 547 let Pattern = pattern; 548} 549 550class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 551 InstrItinClass itin> 552 : I<opcode, OOL, IOL, asmstr, itin> { 553 bits<3> BF; 554 bits<1> L; 555 bits<5> RA; 556 bits<5> RB; 557 558 let Inst{6-8} = BF; 559 let Inst{9} = 0; 560 let Inst{10} = L; 561 let Inst{11-15} = RA; 562 let Inst{16-20} = RB; 563 let Inst{21-30} = xo; 564 let Inst{31} = 0; 565} 566 567class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 568 InstrItinClass itin> 569 : I<opcode, OOL, IOL, asmstr, itin> { 570 bits<4> CT; 571 bits<5> RA; 572 bits<5> RB; 573 574 let Inst{6} = 0; 575 let Inst{7-10} = CT; 576 let Inst{11-15} = RA; 577 let Inst{16-20} = RB; 578 let Inst{21-30} = xo; 579 let Inst{31} = 0; 580} 581 582class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 583 InstrItinClass itin> 584 : I<opcode, OOL, IOL, asmstr, itin> { 585 bits<5> RS; 586 bits<4> SR; 587 588 let Inst{6-10} = RS; 589 let Inst{12-15} = SR; 590 let Inst{21-30} = xo; 591} 592 593class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 594 InstrItinClass itin> 595 : I<opcode, OOL, IOL, asmstr, itin> { 596 bits<5> MO; 597 598 let Inst{6-10} = MO; 599 let Inst{21-30} = xo; 600} 601 602class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 603 InstrItinClass itin> 604 : I<opcode, OOL, IOL, asmstr, itin> { 605 bits<5> RS; 606 bits<5> RB; 607 608 let Inst{6-10} = RS; 609 let Inst{16-20} = RB; 610 let Inst{21-30} = xo; 611} 612 613class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 614 InstrItinClass itin> 615 : I<opcode, OOL, IOL, asmstr, itin> { 616 bits<5> RS; 617 bits<1> L; 618 619 let Inst{6-10} = RS; 620 let Inst{15} = L; 621 let Inst{21-30} = xo; 622} 623 624class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 625 InstrItinClass itin> 626 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 627 let L = PPC64; 628} 629 630class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 631 InstrItinClass itin> 632 : I<opcode, OOL, IOL, asmstr, itin> { 633 bits<3> BF; 634 bits<5> FRA; 635 bits<5> FRB; 636 637 let Inst{6-8} = BF; 638 let Inst{9-10} = 0; 639 let Inst{11-15} = FRA; 640 let Inst{16-20} = FRB; 641 let Inst{21-30} = xo; 642 let Inst{31} = 0; 643} 644 645class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 646 InstrItinClass itin> 647 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 648 let FRA = 0; 649} 650 651// Used for QPX 652class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 653 InstrItinClass itin, list<dag> pattern> 654 : I<opcode, OOL, IOL, asmstr, itin> { 655 bits<5> FRT; 656 bits<5> FRA; 657 bits<5> FRB; 658 659 let Pattern = pattern; 660 661 let Inst{6-10} = FRT; 662 let Inst{11-15} = FRA; 663 let Inst{16-20} = FRB; 664 let Inst{21-30} = xo; 665 let Inst{31} = 0; 666} 667 668class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 669 InstrItinClass itin, list<dag> pattern> 670 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 671 let FRA = 0; 672} 673 674class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 675 InstrItinClass itin, list<dag> pattern> 676 : I<opcode, OOL, IOL, asmstr, itin> { 677 bits<5> FRT; 678 bits<5> FRA; 679 bits<5> FRB; 680 bits<4> tttt; 681 682 let Pattern = pattern; 683 684 let Inst{6-10} = FRT; 685 let Inst{11-15} = FRA; 686 let Inst{16-20} = FRB; 687 let Inst{21-24} = tttt; 688 let Inst{25-30} = xo; 689 let Inst{31} = 0; 690} 691 692class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 693 InstrItinClass itin, list<dag> pattern> 694 : I<opcode, OOL, IOL, asmstr, itin> { 695 let Pattern = pattern; 696 let Inst{6-10} = 31; 697 let Inst{11-15} = 0; 698 let Inst{16-20} = 0; 699 let Inst{21-30} = xo; 700 let Inst{31} = 0; 701} 702 703class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 704 string asmstr, InstrItinClass itin, list<dag> pattern> 705 : I<opcode, OOL, IOL, asmstr, itin> { 706 bits<2> L; 707 708 let Pattern = pattern; 709 let Inst{6-8} = 0; 710 let Inst{9-10} = L; 711 let Inst{11-15} = 0; 712 let Inst{16-20} = 0; 713 let Inst{21-30} = xo; 714 let Inst{31} = 0; 715} 716 717class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 718 string asmstr, InstrItinClass itin, list<dag> pattern> 719 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 720 let L = 0; 721} 722 723class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 724 InstrItinClass itin, list<dag> pattern> 725 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 726} 727 728class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 729 string asmstr, InstrItinClass itin, list<dag> pattern> 730 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 731} 732 733class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 734 InstrItinClass itin, list<dag> pattern> 735 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 736 let A = 0; 737} 738 739class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 740 string asmstr, InstrItinClass itin, list<dag> pattern> 741 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 742} 743 744class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 745 InstrItinClass itin, list<dag> pattern> 746 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 747} 748 749// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 750// numbers presumably relates to some document, but I haven't found it. 751class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 752 InstrItinClass itin, list<dag> pattern> 753 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 754 let Pattern = pattern; 755 756 bit RC = 0; // set by isDOT 757 758 let Inst{6-10} = RST; 759 let Inst{11-20} = 0; 760 let Inst{21-30} = xo; 761 let Inst{31} = RC; 762} 763class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 764 InstrItinClass itin, list<dag> pattern> 765 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 766 let Pattern = pattern; 767 bits<5> FM; 768 769 bit RC = 0; // set by isDOT 770 771 let Inst{6-10} = FM; 772 let Inst{11-20} = 0; 773 let Inst{21-30} = xo; 774 let Inst{31} = RC; 775} 776 777class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 778 InstrItinClass itin> 779 : I<opcode, OOL, IOL, asmstr, itin> { 780 bits<5> RT; 781 bits<3> BFA; 782 783 let Inst{6-10} = RT; 784 let Inst{11-13} = BFA; 785 let Inst{14-15} = 0; 786 let Inst{16-20} = 0; 787 let Inst{21-30} = xo; 788 let Inst{31} = 0; 789} 790 791class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 792 InstrItinClass itin> 793 : I<opcode, OOL, IOL, asmstr, itin> { 794 bits<5> RT; 795 bits<2> L; 796 797 let Inst{6-10} = RT; 798 let Inst{11-13} = 0; 799 let Inst{14-15} = L; 800 let Inst{16-20} = 0; 801 let Inst{21-30} = xo; 802 let Inst{31} = 0; 803} 804 805class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 806 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 807 list<dag> pattern> 808 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 809 let Pattern = pattern; 810 811 let Inst{6-10} = RST; 812 let Inst{11-12} = xo1; 813 let Inst{13-15} = xo2; 814 let Inst{16-20} = 0; 815 let Inst{21-30} = xo; 816 let Inst{31} = 0; 817} 818 819class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 820 bits<10> xo, dag OOL, dag IOL, string asmstr, 821 InstrItinClass itin, list<dag> pattern> 822 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 823 let Pattern = pattern; 824 bits<5> FRB; 825 826 let Inst{6-10} = RST; 827 let Inst{11-12} = xo1; 828 let Inst{13-15} = xo2; 829 let Inst{16-20} = FRB; 830 let Inst{21-30} = xo; 831 let Inst{31} = 0; 832} 833 834class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 835 bits<10> xo, dag OOL, dag IOL, string asmstr, 836 InstrItinClass itin, list<dag> pattern> 837 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 838 let Pattern = pattern; 839 bits<3> DRM; 840 841 let Inst{6-10} = RST; 842 let Inst{11-12} = xo1; 843 let Inst{13-15} = xo2; 844 let Inst{16-17} = 0; 845 let Inst{18-20} = DRM; 846 let Inst{21-30} = xo; 847 let Inst{31} = 0; 848} 849 850class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 851 bits<10> xo, dag OOL, dag IOL, string asmstr, 852 InstrItinClass itin, list<dag> pattern> 853 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 854 let Pattern = pattern; 855 bits<2> RM; 856 857 let Inst{6-10} = RST; 858 let Inst{11-12} = xo1; 859 let Inst{13-15} = xo2; 860 let Inst{16-18} = 0; 861 let Inst{19-20} = RM; 862 let Inst{21-30} = xo; 863 let Inst{31} = 0; 864} 865 866 867class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 868 InstrItinClass itin, list<dag> pattern> 869 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 870 let RST = 0; 871 let A = 0; 872 let B = 0; 873} 874 875class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 876 InstrItinClass itin, list<dag> pattern> 877 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 878 let RST = 0; 879 let A = 0; 880} 881 882class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 883 string asmstr, InstrItinClass itin, list<dag> pattern> 884 : I<opcode, OOL, IOL, asmstr, itin> { 885 bit R; 886 887 bit RC = 1; 888 889 let Inst{6-9} = 0; 890 let Inst{10} = R; 891 let Inst{11-20} = 0; 892 let Inst{21-30} = xo; 893 let Inst{31} = RC; 894} 895 896class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 897 string asmstr, InstrItinClass itin, list<dag> pattern> 898 : I<opcode, OOL, IOL, asmstr, itin> { 899 bit A; 900 901 bit RC = 1; 902 903 let Inst{6} = A; 904 let Inst{7-20} = 0; 905 let Inst{21-30} = xo; 906 let Inst{31} = RC; 907} 908 909class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 910 InstrItinClass itin, list<dag> pattern> 911 : I<opcode, OOL, IOL, asmstr, itin> { 912 bit L; 913 914 bit RC = 0; // set by isDOT 915 916 let Inst{7-9} = 0; 917 let Inst{10} = L; 918 let Inst{11-20} = 0; 919 let Inst{21-30} = xo; 920 let Inst{31} = RC; 921} 922 923class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 924 InstrItinClass itin, list<dag> pattern> 925 : I<opcode, OOL, IOL, asmstr, itin> { 926 bits<3> BF; 927 928 bit RC = 0; 929 930 let Inst{6-8} = BF; 931 let Inst{9-20} = 0; 932 let Inst{21-30} = xo; 933 let Inst{31} = RC; 934} 935 936// [PO RT RA RB XO /] 937class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 938 string asmstr, InstrItinClass itin, list<dag> pattern> 939 : I<opcode, OOL, IOL, asmstr, itin> { 940 bits<3> BF; 941 bits<1> L; 942 bits<5> RA; 943 bits<5> RB; 944 945 let Pattern = pattern; 946 947 let Inst{6-8} = BF; 948 let Inst{9} = 0; 949 let Inst{10} = L; 950 let Inst{11-15} = RA; 951 let Inst{16-20} = RB; 952 let Inst{21-30} = xo; 953 let Inst{31} = 0; 954} 955 956// Same as XForm_17 but with GPR's and new naming convention 957class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 958 string asmstr, InstrItinClass itin, list<dag> pattern> 959 : I<opcode, OOL, IOL, asmstr, itin> { 960 bits<3> BF; 961 bits<5> RA; 962 bits<5> RB; 963 964 let Pattern = pattern; 965 966 let Inst{6-8} = BF; 967 let Inst{9-10} = 0; 968 let Inst{11-15} = RA; 969 let Inst{16-20} = RB; 970 let Inst{21-30} = xo; 971 let Inst{31} = 0; 972} 973 974// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 975class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 976 string asmstr, InstrItinClass itin, list<dag> pattern> 977 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 978 let A = xo2; 979} 980 981class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 982 string asmstr, InstrItinClass itin, list<dag> pattern> 983 : I<opcode, OOL, IOL, asmstr, itin> { 984 bits<3> BF; 985 bits<7> DCMX; 986 bits<5> VB; 987 988 let Pattern = pattern; 989 990 let Inst{6-8} = BF; 991 let Inst{9-15} = DCMX; 992 let Inst{16-20} = VB; 993 let Inst{21-30} = xo; 994 let Inst{31} = 0; 995} 996 997class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 998 string asmstr, InstrItinClass itin, list<dag> pattern> 999 : I<opcode, OOL, IOL, asmstr, itin> { 1000 bits<6> XT; 1001 bits<8> IMM8; 1002 1003 let Pattern = pattern; 1004 1005 let Inst{6-10} = XT{4-0}; 1006 let Inst{11-12} = 0; 1007 let Inst{13-20} = IMM8; 1008 let Inst{21-30} = xo; 1009 let Inst{31} = XT{5}; 1010} 1011 1012// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1013// to specify an SDAG pattern for matching. 1014class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1015 string asmstr, InstrItinClass itin> 1016 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1017} 1018 1019class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1020 InstrItinClass itin> 1021 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1022 let FRA = 0; 1023 let FRB = 0; 1024} 1025 1026// [PO /// L RA RB XO /] 1027class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1028 string asmstr, InstrItinClass itin, list<dag> pattern> 1029 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1030 let BF = 0; 1031 let Pattern = pattern; 1032 1033 bit RC = 0; 1034 let Inst{31} = RC; 1035} 1036 1037// XX*-Form (VSX) 1038class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1039 InstrItinClass itin, list<dag> pattern> 1040 : I<opcode, OOL, IOL, asmstr, itin> { 1041 bits<6> XT; 1042 bits<5> A; 1043 bits<5> B; 1044 1045 let Pattern = pattern; 1046 1047 let Inst{6-10} = XT{4-0}; 1048 let Inst{11-15} = A; 1049 let Inst{16-20} = B; 1050 let Inst{21-30} = xo; 1051 let Inst{31} = XT{5}; 1052} 1053 1054class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1055 string asmstr, InstrItinClass itin, list<dag> pattern> 1056 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1057 1058class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1059 string asmstr, InstrItinClass itin, list<dag> pattern> 1060 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1061 let B = 0; 1062} 1063 1064class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1065 InstrItinClass itin, list<dag> pattern> 1066 : I<opcode, OOL, IOL, asmstr, itin> { 1067 bits<6> XT; 1068 bits<6> XB; 1069 1070 let Pattern = pattern; 1071 1072 let Inst{6-10} = XT{4-0}; 1073 let Inst{11-15} = 0; 1074 let Inst{16-20} = XB{4-0}; 1075 let Inst{21-29} = xo; 1076 let Inst{30} = XB{5}; 1077 let Inst{31} = XT{5}; 1078} 1079 1080class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1081 InstrItinClass itin, list<dag> pattern> 1082 : I<opcode, OOL, IOL, asmstr, itin> { 1083 bits<3> CR; 1084 bits<6> XB; 1085 1086 let Pattern = pattern; 1087 1088 let Inst{6-8} = CR; 1089 let Inst{9-15} = 0; 1090 let Inst{16-20} = XB{4-0}; 1091 let Inst{21-29} = xo; 1092 let Inst{30} = XB{5}; 1093 let Inst{31} = 0; 1094} 1095 1096class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1097 InstrItinClass itin, list<dag> pattern> 1098 : I<opcode, OOL, IOL, asmstr, itin> { 1099 bits<6> XT; 1100 bits<6> XB; 1101 bits<2> D; 1102 1103 let Pattern = pattern; 1104 1105 let Inst{6-10} = XT{4-0}; 1106 let Inst{11-13} = 0; 1107 let Inst{14-15} = D; 1108 let Inst{16-20} = XB{4-0}; 1109 let Inst{21-29} = xo; 1110 let Inst{30} = XB{5}; 1111 let Inst{31} = XT{5}; 1112} 1113 1114class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1115 string asmstr, InstrItinClass itin, list<dag> pattern> 1116 : I<opcode, OOL, IOL, asmstr, itin> { 1117 bits<6> XT; 1118 bits<6> XB; 1119 bits<5> UIM5; 1120 1121 let Pattern = pattern; 1122 1123 let Inst{6-10} = XT{4-0}; 1124 let Inst{11-15} = UIM5; 1125 let Inst{16-20} = XB{4-0}; 1126 let Inst{21-29} = xo; 1127 let Inst{30} = XB{5}; 1128 let Inst{31} = XT{5}; 1129} 1130 1131// [PO T XO B XO BX /] 1132class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1133 string asmstr, InstrItinClass itin, list<dag> pattern> 1134 : I<opcode, OOL, IOL, asmstr, itin> { 1135 bits<5> RT; 1136 bits<6> XB; 1137 1138 let Pattern = pattern; 1139 1140 let Inst{6-10} = RT; 1141 let Inst{11-15} = xo2; 1142 let Inst{16-20} = XB{4-0}; 1143 let Inst{21-29} = xo; 1144 let Inst{30} = XB{5}; 1145 let Inst{31} = 0; 1146} 1147 1148// [PO T XO B XO BX TX] 1149class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1150 string asmstr, InstrItinClass itin, list<dag> pattern> 1151 : I<opcode, OOL, IOL, asmstr, itin> { 1152 bits<6> XT; 1153 bits<6> XB; 1154 1155 let Pattern = pattern; 1156 1157 let Inst{6-10} = XT{4-0}; 1158 let Inst{11-15} = xo2; 1159 let Inst{16-20} = XB{4-0}; 1160 let Inst{21-29} = xo; 1161 let Inst{30} = XB{5}; 1162 let Inst{31} = XT{5}; 1163} 1164 1165class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1166 string asmstr, InstrItinClass itin, list<dag> pattern> 1167 : I<opcode, OOL, IOL, asmstr, itin> { 1168 bits<3> BF; 1169 bits<7> DCMX; 1170 bits<6> XB; 1171 1172 let Pattern = pattern; 1173 1174 let Inst{6-8} = BF; 1175 let Inst{9-15} = DCMX; 1176 let Inst{16-20} = XB{4-0}; 1177 let Inst{21-29} = xo; 1178 let Inst{30} = XB{5}; 1179 let Inst{31} = 0; 1180} 1181 1182class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1183 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1184 list<dag> pattern> 1185 : I<opcode, OOL, IOL, asmstr, itin> { 1186 bits<6> XT; 1187 bits<7> DCMX; 1188 bits<6> XB; 1189 1190 let Pattern = pattern; 1191 1192 let Inst{6-10} = XT{4-0}; 1193 let Inst{11-15} = DCMX{4-0}; 1194 let Inst{16-20} = XB{4-0}; 1195 let Inst{21-24} = xo1; 1196 let Inst{25} = DCMX{5}; 1197 let Inst{26-28} = xo2; 1198 let Inst{29} = DCMX{6}; 1199 let Inst{30} = XB{5}; 1200 let Inst{31} = XT{5}; 1201} 1202 1203class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1204 InstrItinClass itin, list<dag> pattern> 1205 : I<opcode, OOL, IOL, asmstr, itin> { 1206 bits<6> XT; 1207 bits<6> XA; 1208 bits<6> XB; 1209 1210 let Pattern = pattern; 1211 1212 let Inst{6-10} = XT{4-0}; 1213 let Inst{11-15} = XA{4-0}; 1214 let Inst{16-20} = XB{4-0}; 1215 let Inst{21-28} = xo; 1216 let Inst{29} = XA{5}; 1217 let Inst{30} = XB{5}; 1218 let Inst{31} = XT{5}; 1219} 1220 1221class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1222 InstrItinClass itin, list<dag> pattern> 1223 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1224 let XA = XT; 1225 let XB = XT; 1226} 1227 1228class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1229 InstrItinClass itin, list<dag> pattern> 1230 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1231 let XB = XT; 1232 let XA = XT; 1233} 1234 1235class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1236 InstrItinClass itin, list<dag> pattern> 1237 : I<opcode, OOL, IOL, asmstr, itin> { 1238 bits<3> CR; 1239 bits<6> XA; 1240 bits<6> XB; 1241 1242 let Pattern = pattern; 1243 1244 let Inst{6-8} = CR; 1245 let Inst{9-10} = 0; 1246 let Inst{11-15} = XA{4-0}; 1247 let Inst{16-20} = XB{4-0}; 1248 let Inst{21-28} = xo; 1249 let Inst{29} = XA{5}; 1250 let Inst{30} = XB{5}; 1251 let Inst{31} = 0; 1252} 1253 1254class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1255 InstrItinClass itin, list<dag> pattern> 1256 : I<opcode, OOL, IOL, asmstr, itin> { 1257 bits<6> XT; 1258 bits<6> XA; 1259 bits<6> XB; 1260 bits<2> D; 1261 1262 let Pattern = pattern; 1263 1264 let Inst{6-10} = XT{4-0}; 1265 let Inst{11-15} = XA{4-0}; 1266 let Inst{16-20} = XB{4-0}; 1267 let Inst{21} = 0; 1268 let Inst{22-23} = D; 1269 let Inst{24-28} = xo; 1270 let Inst{29} = XA{5}; 1271 let Inst{30} = XB{5}; 1272 let Inst{31} = XT{5}; 1273} 1274 1275class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1276 InstrItinClass itin, list<dag> pattern> 1277 : I<opcode, OOL, IOL, asmstr, itin> { 1278 bits<6> XT; 1279 bits<6> XA; 1280 bits<6> XB; 1281 1282 let Pattern = pattern; 1283 1284 bit RC = 0; // set by isDOT 1285 1286 let Inst{6-10} = XT{4-0}; 1287 let Inst{11-15} = XA{4-0}; 1288 let Inst{16-20} = XB{4-0}; 1289 let Inst{21} = RC; 1290 let Inst{22-28} = xo; 1291 let Inst{29} = XA{5}; 1292 let Inst{30} = XB{5}; 1293 let Inst{31} = XT{5}; 1294} 1295 1296class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1297 InstrItinClass itin, list<dag> pattern> 1298 : I<opcode, OOL, IOL, asmstr, itin> { 1299 bits<6> XT; 1300 bits<6> XA; 1301 bits<6> XB; 1302 bits<6> XC; 1303 1304 let Pattern = pattern; 1305 1306 let Inst{6-10} = XT{4-0}; 1307 let Inst{11-15} = XA{4-0}; 1308 let Inst{16-20} = XB{4-0}; 1309 let Inst{21-25} = XC{4-0}; 1310 let Inst{26-27} = xo; 1311 let Inst{28} = XC{5}; 1312 let Inst{29} = XA{5}; 1313 let Inst{30} = XB{5}; 1314 let Inst{31} = XT{5}; 1315} 1316 1317// DCB_Form - Form X instruction, used for dcb* instructions. 1318class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1319 InstrItinClass itin, list<dag> pattern> 1320 : I<31, OOL, IOL, asmstr, itin> { 1321 bits<5> A; 1322 bits<5> B; 1323 1324 let Pattern = pattern; 1325 1326 let Inst{6-10} = immfield; 1327 let Inst{11-15} = A; 1328 let Inst{16-20} = B; 1329 let Inst{21-30} = xo; 1330 let Inst{31} = 0; 1331} 1332 1333class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1334 InstrItinClass itin, list<dag> pattern> 1335 : I<31, OOL, IOL, asmstr, itin> { 1336 bits<5> TH; 1337 bits<5> A; 1338 bits<5> B; 1339 1340 let Pattern = pattern; 1341 1342 let Inst{6-10} = TH; 1343 let Inst{11-15} = A; 1344 let Inst{16-20} = B; 1345 let Inst{21-30} = xo; 1346 let Inst{31} = 0; 1347} 1348 1349// DSS_Form - Form X instruction, used for altivec dss* instructions. 1350class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1351 InstrItinClass itin, list<dag> pattern> 1352 : I<31, OOL, IOL, asmstr, itin> { 1353 bits<2> STRM; 1354 bits<5> A; 1355 bits<5> B; 1356 1357 let Pattern = pattern; 1358 1359 let Inst{6} = T; 1360 let Inst{7-8} = 0; 1361 let Inst{9-10} = STRM; 1362 let Inst{11-15} = A; 1363 let Inst{16-20} = B; 1364 let Inst{21-30} = xo; 1365 let Inst{31} = 0; 1366} 1367 1368// 1.7.7 XL-Form 1369class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1370 InstrItinClass itin, list<dag> pattern> 1371 : I<opcode, OOL, IOL, asmstr, itin> { 1372 bits<5> CRD; 1373 bits<5> CRA; 1374 bits<5> CRB; 1375 1376 let Pattern = pattern; 1377 1378 let Inst{6-10} = CRD; 1379 let Inst{11-15} = CRA; 1380 let Inst{16-20} = CRB; 1381 let Inst{21-30} = xo; 1382 let Inst{31} = 0; 1383} 1384 1385class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1386 InstrItinClass itin, list<dag> pattern> 1387 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1388 let CRD = 0; 1389 let CRA = 0; 1390 let CRB = 0; 1391} 1392 1393class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1394 InstrItinClass itin, list<dag> pattern> 1395 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1396 bits<5> RT; 1397 bits<5> RB; 1398 1399 let CRD = RT; 1400 let CRA = 0; 1401 let CRB = RB; 1402} 1403 1404class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1405 InstrItinClass itin, list<dag> pattern> 1406 : I<opcode, OOL, IOL, asmstr, itin> { 1407 bits<5> CRD; 1408 1409 let Pattern = pattern; 1410 1411 let Inst{6-10} = CRD; 1412 let Inst{11-15} = CRD; 1413 let Inst{16-20} = CRD; 1414 let Inst{21-30} = xo; 1415 let Inst{31} = 0; 1416} 1417 1418class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1419 InstrItinClass itin, list<dag> pattern> 1420 : I<opcode, OOL, IOL, asmstr, itin> { 1421 bits<5> BO; 1422 bits<5> BI; 1423 bits<2> BH; 1424 1425 let Pattern = pattern; 1426 1427 let Inst{6-10} = BO; 1428 let Inst{11-15} = BI; 1429 let Inst{16-18} = 0; 1430 let Inst{19-20} = BH; 1431 let Inst{21-30} = xo; 1432 let Inst{31} = lk; 1433} 1434 1435class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1436 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1437 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1438 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1439 bits<3> CR; 1440 1441 let BO = BIBO{4-0}; 1442 let BI{0-1} = BIBO{5-6}; 1443 let BI{2-4} = CR{0-2}; 1444 let BH = 0; 1445} 1446 1447class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1448 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1449 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1450 let BO = bo; 1451 let BH = 0; 1452} 1453 1454class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1455 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1456 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1457 let BO = bo; 1458 let BI = bi; 1459 let BH = 0; 1460} 1461 1462class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1463 InstrItinClass itin> 1464 : I<opcode, OOL, IOL, asmstr, itin> { 1465 bits<3> BF; 1466 bits<3> BFA; 1467 1468 let Inst{6-8} = BF; 1469 let Inst{9-10} = 0; 1470 let Inst{11-13} = BFA; 1471 let Inst{14-15} = 0; 1472 let Inst{16-20} = 0; 1473 let Inst{21-30} = xo; 1474 let Inst{31} = 0; 1475} 1476 1477class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1478 InstrItinClass itin> 1479 : I<opcode, OOL, IOL, asmstr, itin> { 1480 bits<3> BF; 1481 bit W; 1482 bits<4> U; 1483 1484 bit RC = 0; 1485 1486 let Inst{6-8} = BF; 1487 let Inst{9-10} = 0; 1488 let Inst{11-14} = 0; 1489 let Inst{15} = W; 1490 let Inst{16-19} = U; 1491 let Inst{20} = 0; 1492 let Inst{21-30} = xo; 1493 let Inst{31} = RC; 1494} 1495 1496class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1497 InstrItinClass itin, list<dag> pattern> 1498 : I<opcode, OOL, IOL, asmstr, itin> { 1499 bits<1> S; 1500 1501 let Pattern = pattern; 1502 1503 let Inst{6-19} = 0; 1504 let Inst{20} = S; 1505 let Inst{21-30} = xo; 1506 let Inst{31} = 0; 1507} 1508 1509class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1510 bits<6> opcode2, bits<2> xo2, 1511 dag OOL, dag IOL, string asmstr, 1512 InstrItinClass itin, list<dag> pattern> 1513 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1514 bits<5> BO; 1515 bits<5> BI; 1516 bits<2> BH; 1517 1518 bits<5> RST; 1519 bits<19> DS_RA; 1520 1521 let Pattern = pattern; 1522 1523 let Inst{6-10} = BO; 1524 let Inst{11-15} = BI; 1525 let Inst{16-18} = 0; 1526 let Inst{19-20} = BH; 1527 let Inst{21-30} = xo1; 1528 let Inst{31} = lk; 1529 1530 let Inst{38-42} = RST; 1531 let Inst{43-47} = DS_RA{18-14}; // Register # 1532 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1533 let Inst{62-63} = xo2; 1534} 1535 1536class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1537 bits<5> bo, bits<5> bi, bit lk, 1538 bits<6> opcode2, bits<2> xo2, 1539 dag OOL, dag IOL, string asmstr, 1540 InstrItinClass itin, list<dag> pattern> 1541 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1542 OOL, IOL, asmstr, itin, pattern> { 1543 let BO = bo; 1544 let BI = bi; 1545 let BH = 0; 1546} 1547 1548// 1.7.8 XFX-Form 1549class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1550 InstrItinClass itin> 1551 : I<opcode, OOL, IOL, asmstr, itin> { 1552 bits<5> RT; 1553 bits<10> SPR; 1554 1555 let Inst{6-10} = RT; 1556 let Inst{11} = SPR{4}; 1557 let Inst{12} = SPR{3}; 1558 let Inst{13} = SPR{2}; 1559 let Inst{14} = SPR{1}; 1560 let Inst{15} = SPR{0}; 1561 let Inst{16} = SPR{9}; 1562 let Inst{17} = SPR{8}; 1563 let Inst{18} = SPR{7}; 1564 let Inst{19} = SPR{6}; 1565 let Inst{20} = SPR{5}; 1566 let Inst{21-30} = xo; 1567 let Inst{31} = 0; 1568} 1569 1570class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1571 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1572 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1573 let SPR = spr; 1574} 1575 1576class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1577 InstrItinClass itin> 1578 : I<opcode, OOL, IOL, asmstr, itin> { 1579 bits<5> RT; 1580 1581 let Inst{6-10} = RT; 1582 let Inst{11-20} = 0; 1583 let Inst{21-30} = xo; 1584 let Inst{31} = 0; 1585} 1586 1587class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1588 InstrItinClass itin, list<dag> pattern> 1589 : I<opcode, OOL, IOL, asmstr, itin> { 1590 bits<5> RT; 1591 bits<10> Entry; 1592 let Pattern = pattern; 1593 1594 let Inst{6-10} = RT; 1595 let Inst{11-20} = Entry; 1596 let Inst{21-30} = xo; 1597 let Inst{31} = 0; 1598} 1599 1600class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1601 InstrItinClass itin> 1602 : I<opcode, OOL, IOL, asmstr, itin> { 1603 bits<8> FXM; 1604 bits<5> rS; 1605 1606 let Inst{6-10} = rS; 1607 let Inst{11} = 0; 1608 let Inst{12-19} = FXM; 1609 let Inst{20} = 0; 1610 let Inst{21-30} = xo; 1611 let Inst{31} = 0; 1612} 1613 1614class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1615 InstrItinClass itin> 1616 : I<opcode, OOL, IOL, asmstr, itin> { 1617 bits<5> ST; 1618 bits<8> FXM; 1619 1620 let Inst{6-10} = ST; 1621 let Inst{11} = 1; 1622 let Inst{12-19} = FXM; 1623 let Inst{20} = 0; 1624 let Inst{21-30} = xo; 1625 let Inst{31} = 0; 1626} 1627 1628class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1629 InstrItinClass itin> 1630 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1631 1632class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1633 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1634 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1635 let SPR = spr; 1636} 1637 1638// XFL-Form - MTFSF 1639// This is probably 1.7.9, but I don't have the reference that uses this 1640// numbering scheme... 1641class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1642 InstrItinClass itin, list<dag>pattern> 1643 : I<opcode, OOL, IOL, asmstr, itin> { 1644 bits<8> FM; 1645 bits<5> rT; 1646 1647 bit RC = 0; // set by isDOT 1648 let Pattern = pattern; 1649 1650 let Inst{6} = 0; 1651 let Inst{7-14} = FM; 1652 let Inst{15} = 0; 1653 let Inst{16-20} = rT; 1654 let Inst{21-30} = xo; 1655 let Inst{31} = RC; 1656} 1657 1658class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1659 InstrItinClass itin, list<dag>pattern> 1660 : I<opcode, OOL, IOL, asmstr, itin> { 1661 bit L; 1662 bits<8> FLM; 1663 bit W; 1664 bits<5> FRB; 1665 1666 bit RC = 0; // set by isDOT 1667 let Pattern = pattern; 1668 1669 let Inst{6} = L; 1670 let Inst{7-14} = FLM; 1671 let Inst{15} = W; 1672 let Inst{16-20} = FRB; 1673 let Inst{21-30} = xo; 1674 let Inst{31} = RC; 1675} 1676 1677// 1.7.10 XS-Form - SRADI. 1678class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1679 InstrItinClass itin, list<dag> pattern> 1680 : I<opcode, OOL, IOL, asmstr, itin> { 1681 bits<5> A; 1682 bits<5> RS; 1683 bits<6> SH; 1684 1685 bit RC = 0; // set by isDOT 1686 let Pattern = pattern; 1687 1688 let Inst{6-10} = RS; 1689 let Inst{11-15} = A; 1690 let Inst{16-20} = SH{4,3,2,1,0}; 1691 let Inst{21-29} = xo; 1692 let Inst{30} = SH{5}; 1693 let Inst{31} = RC; 1694} 1695 1696// 1.7.11 XO-Form 1697class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1698 InstrItinClass itin, list<dag> pattern> 1699 : I<opcode, OOL, IOL, asmstr, itin> { 1700 bits<5> RT; 1701 bits<5> RA; 1702 bits<5> RB; 1703 1704 let Pattern = pattern; 1705 1706 bit RC = 0; // set by isDOT 1707 1708 let Inst{6-10} = RT; 1709 let Inst{11-15} = RA; 1710 let Inst{16-20} = RB; 1711 let Inst{21} = oe; 1712 let Inst{22-30} = xo; 1713 let Inst{31} = RC; 1714} 1715 1716class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1717 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1718 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1719 let RB = 0; 1720} 1721 1722// 1.7.12 A-Form 1723class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1724 InstrItinClass itin, list<dag> pattern> 1725 : I<opcode, OOL, IOL, asmstr, itin> { 1726 bits<5> FRT; 1727 bits<5> FRA; 1728 bits<5> FRC; 1729 bits<5> FRB; 1730 1731 let Pattern = pattern; 1732 1733 bit RC = 0; // set by isDOT 1734 1735 let Inst{6-10} = FRT; 1736 let Inst{11-15} = FRA; 1737 let Inst{16-20} = FRB; 1738 let Inst{21-25} = FRC; 1739 let Inst{26-30} = xo; 1740 let Inst{31} = RC; 1741} 1742 1743class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1744 InstrItinClass itin, list<dag> pattern> 1745 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1746 let FRC = 0; 1747} 1748 1749class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1750 InstrItinClass itin, list<dag> pattern> 1751 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1752 let FRB = 0; 1753} 1754 1755class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1756 InstrItinClass itin, list<dag> pattern> 1757 : I<opcode, OOL, IOL, asmstr, itin> { 1758 bits<5> RT; 1759 bits<5> RA; 1760 bits<5> RB; 1761 bits<5> COND; 1762 1763 let Pattern = pattern; 1764 1765 let Inst{6-10} = RT; 1766 let Inst{11-15} = RA; 1767 let Inst{16-20} = RB; 1768 let Inst{21-25} = COND; 1769 let Inst{26-30} = xo; 1770 let Inst{31} = 0; 1771} 1772 1773// Used for QPX 1774class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1775 InstrItinClass itin, list<dag> pattern> 1776 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1777 let FRA = 0; 1778 let FRC = 0; 1779} 1780 1781// 1.7.13 M-Form 1782class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1783 InstrItinClass itin, list<dag> pattern> 1784 : I<opcode, OOL, IOL, asmstr, itin> { 1785 bits<5> RA; 1786 bits<5> RS; 1787 bits<5> RB; 1788 bits<5> MB; 1789 bits<5> ME; 1790 1791 let Pattern = pattern; 1792 1793 bit RC = 0; // set by isDOT 1794 1795 let Inst{6-10} = RS; 1796 let Inst{11-15} = RA; 1797 let Inst{16-20} = RB; 1798 let Inst{21-25} = MB; 1799 let Inst{26-30} = ME; 1800 let Inst{31} = RC; 1801} 1802 1803class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1804 InstrItinClass itin, list<dag> pattern> 1805 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1806} 1807 1808// 1.7.14 MD-Form 1809class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1810 InstrItinClass itin, list<dag> pattern> 1811 : I<opcode, OOL, IOL, asmstr, itin> { 1812 bits<5> RA; 1813 bits<5> RS; 1814 bits<6> SH; 1815 bits<6> MBE; 1816 1817 let Pattern = pattern; 1818 1819 bit RC = 0; // set by isDOT 1820 1821 let Inst{6-10} = RS; 1822 let Inst{11-15} = RA; 1823 let Inst{16-20} = SH{4,3,2,1,0}; 1824 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1825 let Inst{27-29} = xo; 1826 let Inst{30} = SH{5}; 1827 let Inst{31} = RC; 1828} 1829 1830class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1831 InstrItinClass itin, list<dag> pattern> 1832 : I<opcode, OOL, IOL, asmstr, itin> { 1833 bits<5> RA; 1834 bits<5> RS; 1835 bits<5> RB; 1836 bits<6> MBE; 1837 1838 let Pattern = pattern; 1839 1840 bit RC = 0; // set by isDOT 1841 1842 let Inst{6-10} = RS; 1843 let Inst{11-15} = RA; 1844 let Inst{16-20} = RB; 1845 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1846 let Inst{27-30} = xo; 1847 let Inst{31} = RC; 1848} 1849 1850 1851// E-1 VA-Form 1852 1853// VAForm_1 - DACB ordering. 1854class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1855 InstrItinClass itin, list<dag> pattern> 1856 : I<4, OOL, IOL, asmstr, itin> { 1857 bits<5> VD; 1858 bits<5> VA; 1859 bits<5> VC; 1860 bits<5> VB; 1861 1862 let Pattern = pattern; 1863 1864 let Inst{6-10} = VD; 1865 let Inst{11-15} = VA; 1866 let Inst{16-20} = VB; 1867 let Inst{21-25} = VC; 1868 let Inst{26-31} = xo; 1869} 1870 1871// VAForm_1a - DABC ordering. 1872class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1873 InstrItinClass itin, list<dag> pattern> 1874 : I<4, OOL, IOL, asmstr, itin> { 1875 bits<5> VD; 1876 bits<5> VA; 1877 bits<5> VB; 1878 bits<5> VC; 1879 1880 let Pattern = pattern; 1881 1882 let Inst{6-10} = VD; 1883 let Inst{11-15} = VA; 1884 let Inst{16-20} = VB; 1885 let Inst{21-25} = VC; 1886 let Inst{26-31} = xo; 1887} 1888 1889class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1890 InstrItinClass itin, list<dag> pattern> 1891 : I<4, OOL, IOL, asmstr, itin> { 1892 bits<5> VD; 1893 bits<5> VA; 1894 bits<5> VB; 1895 bits<4> SH; 1896 1897 let Pattern = pattern; 1898 1899 let Inst{6-10} = VD; 1900 let Inst{11-15} = VA; 1901 let Inst{16-20} = VB; 1902 let Inst{21} = 0; 1903 let Inst{22-25} = SH; 1904 let Inst{26-31} = xo; 1905} 1906 1907// E-2 VX-Form 1908class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1909 InstrItinClass itin, list<dag> pattern> 1910 : I<4, OOL, IOL, asmstr, itin> { 1911 bits<5> VD; 1912 bits<5> VA; 1913 bits<5> VB; 1914 1915 let Pattern = pattern; 1916 1917 let Inst{6-10} = VD; 1918 let Inst{11-15} = VA; 1919 let Inst{16-20} = VB; 1920 let Inst{21-31} = xo; 1921} 1922 1923class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1924 InstrItinClass itin, list<dag> pattern> 1925 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1926 let VA = VD; 1927 let VB = VD; 1928} 1929 1930 1931class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1932 InstrItinClass itin, list<dag> pattern> 1933 : I<4, OOL, IOL, asmstr, itin> { 1934 bits<5> VD; 1935 bits<5> VB; 1936 1937 let Pattern = pattern; 1938 1939 let Inst{6-10} = VD; 1940 let Inst{11-15} = 0; 1941 let Inst{16-20} = VB; 1942 let Inst{21-31} = xo; 1943} 1944 1945class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1946 InstrItinClass itin, list<dag> pattern> 1947 : I<4, OOL, IOL, asmstr, itin> { 1948 bits<5> VD; 1949 bits<5> IMM; 1950 1951 let Pattern = pattern; 1952 1953 let Inst{6-10} = VD; 1954 let Inst{11-15} = IMM; 1955 let Inst{16-20} = 0; 1956 let Inst{21-31} = xo; 1957} 1958 1959/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1960class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1961 InstrItinClass itin, list<dag> pattern> 1962 : I<4, OOL, IOL, asmstr, itin> { 1963 bits<5> VD; 1964 1965 let Pattern = pattern; 1966 1967 let Inst{6-10} = VD; 1968 let Inst{11-15} = 0; 1969 let Inst{16-20} = 0; 1970 let Inst{21-31} = xo; 1971} 1972 1973/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1974class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1975 InstrItinClass itin, list<dag> pattern> 1976 : I<4, OOL, IOL, asmstr, itin> { 1977 bits<5> VB; 1978 1979 let Pattern = pattern; 1980 1981 let Inst{6-10} = 0; 1982 let Inst{11-15} = 0; 1983 let Inst{16-20} = VB; 1984 let Inst{21-31} = xo; 1985} 1986 1987// e.g. [PO VRT EO VRB XO] 1988class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1989 string asmstr, InstrItinClass itin, list<dag> pattern> 1990 : I<4, OOL, IOL, asmstr, itin> { 1991 bits<5> RD; 1992 bits<5> VB; 1993 1994 let Pattern = pattern; 1995 1996 let Inst{6-10} = RD; 1997 let Inst{11-15} = eo; 1998 let Inst{16-20} = VB; 1999 let Inst{21-31} = xo; 2000} 2001 2002/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2003class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2004 InstrItinClass itin, list<dag> pattern> 2005 : I<4, OOL, IOL, asmstr, itin> { 2006 bits<5> VD; 2007 bits<5> VA; 2008 bits<1> ST; 2009 bits<4> SIX; 2010 2011 let Pattern = pattern; 2012 2013 let Inst{6-10} = VD; 2014 let Inst{11-15} = VA; 2015 let Inst{16} = ST; 2016 let Inst{17-20} = SIX; 2017 let Inst{21-31} = xo; 2018} 2019 2020/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2021class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2022 InstrItinClass itin, list<dag> pattern> 2023 : I<4, OOL, IOL, asmstr, itin> { 2024 bits<5> VD; 2025 bits<5> VA; 2026 2027 let Pattern = pattern; 2028 2029 let Inst{6-10} = VD; 2030 let Inst{11-15} = VA; 2031 let Inst{16-20} = 0; 2032 let Inst{21-31} = xo; 2033} 2034 2035// E-4 VXR-Form 2036class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2037 InstrItinClass itin, list<dag> pattern> 2038 : I<4, OOL, IOL, asmstr, itin> { 2039 bits<5> VD; 2040 bits<5> VA; 2041 bits<5> VB; 2042 bit RC = 0; 2043 2044 let Pattern = pattern; 2045 2046 let Inst{6-10} = VD; 2047 let Inst{11-15} = VA; 2048 let Inst{16-20} = VB; 2049 let Inst{21} = RC; 2050 let Inst{22-31} = xo; 2051} 2052 2053// VX-Form: [PO VRT EO VRB 1 PS XO] 2054class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2055 dag OOL, dag IOL, string asmstr, 2056 InstrItinClass itin, list<dag> pattern> 2057 : I<4, OOL, IOL, asmstr, itin> { 2058 bits<5> VD; 2059 bits<5> VB; 2060 bit PS; 2061 2062 let Pattern = pattern; 2063 2064 let Inst{6-10} = VD; 2065 let Inst{11-15} = eo; 2066 let Inst{16-20} = VB; 2067 let Inst{21} = 1; 2068 let Inst{22} = PS; 2069 let Inst{23-31} = xo; 2070} 2071 2072// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2073class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2074 InstrItinClass itin, list<dag> pattern> 2075 : I<4, OOL, IOL, asmstr, itin> { 2076 bits<5> VD; 2077 bits<5> VA; 2078 bits<5> VB; 2079 bit PS; 2080 2081 let Pattern = pattern; 2082 2083 let Inst{6-10} = VD; 2084 let Inst{11-15} = VA; 2085 let Inst{16-20} = VB; 2086 let Inst{21} = 1; 2087 let Inst{22} = PS; 2088 let Inst{23-31} = xo; 2089} 2090 2091// Z23-Form (used by QPX) 2092class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2093 InstrItinClass itin, list<dag> pattern> 2094 : I<opcode, OOL, IOL, asmstr, itin> { 2095 bits<5> FRT; 2096 bits<5> FRA; 2097 bits<5> FRB; 2098 bits<2> idx; 2099 2100 let Pattern = pattern; 2101 2102 bit RC = 0; // set by isDOT 2103 2104 let Inst{6-10} = FRT; 2105 let Inst{11-15} = FRA; 2106 let Inst{16-20} = FRB; 2107 let Inst{21-22} = idx; 2108 let Inst{23-30} = xo; 2109 let Inst{31} = RC; 2110} 2111 2112class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2113 InstrItinClass itin, list<dag> pattern> 2114 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 2115 let FRB = 0; 2116} 2117 2118class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2119 InstrItinClass itin, list<dag> pattern> 2120 : I<opcode, OOL, IOL, asmstr, itin> { 2121 bits<5> FRT; 2122 bits<12> idx; 2123 2124 let Pattern = pattern; 2125 2126 bit RC = 0; // set by isDOT 2127 2128 let Inst{6-10} = FRT; 2129 let Inst{11-22} = idx; 2130 let Inst{23-30} = xo; 2131 let Inst{31} = RC; 2132} 2133 2134class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2135 InstrItinClass itin, list<dag> pattern> 2136 : I<opcode, OOL, IOL, asmstr, itin> { 2137 bits<5> VRT; 2138 bit R; 2139 bits<5> VRB; 2140 bits<2> idx; 2141 2142 let Pattern = pattern; 2143 2144 bit RC = 0; // set by isDOT 2145 2146 let Inst{6-10} = VRT; 2147 let Inst{11-14} = 0; 2148 let Inst{15} = R; 2149 let Inst{16-20} = VRB; 2150 let Inst{21-22} = idx; 2151 let Inst{23-30} = xo; 2152 let Inst{31} = RC; 2153} 2154 2155//===----------------------------------------------------------------------===// 2156// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2157// stuff 2158class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2159 : I<0, OOL, IOL, asmstr, NoItinerary> { 2160 let isCodeGenOnly = 1; 2161 let PPC64 = 0; 2162 let Pattern = pattern; 2163 let Inst{31-0} = 0; 2164 let hasNoSchedulingInfo = 1; 2165} 2166 2167// Instruction that require custom insertion support 2168// a.k.a. ISelPseudos, however, these won't have isPseudo set 2169class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2170 list<dag> pattern> 2171 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2172 let usesCustomInserter = 1; 2173} 2174 2175// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2176// files is set only for PostRAPseudo 2177class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2178 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2179 let isPseudo = 1; 2180} 2181 2182class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2183 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2184 2185