1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); 71}]>; 72 73def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); 76}]>; 77 78 79//===----------------------------------------------------------------------===// 80// Calls. 81// 82 83let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 84let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isReturn = 1, Uses = [LR8, RM] in 86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 87 [(retflag)]>, Requires<[In64BitMode]>; 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 94 []>, 95 Requires<[In64BitMode]>; 96 97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 98 "bcctr 12, $bi, 0", IIC_BrB, []>, 99 Requires<[In64BitMode]>; 100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 101 "bcctr 4, $bi, 0", IIC_BrB, []>, 102 Requires<[In64BitMode]>; 103 } 104} 105 106let Defs = [LR8] in 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 108 PPC970_Unit_BRU; 109 110let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 111 let Defs = [CTR8], Uses = [CTR8] in { 112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 113 "bdz $dst">; 114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 115 "bdnz $dst">; 116 } 117 118 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 120 "bdzlr", IIC_BrB, []>; 121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 122 "bdnzlr", IIC_BrB, []>; 123 } 124} 125 126 127 128let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 129 // Convenient aliases for call instructions 130 let Uses = [RM] in { 131 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 132 "bl $func", IIC_BrB, []>; // See Pat patterns below. 133 134 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 135 "bl $func", IIC_BrB, []>; 136 137 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 138 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 139 } 140 let Uses = [RM], isCodeGenOnly = 1 in { 141 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 142 (outs), (ins calltarget:$func), 143 "bl $func\n\tnop", IIC_BrB, []>; 144 145 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 146 (outs), (ins tlscall:$func), 147 "bl $func\n\tnop", IIC_BrB, []>; 148 149 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 150 (outs), (ins abscalltarget:$func), 151 "bla $func\n\tnop", IIC_BrB, 152 [(PPCcall_nop (i64 imm:$func))]>; 153 } 154 let Uses = [CTR8, RM] in { 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc ixaddr:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206// Atomic operations 207let usesCustomInserter = 1 in { 208 let Defs = [CR0] in { 209 def ATOMIC_LOAD_ADD_I64 : Pseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 211 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_SUB_I64 : Pseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 214 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_OR_I64 : Pseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 217 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_XOR_I64 : Pseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 220 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_AND_I64 : Pseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 223 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_NAND_I64 : Pseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 226 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 227 def ATOMIC_LOAD_MIN_I64 : Pseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 229 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_MAX_I64 : Pseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 232 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_UMIN_I64 : Pseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 235 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_UMAX_I64 : Pseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 238 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 239 240 def ATOMIC_CMP_SWAP_I64 : Pseudo< 241 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 242 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 243 244 def ATOMIC_SWAP_I64 : Pseudo< 245 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 246 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 247 } 248} 249 250// Instructions to support atomic operations 251let mayLoad = 1, hasSideEffects = 0 in { 252def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 253 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 254 255// Instruction to support lock versions of atomics 256// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 257def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 258 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 259 260let hasExtraDefRegAllocReq = 1 in 261def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 262 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 263 Requires<[IsISA3_0]>; 264} 265 266let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 267def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 268 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 269 270let mayStore = 1, hasSideEffects = 0 in 271def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 272 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 273 Requires<[IsISA3_0]>; 274 275let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 276let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 277def TCRETURNdi8 :Pseudo< (outs), 278 (ins calltarget:$dst, i32imm:$offset), 279 "#TC_RETURNd8 $dst $offset", 280 []>; 281 282let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 283def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 284 "#TC_RETURNa8 $func $offset", 285 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 286 287let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 288def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 289 "#TC_RETURNr8 $dst $offset", 290 []>; 291 292let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 293 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 294def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 295 []>, 296 Requires<[In64BitMode]>; 297 298let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 299 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 300def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 301 "b $dst", IIC_BrB, 302 []>; 303 304let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 305 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 306def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 307 "ba $dst", IIC_BrB, 308 []>; 309} // Interpretation64Bit 310 311def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 312 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 313 314def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 315 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 316 317def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 318 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 319 320 321// 64-bit CR instructions 322let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 323let hasSideEffects = 0 in { 324// mtocrf's input needs to be prepared by shifting by an amount dependent 325// on the cr register selected. Thus, post-ra anti-dep breaking must not 326// later change that register assignment. 327let hasExtraDefRegAllocReq = 1 in { 328def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 329 "mtocrf $FXM, $ST", IIC_BrMCRX>, 330 PPC970_DGroup_First, PPC970_Unit_CRU; 331 332// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 333// is dependent on the cr fields being set. 334def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 335 "mtcrf $FXM, $rS", IIC_BrMCRX>, 336 PPC970_MicroCode, PPC970_Unit_CRU; 337} // hasExtraDefRegAllocReq = 1 338 339// mfocrf's input needs to be prepared by shifting by an amount dependent 340// on the cr register selected. Thus, post-ra anti-dep breaking must not 341// later change that register assignment. 342let hasExtraSrcRegAllocReq = 1 in { 343def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 344 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 345 PPC970_DGroup_First, PPC970_Unit_CRU; 346 347// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 348// is dependent on the cr fields being copied. 349def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 350 "mfcr $rT", IIC_SprMFCR>, 351 PPC970_MicroCode, PPC970_Unit_CRU; 352} // hasExtraSrcRegAllocReq = 1 353} // hasSideEffects = 0 354 355let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 356 let Defs = [CTR8] in 357 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 358 "#EH_SJLJ_SETJMP64", 359 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 360 Requires<[In64BitMode]>; 361 let isTerminator = 1 in 362 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 363 "#EH_SJLJ_LONGJMP64", 364 [(PPCeh_sjlj_longjmp addr:$buf)]>, 365 Requires<[In64BitMode]>; 366} 367 368def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 369 "mfspr $RT, $SPR", IIC_SprMFSPR>; 370def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 371 "mtspr $SPR, $RT", IIC_SprMTSPR>; 372 373 374//===----------------------------------------------------------------------===// 375// 64-bit SPR manipulation instrs. 376 377let Uses = [CTR8] in { 378def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 379 "mfctr $rT", IIC_SprMFSPR>, 380 PPC970_DGroup_First, PPC970_Unit_FXU; 381} 382let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 383def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 384 "mtctr $rS", IIC_SprMTSPR>, 385 PPC970_DGroup_First, PPC970_Unit_FXU; 386} 387let hasSideEffects = 1, Defs = [CTR8] in { 388let Pattern = [(int_ppc_mtctr i64:$rS)] in 389def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 390 "mtctr $rS", IIC_SprMTSPR>, 391 PPC970_DGroup_First, PPC970_Unit_FXU; 392} 393 394let Pattern = [(set i64:$rT, readcyclecounter)] in 395def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 396 "mfspr $rT, 268", IIC_SprMFTB>, 397 PPC970_DGroup_First, PPC970_Unit_FXU; 398// Note that encoding mftb using mfspr is now the preferred form, 399// and has been since at least ISA v2.03. The mftb instruction has 400// now been phased out. Using mfspr, however, is known not to work on 401// the POWER3. 402 403let Defs = [X1], Uses = [X1] in 404def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 405 [(set i64:$result, 406 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 407def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 408 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 409 410let Defs = [LR8] in { 411def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 412 "mtlr $rS", IIC_SprMTSPR>, 413 PPC970_DGroup_First, PPC970_Unit_FXU; 414} 415let Uses = [LR8] in { 416def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 417 "mflr $rT", IIC_SprMFSPR>, 418 PPC970_DGroup_First, PPC970_Unit_FXU; 419} 420} // Interpretation64Bit 421 422//===----------------------------------------------------------------------===// 423// Fixed point instructions. 424// 425 426let PPC970_Unit = 1 in { // FXU Operations. 427let Interpretation64Bit = 1 in { 428let hasSideEffects = 0 in { 429let isCodeGenOnly = 1 in { 430 431let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 432def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 433 "li $rD, $imm", IIC_IntSimple, 434 [(set i64:$rD, imm64SExt16:$imm)]>; 435def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 436 "lis $rD, $imm", IIC_IntSimple, 437 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 438} 439 440// Logical ops. 441let isCommutable = 1 in { 442defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 443 "nand", "$rA, $rS, $rB", IIC_IntSimple, 444 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 445defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 446 "and", "$rA, $rS, $rB", IIC_IntSimple, 447 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 448} // isCommutable 449defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 450 "andc", "$rA, $rS, $rB", IIC_IntSimple, 451 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 452let isCommutable = 1 in { 453defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 454 "or", "$rA, $rS, $rB", IIC_IntSimple, 455 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 456defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 457 "nor", "$rA, $rS, $rB", IIC_IntSimple, 458 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 459} // isCommutable 460defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 461 "orc", "$rA, $rS, $rB", IIC_IntSimple, 462 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 463let isCommutable = 1 in { 464defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 465 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 466 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 467defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 468 "xor", "$rA, $rS, $rB", IIC_IntSimple, 469 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 470} // let isCommutable = 1 471 472// Logical ops with immediate. 473let Defs = [CR0] in { 474def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 475 "andi. $dst, $src1, $src2", IIC_IntGeneral, 476 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 477 isDOT; 478def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 479 "andis. $dst, $src1, $src2", IIC_IntGeneral, 480 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 481 isDOT; 482} 483def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 484 "ori $dst, $src1, $src2", IIC_IntSimple, 485 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 486def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 487 "oris $dst, $src1, $src2", IIC_IntSimple, 488 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 489def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 490 "xori $dst, $src1, $src2", IIC_IntSimple, 491 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 492def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 493 "xoris $dst, $src1, $src2", IIC_IntSimple, 494 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 495 496let isCommutable = 1 in 497defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 498 "add", "$rT, $rA, $rB", IIC_IntSimple, 499 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 500// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 501// initial-exec thread-local storage model. We need to forbid r0 here - 502// while it works for add just fine, the linker can relax this to local-exec 503// addi, which won't work for r0. 504def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 505 "add $rT, $rA, $rB", IIC_IntSimple, 506 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 507 508let isCommutable = 1 in 509defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 510 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 511 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 512 PPC970_DGroup_Cracked; 513 514let Defs = [CARRY] in 515def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 516 "addic $rD, $rA, $imm", IIC_IntGeneral, 517 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 518def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 519 "addi $rD, $rA, $imm", IIC_IntSimple, 520 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 521def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 522 "addis $rD, $rA, $imm", IIC_IntSimple, 523 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 524 525let Defs = [CARRY] in { 526def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 527 "subfic $rD, $rA, $imm", IIC_IntGeneral, 528 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 529} 530defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 531 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 532 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 533 PPC970_DGroup_Cracked; 534defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 535 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 536 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 537defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 538 "neg", "$rT, $rA", IIC_IntSimple, 539 [(set i64:$rT, (ineg i64:$rA))]>; 540let Uses = [CARRY] in { 541let isCommutable = 1 in 542defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 543 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 544 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 545defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 546 "addme", "$rT, $rA", IIC_IntGeneral, 547 [(set i64:$rT, (adde i64:$rA, -1))]>; 548defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 549 "addze", "$rT, $rA", IIC_IntGeneral, 550 [(set i64:$rT, (adde i64:$rA, 0))]>; 551defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 552 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 553 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 554defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 555 "subfme", "$rT, $rA", IIC_IntGeneral, 556 [(set i64:$rT, (sube -1, i64:$rA))]>; 557defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 558 "subfze", "$rT, $rA", IIC_IntGeneral, 559 [(set i64:$rT, (sube 0, i64:$rA))]>; 560} 561} // isCodeGenOnly 562 563// FIXME: Duplicating this for the asm parser should be unnecessary, but the 564// previous definition must be marked as CodeGen only to prevent decoding 565// conflicts. 566let isAsmParserOnly = 1 in 567def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 568 "add $rT, $rA, $rB", IIC_IntSimple, []>; 569 570let isCommutable = 1 in { 571defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 572 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 573 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 574defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 575 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 576 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 577} // isCommutable 578} 579} // Interpretation64Bit 580 581let isCompare = 1, hasSideEffects = 0 in { 582 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 583 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 584 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 585 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 586 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 587 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 588 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 589 "cmpldi $dst, $src1, $src2", 590 IIC_IntCompare>, isPPC64; 591 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 592 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 593 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 594 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 595 Requires<[IsISA3_0]>; 596 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 597 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 598 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 599} 600 601let hasSideEffects = 0 in { 602defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 603 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 604 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 605defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 606 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 607 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 608defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 609 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 610 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 611 612let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 613defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 614 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 615defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 616 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 617 Requires<[IsISA3_0]>; 618 619defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 620 "extsb", "$rA, $rS", IIC_IntSimple, 621 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 622defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 623 "extsh", "$rA, $rS", IIC_IntSimple, 624 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 625 626defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 627 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 628defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 629 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 630} // Interpretation64Bit 631 632// For fast-isel: 633let isCodeGenOnly = 1 in { 634def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 635 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 636def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 637 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 638} // isCodeGenOnly for fast-isel 639 640defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 641 "extsw", "$rA, $rS", IIC_IntSimple, 642 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 643let Interpretation64Bit = 1, isCodeGenOnly = 1 in 644defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 645 "extsw", "$rA, $rS", IIC_IntSimple, 646 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 647 648defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 649 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 650 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 651defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 652 "cntlzd", "$rA, $rS", IIC_IntGeneral, 653 [(set i64:$rA, (ctlz i64:$rS))]>; 654defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 655 "cnttzd", "$rA, $rS", IIC_IntGeneral, 656 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 657def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 658 "popcntd $rA, $rS", IIC_IntGeneral, 659 [(set i64:$rA, (ctpop i64:$rS))]>; 660def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 661 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 662 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 663 isPPC64, Requires<[HasBPERMD]>; 664 665let isCodeGenOnly = 1, isCommutable = 1 in 666def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 667 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 668 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 669 670// popcntw also does a population count on the high 32 bits (storing the 671// results in the high 32-bits of the output). We'll ignore that here (which is 672// safe because we never separately use the high part of the 64-bit registers). 673def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 674 "popcntw $rA, $rS", IIC_IntGeneral, 675 [(set i32:$rA, (ctpop i32:$rS))]>; 676 677defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 678 "divd", "$rT, $rA, $rB", IIC_IntDivD, 679 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 680defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 681 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 682 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 683def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 684 "divde $rT, $rA, $rB", IIC_IntDivD, 685 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 686 isPPC64, Requires<[HasExtDiv]>; 687let Defs = [CR0] in 688def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 689 "divde. $rT, $rA, $rB", IIC_IntDivD, 690 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 691 isPPC64, Requires<[HasExtDiv]>; 692def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 693 "divdeu $rT, $rA, $rB", IIC_IntDivD, 694 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 695 isPPC64, Requires<[HasExtDiv]>; 696let Defs = [CR0] in 697def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 698 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 699 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 700 isPPC64, Requires<[HasExtDiv]>; 701let isCommutable = 1 in 702defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 703 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 704 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 705let Interpretation64Bit = 1, isCodeGenOnly = 1 in 706def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 707 "mulli $rD, $rA, $imm", IIC_IntMulLI, 708 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 709} 710 711let hasSideEffects = 0 in { 712defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 713 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 714 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 715 []>, isPPC64, RegConstraint<"$rSi = $rA">, 716 NoEncode<"$rSi">; 717 718// Rotate instructions. 719defm RLDCL : MDSForm_1r<30, 8, 720 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 721 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 722 []>, isPPC64; 723defm RLDCR : MDSForm_1r<30, 9, 724 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 725 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 726 []>, isPPC64; 727defm RLDICL : MDForm_1r<30, 0, 728 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 729 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 730 []>, isPPC64; 731// For fast-isel: 732let isCodeGenOnly = 1 in 733def RLDICL_32_64 : MDForm_1<30, 0, 734 (outs g8rc:$rA), 735 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 736 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 737 []>, isPPC64; 738// End fast-isel. 739defm RLDICR : MDForm_1r<30, 1, 740 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 741 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 742 []>, isPPC64; 743defm RLDIC : MDForm_1r<30, 2, 744 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 745 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 746 []>, isPPC64; 747 748let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 749defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 750 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 751 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 752 []>; 753 754defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 755 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 756 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 757 []>; 758 759// RLWIMI can be commuted if the rotate amount is zero. 760let Interpretation64Bit = 1, isCodeGenOnly = 1 in 761defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 762 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 763 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 764 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 765 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 766 767let isSelect = 1 in 768def ISEL8 : AForm_4<31, 15, 769 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 770 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 771 []>; 772} // Interpretation64Bit 773} // hasSideEffects = 0 774} // End FXU Operations. 775 776 777//===----------------------------------------------------------------------===// 778// Load/Store instructions. 779// 780 781 782// Sign extending loads. 783let PPC970_Unit = 2 in { 784let Interpretation64Bit = 1, isCodeGenOnly = 1 in 785def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 786 "lha $rD, $src", IIC_LdStLHA, 787 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 788 PPC970_DGroup_Cracked; 789def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 790 "lwa $rD, $src", IIC_LdStLWA, 791 [(set i64:$rD, 792 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 793 PPC970_DGroup_Cracked; 794let Interpretation64Bit = 1, isCodeGenOnly = 1 in 795def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 796 "lhax $rD, $src", IIC_LdStLHA, 797 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 798 PPC970_DGroup_Cracked; 799def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 800 "lwax $rD, $src", IIC_LdStLHA, 801 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 802 PPC970_DGroup_Cracked; 803// For fast-isel: 804let isCodeGenOnly = 1, mayLoad = 1 in { 805def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 806 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 807 PPC970_DGroup_Cracked; 808def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 809 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 810 PPC970_DGroup_Cracked; 811} // end fast-isel isCodeGenOnly 812 813// Update forms. 814let mayLoad = 1, hasSideEffects = 0 in { 815let Interpretation64Bit = 1, isCodeGenOnly = 1 in 816def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 817 (ins memri:$addr), 818 "lhau $rD, $addr", IIC_LdStLHAU, 819 []>, RegConstraint<"$addr.reg = $ea_result">, 820 NoEncode<"$ea_result">; 821// NO LWAU! 822 823let Interpretation64Bit = 1, isCodeGenOnly = 1 in 824def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 825 (ins memrr:$addr), 826 "lhaux $rD, $addr", IIC_LdStLHAUX, 827 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 828 NoEncode<"$ea_result">; 829def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 830 (ins memrr:$addr), 831 "lwaux $rD, $addr", IIC_LdStLHAUX, 832 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 833 NoEncode<"$ea_result">, isPPC64; 834} 835} 836 837let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 838// Zero extending loads. 839let PPC970_Unit = 2 in { 840def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 841 "lbz $rD, $src", IIC_LdStLoad, 842 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 843def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 844 "lhz $rD, $src", IIC_LdStLoad, 845 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 846def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 847 "lwz $rD, $src", IIC_LdStLoad, 848 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 849 850def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 851 "lbzx $rD, $src", IIC_LdStLoad, 852 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 853def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 854 "lhzx $rD, $src", IIC_LdStLoad, 855 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 856def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 857 "lwzx $rD, $src", IIC_LdStLoad, 858 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 859 860 861// Update forms. 862let mayLoad = 1, hasSideEffects = 0 in { 863def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 864 "lbzu $rD, $addr", IIC_LdStLoadUpd, 865 []>, RegConstraint<"$addr.reg = $ea_result">, 866 NoEncode<"$ea_result">; 867def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 868 "lhzu $rD, $addr", IIC_LdStLoadUpd, 869 []>, RegConstraint<"$addr.reg = $ea_result">, 870 NoEncode<"$ea_result">; 871def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 872 "lwzu $rD, $addr", IIC_LdStLoadUpd, 873 []>, RegConstraint<"$addr.reg = $ea_result">, 874 NoEncode<"$ea_result">; 875 876def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 877 (ins memrr:$addr), 878 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 879 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 880 NoEncode<"$ea_result">; 881def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 882 (ins memrr:$addr), 883 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 884 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 885 NoEncode<"$ea_result">; 886def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 887 (ins memrr:$addr), 888 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 889 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 890 NoEncode<"$ea_result">; 891} 892} 893} // Interpretation64Bit 894 895 896// Full 8-byte loads. 897let PPC970_Unit = 2 in { 898def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 899 "ld $rD, $src", IIC_LdStLD, 900 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 901// The following four definitions are selected for small code model only. 902// Otherwise, we need to create two instructions to form a 32-bit offset, 903// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 904def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 905 "#LDtoc", 906 [(set i64:$rD, 907 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 908def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 909 "#LDtocJTI", 910 [(set i64:$rD, 911 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 912def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 913 "#LDtocCPT", 914 [(set i64:$rD, 915 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 916def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 917 "#LDtocCPT", 918 [(set i64:$rD, 919 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 920 921def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 922 "ldx $rD, $src", IIC_LdStLD, 923 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 924def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 925 "ldbrx $rD, $src", IIC_LdStLoad, 926 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 927 928let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 929def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 930 "lhbrx $rD, $src", IIC_LdStLoad, []>; 931def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 932 "lwbrx $rD, $src", IIC_LdStLoad, []>; 933} 934 935let mayLoad = 1, hasSideEffects = 0 in { 936def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 937 "ldu $rD, $addr", IIC_LdStLDU, 938 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 939 NoEncode<"$ea_result">; 940 941def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 942 (ins memrr:$addr), 943 "ldux $rD, $addr", IIC_LdStLDUX, 944 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 945 NoEncode<"$ea_result">, isPPC64; 946 947def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 948 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 949 Requires<[IsISA3_0]>; 950} 951} 952 953// Support for medium and large code model. 954let hasSideEffects = 0 in { 955def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 956 "#ADDIStocHA", []>, isPPC64; 957let mayLoad = 1 in 958def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 959 "#LDtocL", []>, isPPC64; 960def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 961 "#ADDItocL", []>, isPPC64; 962} 963 964// Support for thread-local storage. 965def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 966 "#ADDISgotTprelHA", 967 [(set i64:$rD, 968 (PPCaddisGotTprelHA i64:$reg, 969 tglobaltlsaddr:$disp))]>, 970 isPPC64; 971def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 972 "#LDgotTprelL", 973 [(set i64:$rD, 974 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 975 isPPC64; 976def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 977 (ADD8TLS $in, tglobaltlsaddr:$g)>; 978def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 979 "#ADDIStlsgdHA", 980 [(set i64:$rD, 981 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 982 isPPC64; 983def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 984 "#ADDItlsgdL", 985 [(set i64:$rD, 986 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 987 isPPC64; 988// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 989// explicitly defined when this op is created, so not mentioned here. 990let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 991 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 992def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 993 "#GETtlsADDR", 994 [(set i64:$rD, 995 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 996 isPPC64; 997// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 998// are true defines while the rest of the Defs are clobbers. 999let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1000 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1001 in 1002def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 1003 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1004 "#ADDItlsgdLADDR", 1005 [(set i64:$rD, 1006 (PPCaddiTlsgdLAddr i64:$reg, 1007 tglobaltlsaddr:$disp, 1008 tglobaltlsaddr:$sym))]>, 1009 isPPC64; 1010def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1011 "#ADDIStlsldHA", 1012 [(set i64:$rD, 1013 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1014 isPPC64; 1015def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1016 "#ADDItlsldL", 1017 [(set i64:$rD, 1018 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1019 isPPC64; 1020// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1021// explicitly defined when this op is created, so not mentioned here. 1022let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1023 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1024def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1025 "#GETtlsldADDR", 1026 [(set i64:$rD, 1027 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1028 isPPC64; 1029// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1030// are true defines, while the rest of the Defs are clobbers. 1031let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1032 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1033 in 1034def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 1035 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1036 "#ADDItlsldLADDR", 1037 [(set i64:$rD, 1038 (PPCaddiTlsldLAddr i64:$reg, 1039 tglobaltlsaddr:$disp, 1040 tglobaltlsaddr:$sym))]>, 1041 isPPC64; 1042def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1043 "#ADDISdtprelHA", 1044 [(set i64:$rD, 1045 (PPCaddisDtprelHA i64:$reg, 1046 tglobaltlsaddr:$disp))]>, 1047 isPPC64; 1048def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1049 "#ADDIdtprelL", 1050 [(set i64:$rD, 1051 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1052 isPPC64; 1053 1054let PPC970_Unit = 2 in { 1055let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1056// Truncating stores. 1057def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1058 "stb $rS, $src", IIC_LdStStore, 1059 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1060def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1061 "sth $rS, $src", IIC_LdStStore, 1062 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1063def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1064 "stw $rS, $src", IIC_LdStStore, 1065 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1066def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1067 "stbx $rS, $dst", IIC_LdStStore, 1068 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1069 PPC970_DGroup_Cracked; 1070def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1071 "sthx $rS, $dst", IIC_LdStStore, 1072 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1073 PPC970_DGroup_Cracked; 1074def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1075 "stwx $rS, $dst", IIC_LdStStore, 1076 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1077 PPC970_DGroup_Cracked; 1078} // Interpretation64Bit 1079 1080// Normal 8-byte stores. 1081def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1082 "std $rS, $dst", IIC_LdStSTD, 1083 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1084def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1085 "stdx $rS, $dst", IIC_LdStSTD, 1086 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1087 PPC970_DGroup_Cracked; 1088def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1089 "stdbrx $rS, $dst", IIC_LdStStore, 1090 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1091 PPC970_DGroup_Cracked; 1092} 1093 1094// Stores with Update (pre-inc). 1095let PPC970_Unit = 2, mayStore = 1 in { 1096let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1097def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1098 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1099 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1100def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1101 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1102 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1103def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1104 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1105 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1106 1107def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1108 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1109 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1110 PPC970_DGroup_Cracked; 1111def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1112 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1113 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1114 PPC970_DGroup_Cracked; 1115def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1116 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1117 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1118 PPC970_DGroup_Cracked; 1119} // Interpretation64Bit 1120 1121def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1122 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1123 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1124 isPPC64; 1125 1126def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1127 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1128 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1129 PPC970_DGroup_Cracked, isPPC64; 1130} 1131 1132// Patterns to match the pre-inc stores. We can't put the patterns on 1133// the instruction definitions directly as ISel wants the address base 1134// and offset to be separate operands, not a single complex operand. 1135def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1136 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1137def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1138 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1139def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1140 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1141def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1142 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1143 1144def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1145 (STBUX8 $rS, $ptrreg, $ptroff)>; 1146def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1147 (STHUX8 $rS, $ptrreg, $ptroff)>; 1148def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1149 (STWUX8 $rS, $ptrreg, $ptroff)>; 1150def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1151 (STDUX $rS, $ptrreg, $ptroff)>; 1152 1153 1154//===----------------------------------------------------------------------===// 1155// Floating point instructions. 1156// 1157 1158 1159let PPC970_Unit = 3, hasSideEffects = 0, 1160 Uses = [RM] in { // FPU Operations. 1161defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1162 "fcfid", "$frD, $frB", IIC_FPGeneral, 1163 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1164defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1165 "fctid", "$frD, $frB", IIC_FPGeneral, 1166 []>, isPPC64; 1167defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1168 "fctidz", "$frD, $frB", IIC_FPGeneral, 1169 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1170 1171defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1172 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1173 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1174defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1175 "fcfids", "$frD, $frB", IIC_FPGeneral, 1176 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1177defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1178 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1179 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1180defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1181 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1182 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1183defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1184 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1185 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1186} 1187 1188 1189//===----------------------------------------------------------------------===// 1190// Instruction Patterns 1191// 1192 1193// Extensions and truncates to/from 32-bit regs. 1194def : Pat<(i64 (zext i32:$in)), 1195 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1196 0, 32)>; 1197def : Pat<(i64 (anyext i32:$in)), 1198 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1199def : Pat<(i32 (trunc i64:$in)), 1200 (EXTRACT_SUBREG $in, sub_32)>; 1201 1202// Implement the 'not' operation with the NOR instruction. 1203// (we could use the default xori pattern, but nor has lower latency on some 1204// cores (such as the A2)). 1205def i64not : OutPatFrag<(ops node:$in), 1206 (NOR8 $in, $in)>; 1207def : Pat<(not i64:$in), 1208 (i64not $in)>; 1209 1210// Extending loads with i64 targets. 1211def : Pat<(zextloadi1 iaddr:$src), 1212 (LBZ8 iaddr:$src)>; 1213def : Pat<(zextloadi1 xaddr:$src), 1214 (LBZX8 xaddr:$src)>; 1215def : Pat<(extloadi1 iaddr:$src), 1216 (LBZ8 iaddr:$src)>; 1217def : Pat<(extloadi1 xaddr:$src), 1218 (LBZX8 xaddr:$src)>; 1219def : Pat<(extloadi8 iaddr:$src), 1220 (LBZ8 iaddr:$src)>; 1221def : Pat<(extloadi8 xaddr:$src), 1222 (LBZX8 xaddr:$src)>; 1223def : Pat<(extloadi16 iaddr:$src), 1224 (LHZ8 iaddr:$src)>; 1225def : Pat<(extloadi16 xaddr:$src), 1226 (LHZX8 xaddr:$src)>; 1227def : Pat<(extloadi32 iaddr:$src), 1228 (LWZ8 iaddr:$src)>; 1229def : Pat<(extloadi32 xaddr:$src), 1230 (LWZX8 xaddr:$src)>; 1231 1232// Standard shifts. These are represented separately from the real shifts above 1233// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1234// amounts. 1235def : Pat<(sra i64:$rS, i32:$rB), 1236 (SRAD $rS, $rB)>; 1237def : Pat<(srl i64:$rS, i32:$rB), 1238 (SRD $rS, $rB)>; 1239def : Pat<(shl i64:$rS, i32:$rB), 1240 (SLD $rS, $rB)>; 1241 1242// SHL/SRL 1243def : Pat<(shl i64:$in, (i32 imm:$imm)), 1244 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1245def : Pat<(srl i64:$in, (i32 imm:$imm)), 1246 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1247 1248// ROTL 1249def : Pat<(rotl i64:$in, i32:$sh), 1250 (RLDCL $in, $sh, 0)>; 1251def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1252 (RLDICL $in, imm:$imm, 0)>; 1253 1254// Hi and Lo for Darwin Global Addresses. 1255def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1256def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1257def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1258def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1259def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1260def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1261def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1262def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1263def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1264 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1265def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1266 (ADDI8 $in, tglobaltlsaddr:$g)>; 1267def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1268 (ADDIS8 $in, tglobaladdr:$g)>; 1269def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1270 (ADDIS8 $in, tconstpool:$g)>; 1271def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1272 (ADDIS8 $in, tjumptable:$g)>; 1273def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1274 (ADDIS8 $in, tblockaddress:$g)>; 1275 1276// Patterns to match r+r indexed loads and stores for 1277// addresses without at least 4-byte alignment. 1278def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1279 (LWAX xoaddr:$src)>; 1280def : Pat<(i64 (unaligned4load xoaddr:$src)), 1281 (LDX xoaddr:$src)>; 1282def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1283 (STDX $rS, xoaddr:$dst)>; 1284 1285// 64-bits atomic loads and stores 1286def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1287def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1288 1289def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1290def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1291 1292let Predicates = [IsISA3_0] in { 1293 1294class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1295 InstrItinClass itin, list<dag> pattern> 1296 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1297 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1298 1299let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1300def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1301def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1302def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1303} 1304 1305// SLB Invalidate Entry Global 1306def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1307 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1308// SLB Synchronize 1309def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1310 1311} // IsISA3_0 1312