1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68 69//===----------------------------------------------------------------------===// 70// Calls. 71// 72 73let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 74let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 75 let isReturn = 1, Uses = [LR8, RM] in 76 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 77 [(retflag)]>, Requires<[In64BitMode]>; 78 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 146 "bctrl", IIC_BrB, [(PPCbctrl)]>, 147 Requires<[In64BitMode]>; 148 149 let isCodeGenOnly = 1 in { 150 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 152 []>, 153 Requires<[In64BitMode]>; 154 155 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 156 "bcctrl 12, $bi, 0", IIC_BrB, []>, 157 Requires<[In64BitMode]>; 158 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 159 "bcctrl 4, $bi, 0", IIC_BrB, []>, 160 Requires<[In64BitMode]>; 161 } 162 } 163} 164 165let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 166 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 167 def BCTRL8_LDinto_toc : 168 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 169 (ins memrix:$src), 170 "bctrl\n\tld 2, $src", IIC_BrB, 171 [(PPCbctrl_load_toc ixaddr:$src)]>, 172 Requires<[In64BitMode]>; 173} 174 175} // Interpretation64Bit 176 177// FIXME: Duplicating this for the asm parser should be unnecessary, but the 178// previous definition must be marked as CodeGen only to prevent decoding 179// conflicts. 180let Interpretation64Bit = 1, isAsmParserOnly = 1 in 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 182def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 183 "bl $func", IIC_BrB, []>; 184 185// Calls 186def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 187 (BL8 tglobaladdr:$dst)>; 188def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 189 (BL8_NOP tglobaladdr:$dst)>; 190 191def : Pat<(PPCcall (i64 texternalsym:$dst)), 192 (BL8 texternalsym:$dst)>; 193def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 194 (BL8_NOP texternalsym:$dst)>; 195 196// Atomic operations 197// FIXME: some of these might be used with constant operands. This will result 198// in constant materialization instructions that may be redundant. We currently 199// clean this up in PPCMIPeephole with calls to 200// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 201// in the first place. 202let Defs = [CR0] in { 203 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 204 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 205 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 206 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 207 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 208 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 209 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 211 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 214 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 217 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 220 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 223 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 226 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 227 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 229 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 232 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 233 234 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 235 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 236 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 237 238 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 239 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 240 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 241} 242 243// Instructions to support atomic operations 244let mayLoad = 1, hasSideEffects = 0 in { 245def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 247 248// Instruction to support lock versions of atomics 249// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 250def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 251 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 252 253let hasExtraDefRegAllocReq = 1 in 254def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 255 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 256 Requires<[IsISA3_0]>; 257} 258 259let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 260def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 261 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 262 263let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 264def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 265 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 266 Requires<[IsISA3_0]>; 267 268let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 269let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 270def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 271 (ins calltarget:$dst, i32imm:$offset), 272 "#TC_RETURNd8 $dst $offset", 273 []>; 274 275let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 276def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 277 "#TC_RETURNa8 $func $offset", 278 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 279 280let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 281def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 282 "#TC_RETURNr8 $dst $offset", 283 []>; 284 285let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 286 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 287def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 288 []>, 289 Requires<[In64BitMode]>; 290 291let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 292 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 293def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 294 "b $dst", IIC_BrB, 295 []>; 296 297let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 298 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 299def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 300 "ba $dst", IIC_BrB, 301 []>; 302} // Interpretation64Bit 303 304def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 305 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 306 307def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 308 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 309 310def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 311 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 312 313 314// 64-bit CR instructions 315let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 316let hasSideEffects = 0 in { 317// mtocrf's input needs to be prepared by shifting by an amount dependent 318// on the cr register selected. Thus, post-ra anti-dep breaking must not 319// later change that register assignment. 320let hasExtraDefRegAllocReq = 1 in { 321def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 322 "mtocrf $FXM, $ST", IIC_BrMCRX>, 323 PPC970_DGroup_First, PPC970_Unit_CRU; 324 325// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 326// is dependent on the cr fields being set. 327def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 328 "mtcrf $FXM, $rS", IIC_BrMCRX>, 329 PPC970_MicroCode, PPC970_Unit_CRU; 330} // hasExtraDefRegAllocReq = 1 331 332// mfocrf's input needs to be prepared by shifting by an amount dependent 333// on the cr register selected. Thus, post-ra anti-dep breaking must not 334// later change that register assignment. 335let hasExtraSrcRegAllocReq = 1 in { 336def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 337 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 338 PPC970_DGroup_First, PPC970_Unit_CRU; 339 340// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 341// is dependent on the cr fields being copied. 342def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 343 "mfcr $rT", IIC_SprMFCR>, 344 PPC970_MicroCode, PPC970_Unit_CRU; 345} // hasExtraSrcRegAllocReq = 1 346} // hasSideEffects = 0 347 348// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 349// is not. 350let hasSideEffects = 1 in { 351 let Defs = [CTR8] in 352 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 353 "#EH_SJLJ_SETJMP64", 354 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 355 Requires<[In64BitMode]>; 356} 357 358let hasSideEffects = 1, isBarrier = 1 in { 359 let isTerminator = 1 in 360 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 361 "#EH_SJLJ_LONGJMP64", 362 [(PPCeh_sjlj_longjmp addr:$buf)]>, 363 Requires<[In64BitMode]>; 364} 365 366def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 367 "mfspr $RT, $SPR", IIC_SprMFSPR>; 368def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 369 "mtspr $SPR, $RT", IIC_SprMTSPR>; 370 371 372//===----------------------------------------------------------------------===// 373// 64-bit SPR manipulation instrs. 374 375let Uses = [CTR8] in { 376def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 377 "mfctr $rT", IIC_SprMFSPR>, 378 PPC970_DGroup_First, PPC970_Unit_FXU; 379} 380let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 381def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 382 "mtctr $rS", IIC_SprMTSPR>, 383 PPC970_DGroup_First, PPC970_Unit_FXU; 384} 385let hasSideEffects = 1, Defs = [CTR8] in { 386let Pattern = [(int_ppc_mtctr i64:$rS)] in 387def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 388 "mtctr $rS", IIC_SprMTSPR>, 389 PPC970_DGroup_First, PPC970_Unit_FXU; 390} 391 392let Pattern = [(set i64:$rT, readcyclecounter)] in 393def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 394 "mfspr $rT, 268", IIC_SprMFTB>, 395 PPC970_DGroup_First, PPC970_Unit_FXU; 396// Note that encoding mftb using mfspr is now the preferred form, 397// and has been since at least ISA v2.03. The mftb instruction has 398// now been phased out. Using mfspr, however, is known not to work on 399// the POWER3. 400 401let Defs = [X1], Uses = [X1] in 402def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 403 [(set i64:$result, 404 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 405def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 406 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 407 408let Defs = [LR8] in { 409def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 410 "mtlr $rS", IIC_SprMTSPR>, 411 PPC970_DGroup_First, PPC970_Unit_FXU; 412} 413let Uses = [LR8] in { 414def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 415 "mflr $rT", IIC_SprMFSPR>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417} 418} // Interpretation64Bit 419 420//===----------------------------------------------------------------------===// 421// Fixed point instructions. 422// 423 424let PPC970_Unit = 1 in { // FXU Operations. 425let Interpretation64Bit = 1 in { 426let hasSideEffects = 0 in { 427let isCodeGenOnly = 1 in { 428 429let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 430def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 431 "li $rD, $imm", IIC_IntSimple, 432 [(set i64:$rD, imm64SExt16:$imm)]>; 433def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 434 "lis $rD, $imm", IIC_IntSimple, 435 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 436} 437 438// Logical ops. 439let isCommutable = 1 in { 440defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 441 "nand", "$rA, $rS, $rB", IIC_IntSimple, 442 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 443defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 444 "and", "$rA, $rS, $rB", IIC_IntSimple, 445 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 446} // isCommutable 447defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 448 "andc", "$rA, $rS, $rB", IIC_IntSimple, 449 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 450let isCommutable = 1 in { 451defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 452 "or", "$rA, $rS, $rB", IIC_IntSimple, 453 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 454defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 455 "nor", "$rA, $rS, $rB", IIC_IntSimple, 456 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 457} // isCommutable 458defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 459 "orc", "$rA, $rS, $rB", IIC_IntSimple, 460 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 461let isCommutable = 1 in { 462defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 463 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 464 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 465defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 466 "xor", "$rA, $rS, $rB", IIC_IntSimple, 467 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 468} // let isCommutable = 1 469 470// Logical ops with immediate. 471let Defs = [CR0] in { 472def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 473 "andi. $dst, $src1, $src2", IIC_IntGeneral, 474 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 475 isDOT; 476def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 477 "andis. $dst, $src1, $src2", IIC_IntGeneral, 478 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 479 isDOT; 480} 481def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 482 "ori $dst, $src1, $src2", IIC_IntSimple, 483 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 484def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 485 "oris $dst, $src1, $src2", IIC_IntSimple, 486 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 487def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 488 "xori $dst, $src1, $src2", IIC_IntSimple, 489 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 490def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 491 "xoris $dst, $src1, $src2", IIC_IntSimple, 492 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 493 494let isCommutable = 1 in 495defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 496 "add", "$rT, $rA, $rB", IIC_IntSimple, 497 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 498// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 499// initial-exec thread-local storage model. We need to forbid r0 here - 500// while it works for add just fine, the linker can relax this to local-exec 501// addi, which won't work for r0. 502def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 503 "add $rT, $rA, $rB", IIC_IntSimple, 504 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 505let mayLoad = 1 in { 506def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 507 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 508def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 509 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 510def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 511 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 512def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 513 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 514def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 515 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 516def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 517 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 518def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 519 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 520 521} 522 523let mayStore = 1 in { 524def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 525 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 526 PPC970_DGroup_Cracked; 527def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 528 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 529 PPC970_DGroup_Cracked; 530def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 531 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 532 PPC970_DGroup_Cracked; 533def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 534 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 535 PPC970_DGroup_Cracked; 536def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 537 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 538 PPC970_DGroup_Cracked; 539def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 540 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 541 PPC970_DGroup_Cracked; 542def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 543 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 544 PPC970_DGroup_Cracked; 545 546} 547 548let isCommutable = 1 in 549defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 550 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 551 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 552 PPC970_DGroup_Cracked; 553 554let Defs = [CARRY] in 555def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 556 "addic $rD, $rA, $imm", IIC_IntGeneral, 557 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 558def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 559 "addi $rD, $rA, $imm", IIC_IntSimple, 560 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 561def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 562 "addis $rD, $rA, $imm", IIC_IntSimple, 563 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 564 565let Defs = [CARRY] in { 566def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 567 "subfic $rD, $rA, $imm", IIC_IntGeneral, 568 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 569} 570defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 571 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 572 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 573 PPC970_DGroup_Cracked; 574defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 575 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 576 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 577defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 578 "neg", "$rT, $rA", IIC_IntSimple, 579 [(set i64:$rT, (ineg i64:$rA))]>; 580let Uses = [CARRY] in { 581let isCommutable = 1 in 582defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 583 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 584 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 585defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 586 "addme", "$rT, $rA", IIC_IntGeneral, 587 [(set i64:$rT, (adde i64:$rA, -1))]>; 588defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 589 "addze", "$rT, $rA", IIC_IntGeneral, 590 [(set i64:$rT, (adde i64:$rA, 0))]>; 591defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 592 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 593 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 594defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 595 "subfme", "$rT, $rA", IIC_IntGeneral, 596 [(set i64:$rT, (sube -1, i64:$rA))]>; 597defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 598 "subfze", "$rT, $rA", IIC_IntGeneral, 599 [(set i64:$rT, (sube 0, i64:$rA))]>; 600} 601} // isCodeGenOnly 602 603// FIXME: Duplicating this for the asm parser should be unnecessary, but the 604// previous definition must be marked as CodeGen only to prevent decoding 605// conflicts. 606let isAsmParserOnly = 1 in { 607def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 608 "add $rT, $rA, $rB", IIC_IntSimple, []>; 609 610let mayLoad = 1 in { 611def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 612 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 613def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 614 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 615def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 616 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 617def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 618 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 619} 620 621let mayStore = 1 in { 622def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 623 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 624 PPC970_DGroup_Cracked; 625def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 626 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 627 PPC970_DGroup_Cracked; 628def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 629 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 630 PPC970_DGroup_Cracked; 631def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 632 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 633 PPC970_DGroup_Cracked; 634} 635} 636 637let isCommutable = 1 in { 638defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 639 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 640 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 641defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 642 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 643 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 644} // isCommutable 645} 646} // Interpretation64Bit 647 648let isCompare = 1, hasSideEffects = 0 in { 649 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 650 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 651 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 652 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 653 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 654 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 655 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 656 "cmpldi $dst, $src1, $src2", 657 IIC_IntCompare>, isPPC64; 658 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 659 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 660 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 661 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 662 Requires<[IsISA3_0]>; 663 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 664 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 665 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 666} 667 668let hasSideEffects = 0 in { 669defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 670 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 671 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 672defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 673 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 674 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 675defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 676 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 677 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 678 679let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 680defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 681 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 682defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 683 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 684 Requires<[IsISA3_0]>; 685 686defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 687 "extsb", "$rA, $rS", IIC_IntSimple, 688 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 689defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 690 "extsh", "$rA, $rS", IIC_IntSimple, 691 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 692 693defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 694 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 695defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 696 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 697} // Interpretation64Bit 698 699// For fast-isel: 700let isCodeGenOnly = 1 in { 701def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 702 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 703def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 704 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 705} // isCodeGenOnly for fast-isel 706 707defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 708 "extsw", "$rA, $rS", IIC_IntSimple, 709 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 710let Interpretation64Bit = 1, isCodeGenOnly = 1 in 711defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 712 "extsw", "$rA, $rS", IIC_IntSimple, 713 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 714let isCodeGenOnly = 1 in 715def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 716 "extsw $rA, $rS", IIC_IntSimple, 717 []>, isPPC64; 718 719defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 720 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 721 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 722 723defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins gprc:$rS, u6imm:$SH), 724 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 725 [(set i64:$rA, (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 726 isPPC64, Requires<[IsISA3_0]>; 727 728// For fast-isel: 729let isCodeGenOnly = 1, Defs = [CARRY] in 730def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 731 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 732 733defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 734 "cntlzd", "$rA, $rS", IIC_IntGeneral, 735 [(set i64:$rA, (ctlz i64:$rS))]>; 736defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 737 "cnttzd", "$rA, $rS", IIC_IntGeneral, 738 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 739def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 740 "popcntd $rA, $rS", IIC_IntGeneral, 741 [(set i64:$rA, (ctpop i64:$rS))]>; 742def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 743 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 744 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 745 isPPC64, Requires<[HasBPERMD]>; 746 747let isCodeGenOnly = 1, isCommutable = 1 in 748def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 749 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 750 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 751 752// popcntw also does a population count on the high 32 bits (storing the 753// results in the high 32-bits of the output). We'll ignore that here (which is 754// safe because we never separately use the high part of the 64-bit registers). 755def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 756 "popcntw $rA, $rS", IIC_IntGeneral, 757 [(set i32:$rA, (ctpop i32:$rS))]>; 758 759def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 760 "popcntb $rA, $rS", IIC_IntGeneral, []>; 761 762defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 763 "divd", "$rT, $rA, $rB", IIC_IntDivD, 764 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 765defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 766 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 767 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 768def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 769 "divde $rT, $rA, $rB", IIC_IntDivD, 770 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 771 isPPC64, Requires<[HasExtDiv]>; 772 773let Predicates = [IsISA3_0] in { 774def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 775 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 776def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 777 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 778def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 779 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 780def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 781 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 782let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 783 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 784 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 785} 786def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 787 "darn $RT, $L", IIC_LdStLD>, isPPC64; 788def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 789 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 790def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 791 "modsd $rT, $rA, $rB", IIC_IntDivW, 792 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 793def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 794 "modud $rT, $rA, $rB", IIC_IntDivW, 795 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 796} 797 798let Defs = [CR0] in 799def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 800 "divde. $rT, $rA, $rB", IIC_IntDivD, 801 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 802 isPPC64, Requires<[HasExtDiv]>; 803def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 804 "divdeu $rT, $rA, $rB", IIC_IntDivD, 805 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 806 isPPC64, Requires<[HasExtDiv]>; 807let Defs = [CR0] in 808def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 809 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 810 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 811 isPPC64, Requires<[HasExtDiv]>; 812let isCommutable = 1 in 813defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 814 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 815 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 816let Interpretation64Bit = 1, isCodeGenOnly = 1 in 817def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 818 "mulli $rD, $rA, $imm", IIC_IntMulLI, 819 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 820} 821 822let hasSideEffects = 0 in { 823defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 824 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 825 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 826 []>, isPPC64, RegConstraint<"$rSi = $rA">, 827 NoEncode<"$rSi">; 828 829// Rotate instructions. 830defm RLDCL : MDSForm_1r<30, 8, 831 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 832 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 833 []>, isPPC64; 834defm RLDCR : MDSForm_1r<30, 9, 835 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 836 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 837 []>, isPPC64; 838defm RLDICL : MDForm_1r<30, 0, 839 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 840 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 841 []>, isPPC64; 842// For fast-isel: 843let isCodeGenOnly = 1 in 844def RLDICL_32_64 : MDForm_1<30, 0, 845 (outs g8rc:$rA), 846 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 847 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 848 []>, isPPC64; 849// End fast-isel. 850let Interpretation64Bit = 1, isCodeGenOnly = 1 in 851defm RLDICL_32 : MDForm_1r<30, 0, 852 (outs gprc:$rA), 853 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 854 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 855 []>, isPPC64; 856defm RLDICR : MDForm_1r<30, 1, 857 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 858 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 859 []>, isPPC64; 860let isCodeGenOnly = 1 in 861def RLDICR_32 : MDForm_1<30, 1, 862 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 863 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 864 []>, isPPC64; 865defm RLDIC : MDForm_1r<30, 2, 866 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 867 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 868 []>, isPPC64; 869 870let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 871defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 872 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 873 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 874 []>; 875 876defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 877 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 878 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 879 []>; 880 881// RLWIMI can be commuted if the rotate amount is zero. 882let Interpretation64Bit = 1, isCodeGenOnly = 1 in 883defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 884 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 885 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 886 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 887 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 888 889let isSelect = 1 in 890def ISEL8 : AForm_4<31, 15, 891 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 892 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 893 []>; 894} // Interpretation64Bit 895} // hasSideEffects = 0 896} // End FXU Operations. 897 898 899//===----------------------------------------------------------------------===// 900// Load/Store instructions. 901// 902 903 904// Sign extending loads. 905let PPC970_Unit = 2 in { 906let Interpretation64Bit = 1, isCodeGenOnly = 1 in 907def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 908 "lha $rD, $src", IIC_LdStLHA, 909 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 910 PPC970_DGroup_Cracked; 911def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 912 "lwa $rD, $src", IIC_LdStLWA, 913 [(set i64:$rD, 914 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 915 PPC970_DGroup_Cracked; 916let Interpretation64Bit = 1, isCodeGenOnly = 1 in 917def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 918 "lhax $rD, $src", IIC_LdStLHA, 919 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 920 PPC970_DGroup_Cracked; 921def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 922 "lwax $rD, $src", IIC_LdStLHA, 923 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 924 PPC970_DGroup_Cracked; 925// For fast-isel: 926let isCodeGenOnly = 1, mayLoad = 1 in { 927def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 928 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 929 PPC970_DGroup_Cracked; 930def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 931 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 932 PPC970_DGroup_Cracked; 933} // end fast-isel isCodeGenOnly 934 935// Update forms. 936let mayLoad = 1, hasSideEffects = 0 in { 937let Interpretation64Bit = 1, isCodeGenOnly = 1 in 938def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 939 (ins memri:$addr), 940 "lhau $rD, $addr", IIC_LdStLHAU, 941 []>, RegConstraint<"$addr.reg = $ea_result">, 942 NoEncode<"$ea_result">; 943// NO LWAU! 944 945let Interpretation64Bit = 1, isCodeGenOnly = 1 in 946def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 947 (ins memrr:$addr), 948 "lhaux $rD, $addr", IIC_LdStLHAUX, 949 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 950 NoEncode<"$ea_result">; 951def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 952 (ins memrr:$addr), 953 "lwaux $rD, $addr", IIC_LdStLHAUX, 954 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 955 NoEncode<"$ea_result">, isPPC64; 956} 957} 958 959let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 960// Zero extending loads. 961let PPC970_Unit = 2 in { 962def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 963 "lbz $rD, $src", IIC_LdStLoad, 964 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 965def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 966 "lhz $rD, $src", IIC_LdStLoad, 967 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 968def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 969 "lwz $rD, $src", IIC_LdStLoad, 970 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 971 972def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 973 "lbzx $rD, $src", IIC_LdStLoad, 974 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 975def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 976 "lhzx $rD, $src", IIC_LdStLoad, 977 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 978def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 979 "lwzx $rD, $src", IIC_LdStLoad, 980 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 981 982 983// Update forms. 984let mayLoad = 1, hasSideEffects = 0 in { 985def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 986 (ins memri:$addr), 987 "lbzu $rD, $addr", IIC_LdStLoadUpd, 988 []>, RegConstraint<"$addr.reg = $ea_result">, 989 NoEncode<"$ea_result">; 990def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 991 (ins memri:$addr), 992 "lhzu $rD, $addr", IIC_LdStLoadUpd, 993 []>, RegConstraint<"$addr.reg = $ea_result">, 994 NoEncode<"$ea_result">; 995def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 996 (ins memri:$addr), 997 "lwzu $rD, $addr", IIC_LdStLoadUpd, 998 []>, RegConstraint<"$addr.reg = $ea_result">, 999 NoEncode<"$ea_result">; 1000 1001def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1002 (ins memrr:$addr), 1003 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1004 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1005 NoEncode<"$ea_result">; 1006def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1007 (ins memrr:$addr), 1008 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1009 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1010 NoEncode<"$ea_result">; 1011def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1012 (ins memrr:$addr), 1013 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1014 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1015 NoEncode<"$ea_result">; 1016} 1017} 1018} // Interpretation64Bit 1019 1020 1021// Full 8-byte loads. 1022let PPC970_Unit = 2 in { 1023def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1024 "ld $rD, $src", IIC_LdStLD, 1025 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 1026// The following four definitions are selected for small code model only. 1027// Otherwise, we need to create two instructions to form a 32-bit offset, 1028// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1029def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1030 "#LDtoc", 1031 [(set i64:$rD, 1032 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1033def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1034 "#LDtocJTI", 1035 [(set i64:$rD, 1036 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1037def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1038 "#LDtocCPT", 1039 [(set i64:$rD, 1040 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1041def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1042 "#LDtocCPT", 1043 [(set i64:$rD, 1044 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1045 1046def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1047 "ldx $rD, $src", IIC_LdStLD, 1048 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 1049def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1050 "ldbrx $rD, $src", IIC_LdStLoad, 1051 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1052 1053let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1054def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1055 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1056def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1057 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1058} 1059 1060let mayLoad = 1, hasSideEffects = 0 in { 1061def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1062 (ins memrix:$addr), 1063 "ldu $rD, $addr", IIC_LdStLDU, 1064 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1065 NoEncode<"$ea_result">; 1066 1067def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1068 (ins memrr:$addr), 1069 "ldux $rD, $addr", IIC_LdStLDUX, 1070 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1071 NoEncode<"$ea_result">, isPPC64; 1072 1073def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1074 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1075 Requires<[IsISA3_0]>; 1076} 1077} 1078 1079// Support for medium and large code model. 1080let hasSideEffects = 0 in { 1081let isReMaterializable = 1 in { 1082def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1083 "#ADDIStocHA", []>, isPPC64; 1084def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1085 "#ADDItocL", []>, isPPC64; 1086} 1087let mayLoad = 1 in 1088def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1089 "#LDtocL", []>, isPPC64; 1090} 1091 1092// Support for thread-local storage. 1093def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1094 "#ADDISgotTprelHA", 1095 [(set i64:$rD, 1096 (PPCaddisGotTprelHA i64:$reg, 1097 tglobaltlsaddr:$disp))]>, 1098 isPPC64; 1099def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1100 "#LDgotTprelL", 1101 [(set i64:$rD, 1102 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1103 isPPC64; 1104 1105let Defs = [CR7], Itinerary = IIC_LdStSync in 1106def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1107 1108def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1109 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1110def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1111 "#ADDIStlsgdHA", 1112 [(set i64:$rD, 1113 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1114 isPPC64; 1115def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1116 "#ADDItlsgdL", 1117 [(set i64:$rD, 1118 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1119 isPPC64; 1120// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1121// explicitly defined when this op is created, so not mentioned here. 1122// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1123// correct because the branch select pass is relying on it. 1124let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1125 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1126def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1127 "#GETtlsADDR", 1128 [(set i64:$rD, 1129 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1130 isPPC64; 1131// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1132// are true defines while the rest of the Defs are clobbers. 1133let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1134 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1135 in 1136def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1137 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1138 "#ADDItlsgdLADDR", 1139 [(set i64:$rD, 1140 (PPCaddiTlsgdLAddr i64:$reg, 1141 tglobaltlsaddr:$disp, 1142 tglobaltlsaddr:$sym))]>, 1143 isPPC64; 1144def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1145 "#ADDIStlsldHA", 1146 [(set i64:$rD, 1147 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1148 isPPC64; 1149def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1150 "#ADDItlsldL", 1151 [(set i64:$rD, 1152 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1153 isPPC64; 1154// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1155// explicitly defined when this op is created, so not mentioned here. 1156let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1157 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1158def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1159 "#GETtlsldADDR", 1160 [(set i64:$rD, 1161 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1162 isPPC64; 1163// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1164// are true defines, while the rest of the Defs are clobbers. 1165let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1166 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1167 in 1168def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1169 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1170 "#ADDItlsldLADDR", 1171 [(set i64:$rD, 1172 (PPCaddiTlsldLAddr i64:$reg, 1173 tglobaltlsaddr:$disp, 1174 tglobaltlsaddr:$sym))]>, 1175 isPPC64; 1176def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1177 "#ADDISdtprelHA", 1178 [(set i64:$rD, 1179 (PPCaddisDtprelHA i64:$reg, 1180 tglobaltlsaddr:$disp))]>, 1181 isPPC64; 1182def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1183 "#ADDIdtprelL", 1184 [(set i64:$rD, 1185 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1186 isPPC64; 1187 1188let PPC970_Unit = 2 in { 1189let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1190// Truncating stores. 1191def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1192 "stb $rS, $src", IIC_LdStStore, 1193 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1194def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1195 "sth $rS, $src", IIC_LdStStore, 1196 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1197def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1198 "stw $rS, $src", IIC_LdStStore, 1199 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1200def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1201 "stbx $rS, $dst", IIC_LdStStore, 1202 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1203 PPC970_DGroup_Cracked; 1204def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1205 "sthx $rS, $dst", IIC_LdStStore, 1206 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1207 PPC970_DGroup_Cracked; 1208def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1209 "stwx $rS, $dst", IIC_LdStStore, 1210 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1211 PPC970_DGroup_Cracked; 1212} // Interpretation64Bit 1213 1214// Normal 8-byte stores. 1215def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1216 "std $rS, $dst", IIC_LdStSTD, 1217 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1218def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1219 "stdx $rS, $dst", IIC_LdStSTD, 1220 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1221 PPC970_DGroup_Cracked; 1222def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1223 "stdbrx $rS, $dst", IIC_LdStStore, 1224 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1225 PPC970_DGroup_Cracked; 1226} 1227 1228// Stores with Update (pre-inc). 1229let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1230let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1231def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1232 "stbu $rS, $dst", IIC_LdStSTU, []>, 1233 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1234def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1235 "sthu $rS, $dst", IIC_LdStSTU, []>, 1236 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1237def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1238 "stwu $rS, $dst", IIC_LdStSTU, []>, 1239 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1240 1241def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1242 (ins g8rc:$rS, memrr:$dst), 1243 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1244 RegConstraint<"$dst.ptrreg = $ea_res">, 1245 NoEncode<"$ea_res">, 1246 PPC970_DGroup_Cracked; 1247def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1248 (ins g8rc:$rS, memrr:$dst), 1249 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1250 RegConstraint<"$dst.ptrreg = $ea_res">, 1251 NoEncode<"$ea_res">, 1252 PPC970_DGroup_Cracked; 1253def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1254 (ins g8rc:$rS, memrr:$dst), 1255 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1256 RegConstraint<"$dst.ptrreg = $ea_res">, 1257 NoEncode<"$ea_res">, 1258 PPC970_DGroup_Cracked; 1259} // Interpretation64Bit 1260 1261def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1262 (ins g8rc:$rS, memrix:$dst), 1263 "stdu $rS, $dst", IIC_LdStSTU, []>, 1264 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1265 isPPC64; 1266 1267def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1268 (ins g8rc:$rS, memrr:$dst), 1269 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1270 RegConstraint<"$dst.ptrreg = $ea_res">, 1271 NoEncode<"$ea_res">, 1272 PPC970_DGroup_Cracked, isPPC64; 1273} 1274 1275// Patterns to match the pre-inc stores. We can't put the patterns on 1276// the instruction definitions directly as ISel wants the address base 1277// and offset to be separate operands, not a single complex operand. 1278def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1279 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1280def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1281 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1282def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1283 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1284def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1285 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1286 1287def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1288 (STBUX8 $rS, $ptrreg, $ptroff)>; 1289def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1290 (STHUX8 $rS, $ptrreg, $ptroff)>; 1291def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1292 (STWUX8 $rS, $ptrreg, $ptroff)>; 1293def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1294 (STDUX $rS, $ptrreg, $ptroff)>; 1295 1296 1297//===----------------------------------------------------------------------===// 1298// Floating point instructions. 1299// 1300 1301 1302let PPC970_Unit = 3, hasSideEffects = 0, 1303 Uses = [RM] in { // FPU Operations. 1304defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1305 "fcfid", "$frD, $frB", IIC_FPGeneral, 1306 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1307defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1308 "fctid", "$frD, $frB", IIC_FPGeneral, 1309 []>, isPPC64; 1310defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1311 "fctidu", "$frD, $frB", IIC_FPGeneral, 1312 []>, isPPC64; 1313defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1314 "fctidz", "$frD, $frB", IIC_FPGeneral, 1315 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1316 1317defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1318 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1319 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1320defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1321 "fcfids", "$frD, $frB", IIC_FPGeneral, 1322 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1323defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1324 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1325 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1326defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1327 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1328 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1329defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1330 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1331 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1332} 1333 1334 1335//===----------------------------------------------------------------------===// 1336// Instruction Patterns 1337// 1338 1339// Extensions and truncates to/from 32-bit regs. 1340def : Pat<(i64 (zext i32:$in)), 1341 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1342 0, 32)>; 1343def : Pat<(i64 (anyext i32:$in)), 1344 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1345def : Pat<(i32 (trunc i64:$in)), 1346 (EXTRACT_SUBREG $in, sub_32)>; 1347 1348// Implement the 'not' operation with the NOR instruction. 1349// (we could use the default xori pattern, but nor has lower latency on some 1350// cores (such as the A2)). 1351def i64not : OutPatFrag<(ops node:$in), 1352 (NOR8 $in, $in)>; 1353def : Pat<(not i64:$in), 1354 (i64not $in)>; 1355 1356// Extending loads with i64 targets. 1357def : Pat<(zextloadi1 iaddr:$src), 1358 (LBZ8 iaddr:$src)>; 1359def : Pat<(zextloadi1 xaddr:$src), 1360 (LBZX8 xaddr:$src)>; 1361def : Pat<(extloadi1 iaddr:$src), 1362 (LBZ8 iaddr:$src)>; 1363def : Pat<(extloadi1 xaddr:$src), 1364 (LBZX8 xaddr:$src)>; 1365def : Pat<(extloadi8 iaddr:$src), 1366 (LBZ8 iaddr:$src)>; 1367def : Pat<(extloadi8 xaddr:$src), 1368 (LBZX8 xaddr:$src)>; 1369def : Pat<(extloadi16 iaddr:$src), 1370 (LHZ8 iaddr:$src)>; 1371def : Pat<(extloadi16 xaddr:$src), 1372 (LHZX8 xaddr:$src)>; 1373def : Pat<(extloadi32 iaddr:$src), 1374 (LWZ8 iaddr:$src)>; 1375def : Pat<(extloadi32 xaddr:$src), 1376 (LWZX8 xaddr:$src)>; 1377 1378// Standard shifts. These are represented separately from the real shifts above 1379// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1380// amounts. 1381def : Pat<(sra i64:$rS, i32:$rB), 1382 (SRAD $rS, $rB)>; 1383def : Pat<(srl i64:$rS, i32:$rB), 1384 (SRD $rS, $rB)>; 1385def : Pat<(shl i64:$rS, i32:$rB), 1386 (SLD $rS, $rB)>; 1387 1388// SUBFIC 1389def : Pat<(sub imm64SExt16:$imm, i64:$in), 1390 (SUBFIC8 $in, imm:$imm)>; 1391 1392// SHL/SRL 1393def : Pat<(shl i64:$in, (i32 imm:$imm)), 1394 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1395def : Pat<(srl i64:$in, (i32 imm:$imm)), 1396 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1397 1398// ROTL 1399def : Pat<(rotl i64:$in, i32:$sh), 1400 (RLDCL $in, $sh, 0)>; 1401def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1402 (RLDICL $in, imm:$imm, 0)>; 1403 1404// Hi and Lo for Darwin Global Addresses. 1405def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1406def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1407def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1408def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1409def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1410def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1411def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1412def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1413def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1414 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1415def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1416 (ADDI8 $in, tglobaltlsaddr:$g)>; 1417def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1418 (ADDIS8 $in, tglobaladdr:$g)>; 1419def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1420 (ADDIS8 $in, tconstpool:$g)>; 1421def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1422 (ADDIS8 $in, tjumptable:$g)>; 1423def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1424 (ADDIS8 $in, tblockaddress:$g)>; 1425 1426// Patterns to match r+r indexed loads and stores for 1427// addresses without at least 4-byte alignment. 1428def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1429 (LWAX xoaddr:$src)>; 1430def : Pat<(i64 (unaligned4load xoaddr:$src)), 1431 (LDX xoaddr:$src)>; 1432def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1433 (STDX $rS, xoaddr:$dst)>; 1434 1435// 64-bits atomic loads and stores 1436def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1437def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1438 1439def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1440def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1441 1442let Predicates = [IsISA3_0] in { 1443 1444class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1445 InstrItinClass itin, list<dag> pattern> 1446 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1447 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1448 1449let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1450def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1451def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1452def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1453} 1454 1455// SLB Invalidate Entry Global 1456def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1457 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1458// SLB Synchronize 1459def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1460 1461} // IsISA3_0 1462