1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstPrinter.h"
15 #include "PPCInstrInfo.h"
16 #include "MCTargetDesc/PPCMCTargetDesc.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOpcodes.h"
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "asm-printer"
30 
31 // FIXME: Once the integrated assembler supports full register names, tie this
32 // to the verbose-asm setting.
33 static cl::opt<bool>
34 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
35              cl::desc("Use full register names when printing assembly"));
36 
37 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
38 static cl::opt<bool>
39 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
40              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
41 
42 #define PRINT_ALIAS_INSTR
43 #include "PPCGenAsmWriter.inc"
44 
45 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
46   const char *RegName = getRegisterName(RegNo);
47   if (RegName[0] == 'q' /* QPX */) {
48     // The system toolchain on the BG/Q does not understand QPX register names
49     // in .cfi_* directives, so print the name of the floating-point
50     // subregister instead.
51     std::string RN(RegName);
52 
53     RN[0] = 'f';
54     OS << RN;
55 
56     return;
57   }
58 
59   OS << RegName;
60 }
61 
62 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
63                                StringRef Annot, const MCSubtargetInfo &STI) {
64   // Check for slwi/srwi mnemonics.
65   if (MI->getOpcode() == PPC::RLWINM) {
66     unsigned char SH = MI->getOperand(2).getImm();
67     unsigned char MB = MI->getOperand(3).getImm();
68     unsigned char ME = MI->getOperand(4).getImm();
69     bool useSubstituteMnemonic = false;
70     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
71       O << "\tslwi "; useSubstituteMnemonic = true;
72     }
73     if (SH <= 31 && MB == (32-SH) && ME == 31) {
74       O << "\tsrwi "; useSubstituteMnemonic = true;
75       SH = 32-SH;
76     }
77     if (useSubstituteMnemonic) {
78       printOperand(MI, 0, O);
79       O << ", ";
80       printOperand(MI, 1, O);
81       O << ", " << (unsigned int)SH;
82 
83       printAnnotation(O, Annot);
84       return;
85     }
86   }
87 
88   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
89       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
90     O << "\tmr ";
91     printOperand(MI, 0, O);
92     O << ", ";
93     printOperand(MI, 1, O);
94     printAnnotation(O, Annot);
95     return;
96   }
97 
98   if (MI->getOpcode() == PPC::RLDICR) {
99     unsigned char SH = MI->getOperand(2).getImm();
100     unsigned char ME = MI->getOperand(3).getImm();
101     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
102     if (63-SH == ME) {
103       O << "\tsldi ";
104       printOperand(MI, 0, O);
105       O << ", ";
106       printOperand(MI, 1, O);
107       O << ", " << (unsigned int)SH;
108       printAnnotation(O, Annot);
109       return;
110     }
111   }
112 
113   // dcbt[st] is printed manually here because:
114   //  1. The assembly syntax is different between embedded and server targets
115   //  2. We must print the short mnemonics for TH == 0 because the
116   //     embedded/server syntax default will not be stable across assemblers
117   //  The syntax for dcbt is:
118   //    dcbt ra, rb, th [server]
119   //    dcbt th, ra, rb [embedded]
120   //  where th can be omitted when it is 0. dcbtst is the same.
121   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
122     unsigned char TH = MI->getOperand(0).getImm();
123     O << "\tdcbt";
124     if (MI->getOpcode() == PPC::DCBTST)
125       O << "st";
126     if (TH == 16)
127       O << "t";
128     O << " ";
129 
130     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
131     if (IsBookE && TH != 0 && TH != 16)
132       O << (unsigned int) TH << ", ";
133 
134     printOperand(MI, 1, O);
135     O << ", ";
136     printOperand(MI, 2, O);
137 
138     if (!IsBookE && TH != 0 && TH != 16)
139       O << ", " << (unsigned int) TH;
140 
141     printAnnotation(O, Annot);
142     return;
143   }
144 
145   if (MI->getOpcode() == PPC::DCBF) {
146     unsigned char L = MI->getOperand(0).getImm();
147     if (!L || L == 1 || L == 3) {
148       O << "\tdcbf";
149       if (L == 1 || L == 3)
150         O << "l";
151       if (L == 3)
152         O << "p";
153       O << " ";
154 
155       printOperand(MI, 1, O);
156       O << ", ";
157       printOperand(MI, 2, O);
158 
159       printAnnotation(O, Annot);
160       return;
161     }
162   }
163 
164   if (!printAliasInstr(MI, O))
165     printInstruction(MI, O);
166   printAnnotation(O, Annot);
167 }
168 
169 
170 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
171                                            raw_ostream &O,
172                                            const char *Modifier) {
173   unsigned Code = MI->getOperand(OpNo).getImm();
174 
175   if (StringRef(Modifier) == "cc") {
176     switch ((PPC::Predicate)Code) {
177     case PPC::PRED_LT_MINUS:
178     case PPC::PRED_LT_PLUS:
179     case PPC::PRED_LT:
180       O << "lt";
181       return;
182     case PPC::PRED_LE_MINUS:
183     case PPC::PRED_LE_PLUS:
184     case PPC::PRED_LE:
185       O << "le";
186       return;
187     case PPC::PRED_EQ_MINUS:
188     case PPC::PRED_EQ_PLUS:
189     case PPC::PRED_EQ:
190       O << "eq";
191       return;
192     case PPC::PRED_GE_MINUS:
193     case PPC::PRED_GE_PLUS:
194     case PPC::PRED_GE:
195       O << "ge";
196       return;
197     case PPC::PRED_GT_MINUS:
198     case PPC::PRED_GT_PLUS:
199     case PPC::PRED_GT:
200       O << "gt";
201       return;
202     case PPC::PRED_NE_MINUS:
203     case PPC::PRED_NE_PLUS:
204     case PPC::PRED_NE:
205       O << "ne";
206       return;
207     case PPC::PRED_UN_MINUS:
208     case PPC::PRED_UN_PLUS:
209     case PPC::PRED_UN:
210       O << "un";
211       return;
212     case PPC::PRED_NU_MINUS:
213     case PPC::PRED_NU_PLUS:
214     case PPC::PRED_NU:
215       O << "nu";
216       return;
217     case PPC::PRED_BIT_SET:
218     case PPC::PRED_BIT_UNSET:
219       llvm_unreachable("Invalid use of bit predicate code");
220     }
221     llvm_unreachable("Invalid predicate code");
222   }
223 
224   if (StringRef(Modifier) == "pm") {
225     switch ((PPC::Predicate)Code) {
226     case PPC::PRED_LT:
227     case PPC::PRED_LE:
228     case PPC::PRED_EQ:
229     case PPC::PRED_GE:
230     case PPC::PRED_GT:
231     case PPC::PRED_NE:
232     case PPC::PRED_UN:
233     case PPC::PRED_NU:
234       return;
235     case PPC::PRED_LT_MINUS:
236     case PPC::PRED_LE_MINUS:
237     case PPC::PRED_EQ_MINUS:
238     case PPC::PRED_GE_MINUS:
239     case PPC::PRED_GT_MINUS:
240     case PPC::PRED_NE_MINUS:
241     case PPC::PRED_UN_MINUS:
242     case PPC::PRED_NU_MINUS:
243       O << "-";
244       return;
245     case PPC::PRED_LT_PLUS:
246     case PPC::PRED_LE_PLUS:
247     case PPC::PRED_EQ_PLUS:
248     case PPC::PRED_GE_PLUS:
249     case PPC::PRED_GT_PLUS:
250     case PPC::PRED_NE_PLUS:
251     case PPC::PRED_UN_PLUS:
252     case PPC::PRED_NU_PLUS:
253       O << "+";
254       return;
255     case PPC::PRED_BIT_SET:
256     case PPC::PRED_BIT_UNSET:
257       llvm_unreachable("Invalid use of bit predicate code");
258     }
259     llvm_unreachable("Invalid predicate code");
260   }
261 
262   assert(StringRef(Modifier) == "reg" &&
263          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
264   printOperand(MI, OpNo+1, O);
265 }
266 
267 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
268                                        raw_ostream &O) {
269   unsigned Code = MI->getOperand(OpNo).getImm();
270   if (Code == 2)
271     O << "-";
272   else if (Code == 3)
273     O << "+";
274 }
275 
276 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
277                                        raw_ostream &O) {
278   unsigned int Value = MI->getOperand(OpNo).getImm();
279   assert(Value <= 1 && "Invalid u1imm argument!");
280   O << (unsigned int)Value;
281 }
282 
283 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
284                                        raw_ostream &O) {
285   unsigned int Value = MI->getOperand(OpNo).getImm();
286   assert(Value <= 3 && "Invalid u2imm argument!");
287   O << (unsigned int)Value;
288 }
289 
290 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
291                                        raw_ostream &O) {
292   unsigned int Value = MI->getOperand(OpNo).getImm();
293   assert(Value <= 8 && "Invalid u3imm argument!");
294   O << (unsigned int)Value;
295 }
296 
297 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
298                                        raw_ostream &O) {
299   unsigned int Value = MI->getOperand(OpNo).getImm();
300   assert(Value <= 15 && "Invalid u4imm argument!");
301   O << (unsigned int)Value;
302 }
303 
304 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
305                                        raw_ostream &O) {
306   int Value = MI->getOperand(OpNo).getImm();
307   Value = SignExtend32<5>(Value);
308   O << (int)Value;
309 }
310 
311 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
312                                        raw_ostream &O) {
313   unsigned int Value = MI->getOperand(OpNo).getImm();
314   assert(Value <= 31 && "Invalid u5imm argument!");
315   O << (unsigned int)Value;
316 }
317 
318 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
319                                        raw_ostream &O) {
320   unsigned int Value = MI->getOperand(OpNo).getImm();
321   assert(Value <= 63 && "Invalid u6imm argument!");
322   O << (unsigned int)Value;
323 }
324 
325 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
326                                        raw_ostream &O) {
327   unsigned int Value = MI->getOperand(OpNo).getImm();
328   assert(Value <= 127 && "Invalid u7imm argument!");
329   O << (unsigned int)Value;
330 }
331 
332 // Operands of BUILD_VECTOR are signed and we use this to print operands
333 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
334 // print as unsigned.
335 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
336                                        raw_ostream &O) {
337   unsigned char Value = MI->getOperand(OpNo).getImm();
338   O << (unsigned int)Value;
339 }
340 
341 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
342                                         raw_ostream &O) {
343   unsigned short Value = MI->getOperand(OpNo).getImm();
344   assert(Value <= 1023 && "Invalid u10imm argument!");
345   O << (unsigned short)Value;
346 }
347 
348 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
349                                         raw_ostream &O) {
350   unsigned short Value = MI->getOperand(OpNo).getImm();
351   assert(Value <= 4095 && "Invalid u12imm argument!");
352   O << (unsigned short)Value;
353 }
354 
355 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
356                                         raw_ostream &O) {
357   if (MI->getOperand(OpNo).isImm())
358     O << (short)MI->getOperand(OpNo).getImm();
359   else
360     printOperand(MI, OpNo, O);
361 }
362 
363 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
364                                         raw_ostream &O) {
365   if (MI->getOperand(OpNo).isImm())
366     O << (unsigned short)MI->getOperand(OpNo).getImm();
367   else
368     printOperand(MI, OpNo, O);
369 }
370 
371 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
372                                         raw_ostream &O) {
373   if (!MI->getOperand(OpNo).isImm())
374     return printOperand(MI, OpNo, O);
375 
376   // Branches can take an immediate operand.  This is used by the branch
377   // selection pass to print .+8, an eight byte displacement from the PC.
378   O << ".+";
379   printAbsBranchOperand(MI, OpNo, O);
380 }
381 
382 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
383                                            raw_ostream &O) {
384   if (!MI->getOperand(OpNo).isImm())
385     return printOperand(MI, OpNo, O);
386 
387   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
388 }
389 
390 
391 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
392                                  raw_ostream &O) {
393   unsigned CCReg = MI->getOperand(OpNo).getReg();
394   unsigned RegNo;
395   switch (CCReg) {
396   default: llvm_unreachable("Unknown CR register");
397   case PPC::CR0: RegNo = 0; break;
398   case PPC::CR1: RegNo = 1; break;
399   case PPC::CR2: RegNo = 2; break;
400   case PPC::CR3: RegNo = 3; break;
401   case PPC::CR4: RegNo = 4; break;
402   case PPC::CR5: RegNo = 5; break;
403   case PPC::CR6: RegNo = 6; break;
404   case PPC::CR7: RegNo = 7; break;
405   }
406   O << (0x80 >> RegNo);
407 }
408 
409 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
410                                     raw_ostream &O) {
411   printS16ImmOperand(MI, OpNo, O);
412   O << '(';
413   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
414     O << "0";
415   else
416     printOperand(MI, OpNo+1, O);
417   O << ')';
418 }
419 
420 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
421                                     raw_ostream &O) {
422   // When used as the base register, r0 reads constant zero rather than
423   // the value contained in the register.  For this reason, the darwin
424   // assembler requires that we print r0 as 0 (no r) when used as the base.
425   if (MI->getOperand(OpNo).getReg() == PPC::R0)
426     O << "0";
427   else
428     printOperand(MI, OpNo, O);
429   O << ", ";
430   printOperand(MI, OpNo+1, O);
431 }
432 
433 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
434                                   raw_ostream &O) {
435   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
436   // come at the _end_ of the expression.
437   const MCOperand &Op = MI->getOperand(OpNo);
438   const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
439   O << refExp.getSymbol().getName();
440   O << '(';
441   printOperand(MI, OpNo+1, O);
442   O << ')';
443   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
444     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
445 }
446 
447 
448 /// stripRegisterPrefix - This method strips the character prefix from a
449 /// register name so that only the number is left.  Used by for linux asm.
450 static const char *stripRegisterPrefix(const char *RegName) {
451   if (FullRegNames || ShowVSRNumsAsVR)
452     return RegName;
453 
454   switch (RegName[0]) {
455   case 'r':
456   case 'f':
457   case 'q': // for QPX
458   case 'v':
459     if (RegName[1] == 's')
460       return RegName + 2;
461     return RegName + 1;
462   case 'c': if (RegName[1] == 'r') return RegName + 2;
463   }
464 
465   return RegName;
466 }
467 
468 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
469                                   raw_ostream &O) {
470   const MCOperand &Op = MI->getOperand(OpNo);
471   if (Op.isReg()) {
472     unsigned Reg = Op.getReg();
473 
474     // There are VSX instructions that use VSX register numbering (vs0 - vs63)
475     // as well as those that use VMX register numbering (v0 - v31 which
476     // correspond to vs32 - vs63). If we have an instruction that uses VSX
477     // numbering, we need to convert the VMX registers to VSX registers.
478     // Namely, we print 32-63 when the instruction operates on one of the
479     // VMX registers.
480     // (Please synchronize with PPCAsmPrinter::printOperand)
481     if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
482         !ShowVSRNumsAsVR) {
483       if (PPCInstrInfo::isVRRegister(Reg))
484         Reg = PPC::VSX32 + (Reg - PPC::V0);
485       else if (PPCInstrInfo::isVFRegister(Reg))
486         Reg = PPC::VSX32 + (Reg - PPC::VF0);
487     }
488 
489     const char *RegName = getRegisterName(Reg);
490     // The linux and AIX assembler does not take register prefixes.
491     if (!isDarwinSyntax())
492       RegName = stripRegisterPrefix(RegName);
493 
494     O << RegName;
495     return;
496   }
497 
498   if (Op.isImm()) {
499     O << Op.getImm();
500     return;
501   }
502 
503   assert(Op.isExpr() && "unknown operand kind in printOperand");
504   Op.getExpr()->print(O, &MAI);
505 }
506 
507