1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetOpcodes.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "asm-printer"
27 
28 // FIXME: Once the integrated assembler supports full register names, tie this
29 // to the verbose-asm setting.
30 static cl::opt<bool>
31 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
32              cl::desc("Use full register names when printing assembly"));
33 
34 #include "PPCGenAsmWriter.inc"
35 
36 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37   OS << getRegisterName(RegNo);
38 }
39 
40 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
41                                StringRef Annot) {
42   // Check for slwi/srwi mnemonics.
43   if (MI->getOpcode() == PPC::RLWINM) {
44     unsigned char SH = MI->getOperand(2).getImm();
45     unsigned char MB = MI->getOperand(3).getImm();
46     unsigned char ME = MI->getOperand(4).getImm();
47     bool useSubstituteMnemonic = false;
48     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
49       O << "\tslwi "; useSubstituteMnemonic = true;
50     }
51     if (SH <= 31 && MB == (32-SH) && ME == 31) {
52       O << "\tsrwi "; useSubstituteMnemonic = true;
53       SH = 32-SH;
54     }
55     if (useSubstituteMnemonic) {
56       printOperand(MI, 0, O);
57       O << ", ";
58       printOperand(MI, 1, O);
59       O << ", " << (unsigned int)SH;
60 
61       printAnnotation(O, Annot);
62       return;
63     }
64   }
65 
66   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
67       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
68     O << "\tmr ";
69     printOperand(MI, 0, O);
70     O << ", ";
71     printOperand(MI, 1, O);
72     printAnnotation(O, Annot);
73     return;
74   }
75 
76   if (MI->getOpcode() == PPC::RLDICR) {
77     unsigned char SH = MI->getOperand(2).getImm();
78     unsigned char ME = MI->getOperand(3).getImm();
79     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
80     if (63-SH == ME) {
81       O << "\tsldi ";
82       printOperand(MI, 0, O);
83       O << ", ";
84       printOperand(MI, 1, O);
85       O << ", " << (unsigned int)SH;
86       printAnnotation(O, Annot);
87       return;
88     }
89   }
90 
91   // For fast-isel, a COPY_TO_REGCLASS may survive this long.  This is
92   // used when converting a 32-bit float to a 64-bit float as part of
93   // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
94   // as otherwise we have problems with incorrect register classes
95   // in machine instruction verification.  For now, just avoid trying
96   // to print it as such an instruction has no effect (a 32-bit float
97   // in a register is already in 64-bit form, just with lower
98   // precision).  FIXME: Is there a better solution?
99   if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
100     return;
101 
102   printInstruction(MI, O);
103   printAnnotation(O, Annot);
104 }
105 
106 
107 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
108                                            raw_ostream &O,
109                                            const char *Modifier) {
110   unsigned Code = MI->getOperand(OpNo).getImm();
111 
112   if (StringRef(Modifier) == "cc") {
113     switch ((PPC::Predicate)Code) {
114     case PPC::PRED_LT_MINUS:
115     case PPC::PRED_LT_PLUS:
116     case PPC::PRED_LT:
117       O << "lt";
118       return;
119     case PPC::PRED_LE_MINUS:
120     case PPC::PRED_LE_PLUS:
121     case PPC::PRED_LE:
122       O << "le";
123       return;
124     case PPC::PRED_EQ_MINUS:
125     case PPC::PRED_EQ_PLUS:
126     case PPC::PRED_EQ:
127       O << "eq";
128       return;
129     case PPC::PRED_GE_MINUS:
130     case PPC::PRED_GE_PLUS:
131     case PPC::PRED_GE:
132       O << "ge";
133       return;
134     case PPC::PRED_GT_MINUS:
135     case PPC::PRED_GT_PLUS:
136     case PPC::PRED_GT:
137       O << "gt";
138       return;
139     case PPC::PRED_NE_MINUS:
140     case PPC::PRED_NE_PLUS:
141     case PPC::PRED_NE:
142       O << "ne";
143       return;
144     case PPC::PRED_UN_MINUS:
145     case PPC::PRED_UN_PLUS:
146     case PPC::PRED_UN:
147       O << "un";
148       return;
149     case PPC::PRED_NU_MINUS:
150     case PPC::PRED_NU_PLUS:
151     case PPC::PRED_NU:
152       O << "nu";
153       return;
154     case PPC::PRED_BIT_SET:
155     case PPC::PRED_BIT_UNSET:
156       llvm_unreachable("Invalid use of bit predicate code");
157     }
158     llvm_unreachable("Invalid predicate code");
159   }
160 
161   if (StringRef(Modifier) == "pm") {
162     switch ((PPC::Predicate)Code) {
163     case PPC::PRED_LT:
164     case PPC::PRED_LE:
165     case PPC::PRED_EQ:
166     case PPC::PRED_GE:
167     case PPC::PRED_GT:
168     case PPC::PRED_NE:
169     case PPC::PRED_UN:
170     case PPC::PRED_NU:
171       return;
172     case PPC::PRED_LT_MINUS:
173     case PPC::PRED_LE_MINUS:
174     case PPC::PRED_EQ_MINUS:
175     case PPC::PRED_GE_MINUS:
176     case PPC::PRED_GT_MINUS:
177     case PPC::PRED_NE_MINUS:
178     case PPC::PRED_UN_MINUS:
179     case PPC::PRED_NU_MINUS:
180       O << "-";
181       return;
182     case PPC::PRED_LT_PLUS:
183     case PPC::PRED_LE_PLUS:
184     case PPC::PRED_EQ_PLUS:
185     case PPC::PRED_GE_PLUS:
186     case PPC::PRED_GT_PLUS:
187     case PPC::PRED_NE_PLUS:
188     case PPC::PRED_UN_PLUS:
189     case PPC::PRED_NU_PLUS:
190       O << "+";
191       return;
192     case PPC::PRED_BIT_SET:
193     case PPC::PRED_BIT_UNSET:
194       llvm_unreachable("Invalid use of bit predicate code");
195     }
196     llvm_unreachable("Invalid predicate code");
197   }
198 
199   assert(StringRef(Modifier) == "reg" &&
200          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
201   printOperand(MI, OpNo+1, O);
202 }
203 
204 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
205                                        raw_ostream &O) {
206   unsigned int Value = MI->getOperand(OpNo).getImm();
207   assert(Value <= 3 && "Invalid u2imm argument!");
208   O << (unsigned int)Value;
209 }
210 
211 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
212                                        raw_ostream &O) {
213   int Value = MI->getOperand(OpNo).getImm();
214   Value = SignExtend32<5>(Value);
215   O << (int)Value;
216 }
217 
218 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
219                                        raw_ostream &O) {
220   unsigned int Value = MI->getOperand(OpNo).getImm();
221   assert(Value <= 31 && "Invalid u5imm argument!");
222   O << (unsigned int)Value;
223 }
224 
225 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
226                                        raw_ostream &O) {
227   unsigned int Value = MI->getOperand(OpNo).getImm();
228   assert(Value <= 63 && "Invalid u6imm argument!");
229   O << (unsigned int)Value;
230 }
231 
232 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
233                                         raw_ostream &O) {
234   if (MI->getOperand(OpNo).isImm())
235     O << (short)MI->getOperand(OpNo).getImm();
236   else
237     printOperand(MI, OpNo, O);
238 }
239 
240 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
241                                         raw_ostream &O) {
242   if (MI->getOperand(OpNo).isImm())
243     O << (unsigned short)MI->getOperand(OpNo).getImm();
244   else
245     printOperand(MI, OpNo, O);
246 }
247 
248 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
249                                         raw_ostream &O) {
250   if (!MI->getOperand(OpNo).isImm())
251     return printOperand(MI, OpNo, O);
252 
253   // Branches can take an immediate operand.  This is used by the branch
254   // selection pass to print .+8, an eight byte displacement from the PC.
255   O << ".+";
256   printAbsBranchOperand(MI, OpNo, O);
257 }
258 
259 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
260                                            raw_ostream &O) {
261   if (!MI->getOperand(OpNo).isImm())
262     return printOperand(MI, OpNo, O);
263 
264   O << (int)MI->getOperand(OpNo).getImm()*4;
265 }
266 
267 
268 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
269                                  raw_ostream &O) {
270   unsigned CCReg = MI->getOperand(OpNo).getReg();
271   unsigned RegNo;
272   switch (CCReg) {
273   default: llvm_unreachable("Unknown CR register");
274   case PPC::CR0: RegNo = 0; break;
275   case PPC::CR1: RegNo = 1; break;
276   case PPC::CR2: RegNo = 2; break;
277   case PPC::CR3: RegNo = 3; break;
278   case PPC::CR4: RegNo = 4; break;
279   case PPC::CR5: RegNo = 5; break;
280   case PPC::CR6: RegNo = 6; break;
281   case PPC::CR7: RegNo = 7; break;
282   }
283   O << (0x80 >> RegNo);
284 }
285 
286 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
287                                     raw_ostream &O) {
288   printS16ImmOperand(MI, OpNo, O);
289   O << '(';
290   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
291     O << "0";
292   else
293     printOperand(MI, OpNo+1, O);
294   O << ')';
295 }
296 
297 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
298                                     raw_ostream &O) {
299   // When used as the base register, r0 reads constant zero rather than
300   // the value contained in the register.  For this reason, the darwin
301   // assembler requires that we print r0 as 0 (no r) when used as the base.
302   if (MI->getOperand(OpNo).getReg() == PPC::R0)
303     O << "0";
304   else
305     printOperand(MI, OpNo, O);
306   O << ", ";
307   printOperand(MI, OpNo+1, O);
308 }
309 
310 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
311                                   raw_ostream &O) {
312   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
313   // come at the _end_ of the expression.
314   const MCOperand &Op = MI->getOperand(OpNo);
315   const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
316   O << refExp.getSymbol().getName();
317   O << '(';
318   printOperand(MI, OpNo+1, O);
319   O << ')';
320   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
321     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
322 }
323 
324 
325 /// stripRegisterPrefix - This method strips the character prefix from a
326 /// register name so that only the number is left.  Used by for linux asm.
327 static const char *stripRegisterPrefix(const char *RegName) {
328   if (FullRegNames)
329     return RegName;
330 
331   switch (RegName[0]) {
332   case 'r':
333   case 'f':
334   case 'v':
335     if (RegName[1] == 's')
336       return RegName + 2;
337     return RegName + 1;
338   case 'c': if (RegName[1] == 'r') return RegName + 2;
339   }
340 
341   return RegName;
342 }
343 
344 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
345                                   raw_ostream &O) {
346   const MCOperand &Op = MI->getOperand(OpNo);
347   if (Op.isReg()) {
348     const char *RegName = getRegisterName(Op.getReg());
349     // The linux and AIX assembler does not take register prefixes.
350     if (!isDarwinSyntax())
351       RegName = stripRegisterPrefix(RegName);
352 
353     O << RegName;
354     return;
355   }
356 
357   if (Op.isImm()) {
358     O << Op.getImm();
359     return;
360   }
361 
362   assert(Op.isExpr() && "unknown operand kind in printOperand");
363   O << *Op.getExpr();
364 }
365 
366