1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "asm-printer"
15 #include "PPCInstPrinter.h"
16 #include "MCTargetDesc/PPCMCTargetDesc.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetOpcodes.h"
25 using namespace llvm;
26 
27 // FIXME: Once the integrated assembler supports full register names, tie this
28 // to the verbose-asm setting.
29 static cl::opt<bool>
30 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
31              cl::desc("Use full register names when printing assembly"));
32 
33 #include "PPCGenAsmWriter.inc"
34 
35 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
36   OS << getRegisterName(RegNo);
37 }
38 
39 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
40                                StringRef Annot) {
41   // Check for slwi/srwi mnemonics.
42   if (MI->getOpcode() == PPC::RLWINM) {
43     unsigned char SH = MI->getOperand(2).getImm();
44     unsigned char MB = MI->getOperand(3).getImm();
45     unsigned char ME = MI->getOperand(4).getImm();
46     bool useSubstituteMnemonic = false;
47     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
48       O << "\tslwi "; useSubstituteMnemonic = true;
49     }
50     if (SH <= 31 && MB == (32-SH) && ME == 31) {
51       O << "\tsrwi "; useSubstituteMnemonic = true;
52       SH = 32-SH;
53     }
54     if (useSubstituteMnemonic) {
55       printOperand(MI, 0, O);
56       O << ", ";
57       printOperand(MI, 1, O);
58       O << ", " << (unsigned int)SH;
59 
60       printAnnotation(O, Annot);
61       return;
62     }
63   }
64 
65   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
66       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67     O << "\tmr ";
68     printOperand(MI, 0, O);
69     O << ", ";
70     printOperand(MI, 1, O);
71     printAnnotation(O, Annot);
72     return;
73   }
74 
75   if (MI->getOpcode() == PPC::RLDICR) {
76     unsigned char SH = MI->getOperand(2).getImm();
77     unsigned char ME = MI->getOperand(3).getImm();
78     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
79     if (63-SH == ME) {
80       O << "\tsldi ";
81       printOperand(MI, 0, O);
82       O << ", ";
83       printOperand(MI, 1, O);
84       O << ", " << (unsigned int)SH;
85       printAnnotation(O, Annot);
86       return;
87     }
88   }
89 
90   // For fast-isel, a COPY_TO_REGCLASS may survive this long.  This is
91   // used when converting a 32-bit float to a 64-bit float as part of
92   // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
93   // as otherwise we have problems with incorrect register classes
94   // in machine instruction verification.  For now, just avoid trying
95   // to print it as such an instruction has no effect (a 32-bit float
96   // in a register is already in 64-bit form, just with lower
97   // precision).  FIXME: Is there a better solution?
98   if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
99     return;
100 
101   printInstruction(MI, O);
102   printAnnotation(O, Annot);
103 }
104 
105 
106 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
107                                            raw_ostream &O,
108                                            const char *Modifier) {
109   unsigned Code = MI->getOperand(OpNo).getImm();
110 
111   if (StringRef(Modifier) == "cc") {
112     switch ((PPC::Predicate)Code) {
113     case PPC::PRED_LT_MINUS:
114     case PPC::PRED_LT_PLUS:
115     case PPC::PRED_LT:
116       O << "lt";
117       return;
118     case PPC::PRED_LE_MINUS:
119     case PPC::PRED_LE_PLUS:
120     case PPC::PRED_LE:
121       O << "le";
122       return;
123     case PPC::PRED_EQ_MINUS:
124     case PPC::PRED_EQ_PLUS:
125     case PPC::PRED_EQ:
126       O << "eq";
127       return;
128     case PPC::PRED_GE_MINUS:
129     case PPC::PRED_GE_PLUS:
130     case PPC::PRED_GE:
131       O << "ge";
132       return;
133     case PPC::PRED_GT_MINUS:
134     case PPC::PRED_GT_PLUS:
135     case PPC::PRED_GT:
136       O << "gt";
137       return;
138     case PPC::PRED_NE_MINUS:
139     case PPC::PRED_NE_PLUS:
140     case PPC::PRED_NE:
141       O << "ne";
142       return;
143     case PPC::PRED_UN_MINUS:
144     case PPC::PRED_UN_PLUS:
145     case PPC::PRED_UN:
146       O << "un";
147       return;
148     case PPC::PRED_NU_MINUS:
149     case PPC::PRED_NU_PLUS:
150     case PPC::PRED_NU:
151       O << "nu";
152       return;
153     }
154     llvm_unreachable("Invalid predicate code");
155   }
156 
157   if (StringRef(Modifier) == "pm") {
158     switch ((PPC::Predicate)Code) {
159     case PPC::PRED_LT:
160     case PPC::PRED_LE:
161     case PPC::PRED_EQ:
162     case PPC::PRED_GE:
163     case PPC::PRED_GT:
164     case PPC::PRED_NE:
165     case PPC::PRED_UN:
166     case PPC::PRED_NU:
167       return;
168     case PPC::PRED_LT_MINUS:
169     case PPC::PRED_LE_MINUS:
170     case PPC::PRED_EQ_MINUS:
171     case PPC::PRED_GE_MINUS:
172     case PPC::PRED_GT_MINUS:
173     case PPC::PRED_NE_MINUS:
174     case PPC::PRED_UN_MINUS:
175     case PPC::PRED_NU_MINUS:
176       O << "-";
177       return;
178     case PPC::PRED_LT_PLUS:
179     case PPC::PRED_LE_PLUS:
180     case PPC::PRED_EQ_PLUS:
181     case PPC::PRED_GE_PLUS:
182     case PPC::PRED_GT_PLUS:
183     case PPC::PRED_NE_PLUS:
184     case PPC::PRED_UN_PLUS:
185     case PPC::PRED_NU_PLUS:
186       O << "+";
187       return;
188     }
189     llvm_unreachable("Invalid predicate code");
190   }
191 
192   assert(StringRef(Modifier) == "reg" &&
193          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
194   printOperand(MI, OpNo+1, O);
195 }
196 
197 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
198                                        raw_ostream &O) {
199   int Value = MI->getOperand(OpNo).getImm();
200   Value = SignExtend32<5>(Value);
201   O << (int)Value;
202 }
203 
204 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
205                                        raw_ostream &O) {
206   unsigned int Value = MI->getOperand(OpNo).getImm();
207   assert(Value <= 31 && "Invalid u5imm argument!");
208   O << (unsigned int)Value;
209 }
210 
211 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
212                                        raw_ostream &O) {
213   unsigned int Value = MI->getOperand(OpNo).getImm();
214   assert(Value <= 63 && "Invalid u6imm argument!");
215   O << (unsigned int)Value;
216 }
217 
218 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
219                                         raw_ostream &O) {
220   if (MI->getOperand(OpNo).isImm())
221     O << (short)MI->getOperand(OpNo).getImm();
222   else
223     printOperand(MI, OpNo, O);
224 }
225 
226 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
227                                         raw_ostream &O) {
228   if (MI->getOperand(OpNo).isImm())
229     O << (unsigned short)MI->getOperand(OpNo).getImm();
230   else
231     printOperand(MI, OpNo, O);
232 }
233 
234 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
235                                         raw_ostream &O) {
236   if (!MI->getOperand(OpNo).isImm())
237     return printOperand(MI, OpNo, O);
238 
239   // Branches can take an immediate operand.  This is used by the branch
240   // selection pass to print .+8, an eight byte displacement from the PC.
241   O << ".+";
242   printAbsBranchOperand(MI, OpNo, O);
243 }
244 
245 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
246                                            raw_ostream &O) {
247   if (!MI->getOperand(OpNo).isImm())
248     return printOperand(MI, OpNo, O);
249 
250   O << (int)MI->getOperand(OpNo).getImm()*4;
251 }
252 
253 
254 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
255                                  raw_ostream &O) {
256   unsigned CCReg = MI->getOperand(OpNo).getReg();
257   unsigned RegNo;
258   switch (CCReg) {
259   default: llvm_unreachable("Unknown CR register");
260   case PPC::CR0: RegNo = 0; break;
261   case PPC::CR1: RegNo = 1; break;
262   case PPC::CR2: RegNo = 2; break;
263   case PPC::CR3: RegNo = 3; break;
264   case PPC::CR4: RegNo = 4; break;
265   case PPC::CR5: RegNo = 5; break;
266   case PPC::CR6: RegNo = 6; break;
267   case PPC::CR7: RegNo = 7; break;
268   }
269   O << (0x80 >> RegNo);
270 }
271 
272 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
273                                     raw_ostream &O) {
274   printS16ImmOperand(MI, OpNo, O);
275   O << '(';
276   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
277     O << "0";
278   else
279     printOperand(MI, OpNo+1, O);
280   O << ')';
281 }
282 
283 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
284                                     raw_ostream &O) {
285   // When used as the base register, r0 reads constant zero rather than
286   // the value contained in the register.  For this reason, the darwin
287   // assembler requires that we print r0 as 0 (no r) when used as the base.
288   if (MI->getOperand(OpNo).getReg() == PPC::R0)
289     O << "0";
290   else
291     printOperand(MI, OpNo, O);
292   O << ", ";
293   printOperand(MI, OpNo+1, O);
294 }
295 
296 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
297                                   raw_ostream &O) {
298   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
299   // come at the _end_ of the expression.
300   const MCOperand &Op = MI->getOperand(OpNo);
301   const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
302   O << refExp.getSymbol().getName();
303   O << '(';
304   printOperand(MI, OpNo+1, O);
305   O << ')';
306   if (refExp.getKind() != MCSymbolRefExpr::VK_None)
307     O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
308 }
309 
310 
311 /// stripRegisterPrefix - This method strips the character prefix from a
312 /// register name so that only the number is left.  Used by for linux asm.
313 static const char *stripRegisterPrefix(const char *RegName) {
314   if (FullRegNames)
315     return RegName;
316 
317   switch (RegName[0]) {
318   case 'r':
319   case 'f':
320   case 'v': return RegName + 1;
321   case 'c': if (RegName[1] == 'r') return RegName + 2;
322   }
323 
324   return RegName;
325 }
326 
327 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
328                                   raw_ostream &O) {
329   const MCOperand &Op = MI->getOperand(OpNo);
330   if (Op.isReg()) {
331     const char *RegName = getRegisterName(Op.getReg());
332     // The linux and AIX assembler does not take register prefixes.
333     if (!isDarwinSyntax())
334       RegName = stripRegisterPrefix(RegName);
335 
336     O << RegName;
337     return;
338   }
339 
340   if (Op.isImm()) {
341     O << Op.getImm();
342     return;
343   }
344 
345   assert(Op.isExpr() && "unknown operand kind in printOperand");
346   O << *Op.getExpr();
347 }
348 
349