1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
3 
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "MipsCCState.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/CodeGen/FastISel.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/IR/GlobalAlias.h"
14 #include "llvm/IR/GlobalVariable.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetLibraryInfo.h"
17 
18 using namespace llvm;
19 
20 namespace {
21 
22 class MipsFastISel final : public FastISel {
23 
24   // All possible address modes.
25   class Address {
26   public:
27     typedef enum { RegBase, FrameIndexBase } BaseKind;
28 
29   private:
30     BaseKind Kind;
31     union {
32       unsigned Reg;
33       int FI;
34     } Base;
35 
36     int64_t Offset;
37 
38     const GlobalValue *GV;
39 
40   public:
41     // Innocuous defaults for our address.
42     Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
43     void setKind(BaseKind K) { Kind = K; }
44     BaseKind getKind() const { return Kind; }
45     bool isRegBase() const { return Kind == RegBase; }
46     void setReg(unsigned Reg) {
47       assert(isRegBase() && "Invalid base register access!");
48       Base.Reg = Reg;
49     }
50     unsigned getReg() const {
51       assert(isRegBase() && "Invalid base register access!");
52       return Base.Reg;
53     }
54     void setOffset(int64_t Offset_) { Offset = Offset_; }
55     int64_t getOffset() const { return Offset; }
56     void setGlobalValue(const GlobalValue *G) { GV = G; }
57     const GlobalValue *getGlobalValue() { return GV; }
58   };
59 
60   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
61   /// make the right decision when generating code for different targets.
62   const TargetMachine &TM;
63   const TargetInstrInfo &TII;
64   const TargetLowering &TLI;
65   const MipsSubtarget *Subtarget;
66   MipsFunctionInfo *MFI;
67 
68   // Convenience variables to avoid some queries.
69   LLVMContext *Context;
70 
71   bool fastLowerCall(CallLoweringInfo &CLI) override;
72 
73   bool TargetSupported;
74   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
75   // floating point but not reject doing fast-isel in other
76   // situations
77 
78 private:
79   // Selection routines.
80   bool selectLoad(const Instruction *I);
81   bool selectStore(const Instruction *I);
82   bool selectBranch(const Instruction *I);
83   bool selectCmp(const Instruction *I);
84   bool selectFPExt(const Instruction *I);
85   bool selectFPTrunc(const Instruction *I);
86   bool selectFPToInt(const Instruction *I, bool IsSigned);
87   bool selectRet(const Instruction *I);
88   bool selectTrunc(const Instruction *I);
89   bool selectIntExt(const Instruction *I);
90 
91   // Utility helper routines.
92   bool isTypeLegal(Type *Ty, MVT &VT);
93   bool isLoadTypeLegal(Type *Ty, MVT &VT);
94   bool computeAddress(const Value *Obj, Address &Addr);
95   bool computeCallAddress(const Value *V, Address &Addr);
96 
97   // Emit helper routines.
98   bool emitCmp(unsigned DestReg, const CmpInst *CI);
99   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
100                 unsigned Alignment = 0);
101   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
102                  MachineMemOperand *MMO = nullptr);
103   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
104                  unsigned Alignment = 0);
105   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
106   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
107 
108                   bool IsZExt);
109   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
110 
111   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
112   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
113                        unsigned DestReg);
114   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
115                        unsigned DestReg);
116 
117   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
118 
119   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
120   unsigned materializeGV(const GlobalValue *GV, MVT VT);
121   unsigned materializeInt(const Constant *C, MVT VT);
122   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
123 
124   MachineInstrBuilder emitInst(unsigned Opc) {
125     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
126   }
127   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
128     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
129                    DstReg);
130   }
131   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
132                                     unsigned MemReg, int64_t MemOffset) {
133     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
134   }
135   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
136                                    unsigned MemReg, int64_t MemOffset) {
137     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
138   }
139   // for some reason, this default is not generated by tablegen
140   // so we explicitly generate it here.
141   //
142   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
143                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
144                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
145     return 0;
146   }
147 
148   // Call handling routines.
149 private:
150   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
151   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
152                        unsigned &NumBytes);
153   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
154 
155 public:
156   // Backend specific FastISel code.
157   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
158                         const TargetLibraryInfo *libInfo)
159       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
160         TII(*TM.getSubtargetImpl()->getInstrInfo()),
161         TLI(*TM.getSubtargetImpl()->getTargetLowering()),
162         Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
163     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
164     Context = &funcInfo.Fn->getContext();
165     TargetSupported = ((TM.getRelocationModel() == Reloc::PIC_) &&
166                        ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
167                         (Subtarget->isABI_O32())));
168     UnsupportedFPMode = Subtarget->isFP64bit();
169   }
170 
171   unsigned fastMaterializeConstant(const Constant *C) override;
172   bool fastSelectInstruction(const Instruction *I) override;
173 
174 #include "MipsGenFastISel.inc"
175 };
176 } // end anonymous namespace.
177 
178 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
179                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
180                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
181 
182 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
183                             CCValAssign::LocInfo LocInfo,
184                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
185   llvm_unreachable("should not be called");
186 }
187 
188 bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
189                      CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
190                      CCState &State) {
191   llvm_unreachable("should not be called");
192 }
193 
194 #include "MipsGenCallingConv.inc"
195 
196 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
197   return CC_MipsO32;
198 }
199 
200 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
201   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
202     return 0;
203   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
204   const ConstantInt *CI = cast<ConstantInt>(C);
205   int64_t Imm;
206   if ((VT != MVT::i1) && CI->isNegative())
207     Imm = CI->getSExtValue();
208   else
209     Imm = CI->getZExtValue();
210   return materialize32BitInt(Imm, RC);
211 }
212 
213 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
214                                            const TargetRegisterClass *RC) {
215   unsigned ResultReg = createResultReg(RC);
216 
217   if (isInt<16>(Imm)) {
218     unsigned Opc = Mips::ADDiu;
219     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
220     return ResultReg;
221   } else if (isUInt<16>(Imm)) {
222     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
223     return ResultReg;
224   }
225   unsigned Lo = Imm & 0xFFFF;
226   unsigned Hi = (Imm >> 16) & 0xFFFF;
227   if (Lo) {
228     // Both Lo and Hi have nonzero bits.
229     unsigned TmpReg = createResultReg(RC);
230     emitInst(Mips::LUi, TmpReg).addImm(Hi);
231     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
232   } else {
233     emitInst(Mips::LUi, ResultReg).addImm(Hi);
234   }
235   return ResultReg;
236 }
237 
238 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
239   if (UnsupportedFPMode)
240     return 0;
241   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
242   if (VT == MVT::f32) {
243     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
244     unsigned DestReg = createResultReg(RC);
245     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
246     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
247     return DestReg;
248   } else if (VT == MVT::f64) {
249     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
250     unsigned DestReg = createResultReg(RC);
251     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
252     unsigned TempReg2 =
253         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
254     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
255     return DestReg;
256   }
257   return 0;
258 }
259 
260 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
261   // For now 32-bit only.
262   if (VT != MVT::i32)
263     return 0;
264   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
265   unsigned DestReg = createResultReg(RC);
266   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
267   bool IsThreadLocal = GVar && GVar->isThreadLocal();
268   // TLS not supported at this time.
269   if (IsThreadLocal)
270     return 0;
271   emitInst(Mips::LW, DestReg)
272       .addReg(MFI->getGlobalBaseReg())
273       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
274   if ((GV->hasInternalLinkage() ||
275        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
276     unsigned TempReg = createResultReg(RC);
277     emitInst(Mips::ADDiu, TempReg)
278         .addReg(DestReg)
279         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
280     DestReg = TempReg;
281   }
282   return DestReg;
283 }
284 
285 // Materialize a constant into a register, and return the register
286 // number (or zero if we failed to handle it).
287 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
288   EVT CEVT = TLI.getValueType(C->getType(), true);
289 
290   // Only handle simple types.
291   if (!CEVT.isSimple())
292     return 0;
293   MVT VT = CEVT.getSimpleVT();
294 
295   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
296     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
297   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
298     return materializeGV(GV, VT);
299   else if (isa<ConstantInt>(C))
300     return materializeInt(C, VT);
301 
302   return 0;
303 }
304 
305 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
306   // This construct looks a big awkward but it is how other ports handle this
307   // and as this function is more fully completed, these cases which
308   // return false will have additional code in them.
309   //
310   if (isa<Instruction>(Obj))
311     return false;
312   else if (isa<ConstantExpr>(Obj))
313     return false;
314   Addr.setReg(getRegForValue(Obj));
315   return Addr.getReg() != 0;
316 }
317 
318 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
319   const GlobalValue *GV = dyn_cast<GlobalValue>(V);
320   if (GV && isa<Function>(GV) && dyn_cast<Function>(GV)->isIntrinsic())
321     return false;
322   if (!GV)
323     return false;
324   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
325     Addr.setGlobalValue(GV);
326     return true;
327   }
328   return false;
329 }
330 
331 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
332   EVT evt = TLI.getValueType(Ty, true);
333   // Only handle simple types.
334   if (evt == MVT::Other || !evt.isSimple())
335     return false;
336   VT = evt.getSimpleVT();
337 
338   // Handle all legal types, i.e. a register that will directly hold this
339   // value.
340   return TLI.isTypeLegal(VT);
341 }
342 
343 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
344   if (isTypeLegal(Ty, VT))
345     return true;
346   // We will extend this in a later patch:
347   //   If this is a type than can be sign or zero-extended to a basic operation
348   //   go ahead and accept it now.
349   if (VT == MVT::i8 || VT == MVT::i16)
350     return true;
351   return false;
352 }
353 // Because of how EmitCmp is called with fast-isel, you can
354 // end up with redundant "andi" instructions after the sequences emitted below.
355 // We should try and solve this issue in the future.
356 //
357 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
358   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
359   bool IsUnsigned = CI->isUnsigned();
360   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
361   if (LeftReg == 0)
362     return false;
363   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
364   if (RightReg == 0)
365     return false;
366   CmpInst::Predicate P = CI->getPredicate();
367 
368   switch (P) {
369   default:
370     return false;
371   case CmpInst::ICMP_EQ: {
372     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
373     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
374     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
375     break;
376   }
377   case CmpInst::ICMP_NE: {
378     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
379     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
380     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
381     break;
382   }
383   case CmpInst::ICMP_UGT: {
384     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
385     break;
386   }
387   case CmpInst::ICMP_ULT: {
388     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
389     break;
390   }
391   case CmpInst::ICMP_UGE: {
392     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
393     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
394     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
395     break;
396   }
397   case CmpInst::ICMP_ULE: {
398     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
399     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
400     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
401     break;
402   }
403   case CmpInst::ICMP_SGT: {
404     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
405     break;
406   }
407   case CmpInst::ICMP_SLT: {
408     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
409     break;
410   }
411   case CmpInst::ICMP_SGE: {
412     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
413     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
414     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
415     break;
416   }
417   case CmpInst::ICMP_SLE: {
418     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
419     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
420     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
421     break;
422   }
423   case CmpInst::FCMP_OEQ:
424   case CmpInst::FCMP_UNE:
425   case CmpInst::FCMP_OLT:
426   case CmpInst::FCMP_OLE:
427   case CmpInst::FCMP_OGT:
428   case CmpInst::FCMP_OGE: {
429     if (UnsupportedFPMode)
430       return false;
431     bool IsFloat = Left->getType()->isFloatTy();
432     bool IsDouble = Left->getType()->isDoubleTy();
433     if (!IsFloat && !IsDouble)
434       return false;
435     unsigned Opc, CondMovOpc;
436     switch (P) {
437     case CmpInst::FCMP_OEQ:
438       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
439       CondMovOpc = Mips::MOVT_I;
440       break;
441     case CmpInst::FCMP_UNE:
442       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
443       CondMovOpc = Mips::MOVF_I;
444       break;
445     case CmpInst::FCMP_OLT:
446       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
447       CondMovOpc = Mips::MOVT_I;
448       break;
449     case CmpInst::FCMP_OLE:
450       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
451       CondMovOpc = Mips::MOVT_I;
452       break;
453     case CmpInst::FCMP_OGT:
454       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
455       CondMovOpc = Mips::MOVF_I;
456       break;
457     case CmpInst::FCMP_OGE:
458       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
459       CondMovOpc = Mips::MOVF_I;
460       break;
461     default:
462       llvm_unreachable("Only switching of a subset of CCs.");
463     }
464     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
465     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
466     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
467     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
468     emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
469         Mips::FCC0, RegState::ImplicitDefine);
470     MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
471                                  .addReg(RegWithOne)
472                                  .addReg(Mips::FCC0)
473                                  .addReg(RegWithZero, RegState::Implicit);
474     MI->tieOperands(0, 3);
475     break;
476   }
477   }
478   return true;
479 }
480 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
481                             unsigned Alignment) {
482   //
483   // more cases will be handled here in following patches.
484   //
485   unsigned Opc;
486   switch (VT.SimpleTy) {
487   case MVT::i32: {
488     ResultReg = createResultReg(&Mips::GPR32RegClass);
489     Opc = Mips::LW;
490     break;
491   }
492   case MVT::i16: {
493     ResultReg = createResultReg(&Mips::GPR32RegClass);
494     Opc = Mips::LHu;
495     break;
496   }
497   case MVT::i8: {
498     ResultReg = createResultReg(&Mips::GPR32RegClass);
499     Opc = Mips::LBu;
500     break;
501   }
502   case MVT::f32: {
503     if (UnsupportedFPMode)
504       return false;
505     ResultReg = createResultReg(&Mips::FGR32RegClass);
506     Opc = Mips::LWC1;
507     break;
508   }
509   case MVT::f64: {
510     if (UnsupportedFPMode)
511       return false;
512     ResultReg = createResultReg(&Mips::AFGR64RegClass);
513     Opc = Mips::LDC1;
514     break;
515   }
516   default:
517     return false;
518   }
519   emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
520   return true;
521 }
522 
523 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
524                              unsigned Alignment) {
525   //
526   // more cases will be handled here in following patches.
527   //
528   unsigned Opc;
529   switch (VT.SimpleTy) {
530   case MVT::i8:
531     Opc = Mips::SB;
532     break;
533   case MVT::i16:
534     Opc = Mips::SH;
535     break;
536   case MVT::i32:
537     Opc = Mips::SW;
538     break;
539   case MVT::f32:
540     if (UnsupportedFPMode)
541       return false;
542     Opc = Mips::SWC1;
543     break;
544   case MVT::f64:
545     if (UnsupportedFPMode)
546       return false;
547     Opc = Mips::SDC1;
548     break;
549   default:
550     return false;
551   }
552   emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
553   return true;
554 }
555 
556 bool MipsFastISel::selectLoad(const Instruction *I) {
557   // Atomic loads need special handling.
558   if (cast<LoadInst>(I)->isAtomic())
559     return false;
560 
561   // Verify we have a legal type before going any further.
562   MVT VT;
563   if (!isLoadTypeLegal(I->getType(), VT))
564     return false;
565 
566   // See if we can handle this address.
567   Address Addr;
568   if (!computeAddress(I->getOperand(0), Addr))
569     return false;
570 
571   unsigned ResultReg;
572   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
573     return false;
574   updateValueMap(I, ResultReg);
575   return true;
576 }
577 
578 bool MipsFastISel::selectStore(const Instruction *I) {
579   Value *Op0 = I->getOperand(0);
580   unsigned SrcReg = 0;
581 
582   // Atomic stores need special handling.
583   if (cast<StoreInst>(I)->isAtomic())
584     return false;
585 
586   // Verify we have a legal type before going any further.
587   MVT VT;
588   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
589     return false;
590 
591   // Get the value to be stored into a register.
592   SrcReg = getRegForValue(Op0);
593   if (SrcReg == 0)
594     return false;
595 
596   // See if we can handle this address.
597   Address Addr;
598   if (!computeAddress(I->getOperand(1), Addr))
599     return false;
600 
601   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
602     return false;
603   return true;
604 }
605 
606 //
607 // This can cause a redundant sltiu to be generated.
608 // FIXME: try and eliminate this in a future patch.
609 //
610 bool MipsFastISel::selectBranch(const Instruction *I) {
611   const BranchInst *BI = cast<BranchInst>(I);
612   MachineBasicBlock *BrBB = FuncInfo.MBB;
613   //
614   // TBB is the basic block for the case where the comparison is true.
615   // FBB is the basic block for the case where the comparison is false.
616   // if (cond) goto TBB
617   // goto FBB
618   // TBB:
619   //
620   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
621   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
622   BI->getCondition();
623   // For now, just try the simplest case where it's fed by a compare.
624   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
625     unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
626     if (!emitCmp(CondReg, CI))
627       return false;
628     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
629         .addReg(CondReg)
630         .addMBB(TBB);
631     fastEmitBranch(FBB, DbgLoc);
632     FuncInfo.MBB->addSuccessor(TBB);
633     return true;
634   }
635   return false;
636 }
637 
638 bool MipsFastISel::selectCmp(const Instruction *I) {
639   const CmpInst *CI = cast<CmpInst>(I);
640   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
641   if (!emitCmp(ResultReg, CI))
642     return false;
643   updateValueMap(I, ResultReg);
644   return true;
645 }
646 
647 // Attempt to fast-select a floating-point extend instruction.
648 bool MipsFastISel::selectFPExt(const Instruction *I) {
649   if (UnsupportedFPMode)
650     return false;
651   Value *Src = I->getOperand(0);
652   EVT SrcVT = TLI.getValueType(Src->getType(), true);
653   EVT DestVT = TLI.getValueType(I->getType(), true);
654 
655   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
656     return false;
657 
658   unsigned SrcReg =
659       getRegForValue(Src); // his must be a 32 bit floating point register class
660                            // maybe we should handle this differently
661   if (!SrcReg)
662     return false;
663 
664   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
665   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
666   updateValueMap(I, DestReg);
667   return true;
668 }
669 
670 // Attempt to fast-select a floating-point truncate instruction.
671 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
672   if (UnsupportedFPMode)
673     return false;
674   Value *Src = I->getOperand(0);
675   EVT SrcVT = TLI.getValueType(Src->getType(), true);
676   EVT DestVT = TLI.getValueType(I->getType(), true);
677 
678   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
679     return false;
680 
681   unsigned SrcReg = getRegForValue(Src);
682   if (!SrcReg)
683     return false;
684 
685   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
686   if (!DestReg)
687     return false;
688 
689   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
690   updateValueMap(I, DestReg);
691   return true;
692 }
693 
694 // Attempt to fast-select a floating-point-to-integer conversion.
695 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
696   if (UnsupportedFPMode)
697     return false;
698   MVT DstVT, SrcVT;
699   if (!IsSigned)
700     return false; // We don't handle this case yet. There is no native
701                   // instruction for this but it can be synthesized.
702   Type *DstTy = I->getType();
703   if (!isTypeLegal(DstTy, DstVT))
704     return false;
705 
706   if (DstVT != MVT::i32)
707     return false;
708 
709   Value *Src = I->getOperand(0);
710   Type *SrcTy = Src->getType();
711   if (!isTypeLegal(SrcTy, SrcVT))
712     return false;
713 
714   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
715     return false;
716 
717   unsigned SrcReg = getRegForValue(Src);
718   if (SrcReg == 0)
719     return false;
720 
721   // Determine the opcode for the conversion, which takes place
722   // entirely within FPRs.
723   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
724   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
725   unsigned Opc;
726 
727   if (SrcVT == MVT::f32)
728     Opc = Mips::TRUNC_W_S;
729   else
730     Opc = Mips::TRUNC_W_D32;
731 
732   // Generate the convert.
733   emitInst(Opc, TempReg).addReg(SrcReg);
734 
735   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
736 
737   updateValueMap(I, DestReg);
738   return true;
739 }
740 //
741 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
742                                    SmallVectorImpl<MVT> &OutVTs,
743                                    unsigned &NumBytes) {
744   CallingConv::ID CC = CLI.CallConv;
745   SmallVector<CCValAssign, 16> ArgLocs;
746   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
747   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
748   // Get a count of how many bytes are to be pushed on the stack.
749   NumBytes = CCInfo.getNextStackOffset();
750   // This is the minimum argument area used for A0-A3.
751   if (NumBytes < 16)
752     NumBytes = 16;
753 
754   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
755   // Process the args.
756   MVT firstMVT;
757   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
758     CCValAssign &VA = ArgLocs[i];
759     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
760     MVT ArgVT = OutVTs[VA.getValNo()];
761 
762     if (i == 0) {
763       firstMVT = ArgVT;
764       if (ArgVT == MVT::f32) {
765         VA.convertToReg(Mips::F12);
766       } else if (ArgVT == MVT::f64) {
767         VA.convertToReg(Mips::D6);
768       }
769     } else if (i == 1) {
770       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
771         if (ArgVT == MVT::f32) {
772           VA.convertToReg(Mips::F14);
773         } else if (ArgVT == MVT::f64) {
774           VA.convertToReg(Mips::D7);
775         }
776       }
777     }
778     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
779       switch (VA.getLocMemOffset()) {
780       case 0:
781         VA.convertToReg(Mips::A0);
782         break;
783       case 4:
784         VA.convertToReg(Mips::A1);
785         break;
786       case 8:
787         VA.convertToReg(Mips::A2);
788         break;
789       case 12:
790         VA.convertToReg(Mips::A3);
791         break;
792       default:
793         break;
794       }
795     }
796     unsigned ArgReg = getRegForValue(ArgVal);
797     if (!ArgReg)
798       return false;
799 
800     // Handle arg promotion: SExt, ZExt, AExt.
801     switch (VA.getLocInfo()) {
802     case CCValAssign::Full:
803       break;
804     case CCValAssign::AExt:
805     case CCValAssign::SExt: {
806       MVT DestVT = VA.getLocVT();
807       MVT SrcVT = ArgVT;
808       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
809       if (!ArgReg)
810         return false;
811       break;
812     }
813     case CCValAssign::ZExt: {
814       MVT DestVT = VA.getLocVT();
815       MVT SrcVT = ArgVT;
816       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
817       if (!ArgReg)
818         return false;
819       break;
820     }
821     default:
822       llvm_unreachable("Unknown arg promotion!");
823     }
824 
825     // Now copy/store arg to correct locations.
826     if (VA.isRegLoc() && !VA.needsCustom()) {
827       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
828               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
829       CLI.OutRegs.push_back(VA.getLocReg());
830     } else if (VA.needsCustom()) {
831       llvm_unreachable("Mips does not use custom args.");
832       return false;
833     } else {
834       //
835       // FIXME: This path will currently return false. It was copied
836       // from the AArch64 port and should be essentially fine for Mips too.
837       // The work to finish up this path will be done in a follow-on patch.
838       //
839       assert(VA.isMemLoc() && "Assuming store on stack.");
840       // Don't emit stores for undef values.
841       if (isa<UndefValue>(ArgVal))
842         continue;
843 
844       // Need to store on the stack.
845       // FIXME: This alignment is incorrect but this path is disabled
846       // for now (will return false). We need to determine the right alignment
847       // based on the normal alignment for the underlying machine type.
848       //
849       unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
850 
851       unsigned BEAlign = 0;
852       if (ArgSize < 8 && !Subtarget->isLittle())
853         BEAlign = 8 - ArgSize;
854 
855       Address Addr;
856       Addr.setKind(Address::RegBase);
857       Addr.setReg(Mips::SP);
858       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
859 
860       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
861       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
862           MachinePointerInfo::getStack(Addr.getOffset()),
863           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
864       (void)(MMO);
865       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
866       return false; // can't store on the stack yet.
867     }
868   }
869 
870   return true;
871 }
872 
873 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
874                               unsigned NumBytes) {
875   CallingConv::ID CC = CLI.CallConv;
876   emitInst(Mips::ADJCALLSTACKUP).addImm(16);
877   if (RetVT != MVT::isVoid) {
878     SmallVector<CCValAssign, 16> RVLocs;
879     CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
880     CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
881 
882     // Only handle a single return value.
883     if (RVLocs.size() != 1)
884       return false;
885     // Copy all of the result registers out of their specified physreg.
886     MVT CopyVT = RVLocs[0].getValVT();
887     // Special handling for extended integers.
888     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
889       CopyVT = MVT::i32;
890 
891     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
892     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
893             TII.get(TargetOpcode::COPY),
894             ResultReg).addReg(RVLocs[0].getLocReg());
895     CLI.InRegs.push_back(RVLocs[0].getLocReg());
896 
897     CLI.ResultReg = ResultReg;
898     CLI.NumResultRegs = 1;
899   }
900   return true;
901 }
902 
903 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
904   CallingConv::ID CC = CLI.CallConv;
905   bool IsTailCall = CLI.IsTailCall;
906   bool IsVarArg = CLI.IsVarArg;
907   const Value *Callee = CLI.Callee;
908   // const char *SymName = CLI.SymName;
909 
910   // Allow SelectionDAG isel to handle tail calls.
911   if (IsTailCall)
912     return false;
913 
914   // Let SDISel handle vararg functions.
915   if (IsVarArg)
916     return false;
917 
918   // FIXME: Only handle *simple* calls for now.
919   MVT RetVT;
920   if (CLI.RetTy->isVoidTy())
921     RetVT = MVT::isVoid;
922   else if (!isTypeLegal(CLI.RetTy, RetVT))
923     return false;
924 
925   for (auto Flag : CLI.OutFlags)
926     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
927       return false;
928 
929   // Set up the argument vectors.
930   SmallVector<MVT, 16> OutVTs;
931   OutVTs.reserve(CLI.OutVals.size());
932 
933   for (auto *Val : CLI.OutVals) {
934     MVT VT;
935     if (!isTypeLegal(Val->getType(), VT) &&
936         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
937       return false;
938 
939     // We don't handle vector parameters yet.
940     if (VT.isVector() || VT.getSizeInBits() > 64)
941       return false;
942 
943     OutVTs.push_back(VT);
944   }
945 
946   Address Addr;
947   if (!computeCallAddress(Callee, Addr))
948     return false;
949 
950   // Handle the arguments now that we've gotten them.
951   unsigned NumBytes;
952   if (!processCallArgs(CLI, OutVTs, NumBytes))
953     return false;
954 
955   // Issue the call.
956   unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
957   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
958   MachineInstrBuilder MIB =
959       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
960               Mips::RA).addReg(Mips::T9);
961 
962   // Add implicit physical register uses to the call.
963   for (auto Reg : CLI.OutRegs)
964     MIB.addReg(Reg, RegState::Implicit);
965 
966   // Add a register mask with the call-preserved registers.
967   // Proper defs for return values will be added by setPhysRegsDeadExcept().
968   MIB.addRegMask(TRI.getCallPreservedMask(CC));
969 
970   CLI.Call = MIB;
971 
972   // Add implicit physical register uses to the call.
973   for (auto Reg : CLI.OutRegs)
974     MIB.addReg(Reg, RegState::Implicit);
975 
976   // Add a register mask with the call-preserved registers.  Proper
977   // defs for return values will be added by setPhysRegsDeadExcept().
978   MIB.addRegMask(TRI.getCallPreservedMask(CC));
979 
980   CLI.Call = MIB;
981   // Finish off the call including any return values.
982   return finishCall(CLI, RetVT, NumBytes);
983 }
984 
985 bool MipsFastISel::selectRet(const Instruction *I) {
986   const ReturnInst *Ret = cast<ReturnInst>(I);
987 
988   if (!FuncInfo.CanLowerReturn)
989     return false;
990   if (Ret->getNumOperands() > 0) {
991     return false;
992   }
993   emitInst(Mips::RetRA);
994   return true;
995 }
996 
997 bool MipsFastISel::selectTrunc(const Instruction *I) {
998   // The high bits for a type smaller than the register size are assumed to be
999   // undefined.
1000   Value *Op = I->getOperand(0);
1001 
1002   EVT SrcVT, DestVT;
1003   SrcVT = TLI.getValueType(Op->getType(), true);
1004   DestVT = TLI.getValueType(I->getType(), true);
1005 
1006   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1007     return false;
1008   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1009     return false;
1010 
1011   unsigned SrcReg = getRegForValue(Op);
1012   if (!SrcReg)
1013     return false;
1014 
1015   // Because the high bits are undefined, a truncate doesn't generate
1016   // any code.
1017   updateValueMap(I, SrcReg);
1018   return true;
1019 }
1020 bool MipsFastISel::selectIntExt(const Instruction *I) {
1021   Type *DestTy = I->getType();
1022   Value *Src = I->getOperand(0);
1023   Type *SrcTy = Src->getType();
1024 
1025   bool isZExt = isa<ZExtInst>(I);
1026   unsigned SrcReg = getRegForValue(Src);
1027   if (!SrcReg)
1028     return false;
1029 
1030   EVT SrcEVT, DestEVT;
1031   SrcEVT = TLI.getValueType(SrcTy, true);
1032   DestEVT = TLI.getValueType(DestTy, true);
1033   if (!SrcEVT.isSimple())
1034     return false;
1035   if (!DestEVT.isSimple())
1036     return false;
1037 
1038   MVT SrcVT = SrcEVT.getSimpleVT();
1039   MVT DestVT = DestEVT.getSimpleVT();
1040   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1041 
1042   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1043     return false;
1044   updateValueMap(I, ResultReg);
1045   return true;
1046 }
1047 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1048                                    unsigned DestReg) {
1049   unsigned ShiftAmt;
1050   switch (SrcVT.SimpleTy) {
1051   default:
1052     return false;
1053   case MVT::i8:
1054     ShiftAmt = 24;
1055     break;
1056   case MVT::i16:
1057     ShiftAmt = 16;
1058     break;
1059   }
1060   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1061   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1062   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1063   return true;
1064 }
1065 
1066 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1067                                    unsigned DestReg) {
1068   switch (SrcVT.SimpleTy) {
1069   default:
1070     return false;
1071   case MVT::i8:
1072     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1073     break;
1074   case MVT::i16:
1075     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1076     break;
1077   }
1078   return true;
1079 }
1080 
1081 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1082                                unsigned DestReg) {
1083   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1084     return false;
1085   if (Subtarget->hasMips32r2())
1086     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1087   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1088 }
1089 
1090 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1091                                unsigned DestReg) {
1092   switch (SrcVT.SimpleTy) {
1093   default:
1094     return false;
1095   case MVT::i1:
1096     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1097     break;
1098   case MVT::i8:
1099     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1100     break;
1101   case MVT::i16:
1102     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1103     break;
1104   }
1105   return true;
1106 }
1107 
1108 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1109                               unsigned DestReg, bool IsZExt) {
1110   if (IsZExt)
1111     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1112   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1113 }
1114 
1115 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1116                                   bool isZExt) {
1117   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1118   return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1119 }
1120 
1121 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1122   if (!TargetSupported)
1123     return false;
1124   switch (I->getOpcode()) {
1125   default:
1126     break;
1127   case Instruction::Load:
1128     return selectLoad(I);
1129   case Instruction::Store:
1130     return selectStore(I);
1131   case Instruction::Br:
1132     return selectBranch(I);
1133   case Instruction::Ret:
1134     return selectRet(I);
1135   case Instruction::Trunc:
1136     return selectTrunc(I);
1137   case Instruction::ZExt:
1138   case Instruction::SExt:
1139     return selectIntExt(I);
1140   case Instruction::FPTrunc:
1141     return selectFPTrunc(I);
1142   case Instruction::FPExt:
1143     return selectFPExt(I);
1144   case Instruction::FPToSI:
1145     return selectFPToInt(I, /*isSigned*/ true);
1146   case Instruction::FPToUI:
1147     return selectFPToInt(I, /*isSigned*/ false);
1148   case Instruction::ICmp:
1149   case Instruction::FCmp:
1150     return selectCmp(I);
1151   }
1152   return false;
1153 }
1154 
1155 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1156                                                            bool IsUnsigned) {
1157   unsigned VReg = getRegForValue(V);
1158   if (VReg == 0)
1159     return 0;
1160   MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1161   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1162     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1163     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1164       return 0;
1165     VReg = TempReg;
1166   }
1167   return VReg;
1168 }
1169 
1170 namespace llvm {
1171 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1172                                const TargetLibraryInfo *libInfo) {
1173   return new MipsFastISel(funcInfo, libInfo);
1174 }
1175 }
1176