1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Analysis/TargetLibraryInfo.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/TargetInstrInfo.h"
40 #include "llvm/CodeGen/TargetLowering.h"
41 #include "llvm/CodeGen/ValueTypes.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/Constant.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DataLayout.h"
47 #include "llvm/IR/Function.h"
48 #include "llvm/IR/GetElementPtrTypeIterator.h"
49 #include "llvm/IR/GlobalValue.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InstrTypes.h"
52 #include "llvm/IR/Instruction.h"
53 #include "llvm/IR/Instructions.h"
54 #include "llvm/IR/IntrinsicInst.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/IR/User.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCInstrDesc.h"
61 #include "llvm/MC/MCRegisterInfo.h"
62 #include "llvm/MC/MCSymbol.h"
63 #include "llvm/Support/Casting.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/Debug.h"
66 #include "llvm/Support/ErrorHandling.h"
67 #include "llvm/Support/MachineValueType.h"
68 #include "llvm/Support/MathExtras.h"
69 #include "llvm/Support/raw_ostream.h"
70 #include <algorithm>
71 #include <array>
72 #include <cassert>
73 #include <cstdint>
74 
75 #define DEBUG_TYPE "mips-fastisel"
76 
77 using namespace llvm;
78 
79 extern cl::opt<bool> EmitJalrReloc;
80 
81 namespace {
82 
83 class MipsFastISel final : public FastISel {
84 
85   // All possible address modes.
86   class Address {
87   public:
88     using BaseKind = enum { RegBase, FrameIndexBase };
89 
90   private:
91     BaseKind Kind = RegBase;
92     union {
93       unsigned Reg;
94       int FI;
95     } Base;
96 
97     int64_t Offset = 0;
98 
99     const GlobalValue *GV = nullptr;
100 
101   public:
102     // Innocuous defaults for our address.
103     Address() { Base.Reg = 0; }
104 
105     void setKind(BaseKind K) { Kind = K; }
106     BaseKind getKind() const { return Kind; }
107     bool isRegBase() const { return Kind == RegBase; }
108     bool isFIBase() const { return Kind == FrameIndexBase; }
109 
110     void setReg(unsigned Reg) {
111       assert(isRegBase() && "Invalid base register access!");
112       Base.Reg = Reg;
113     }
114 
115     unsigned getReg() const {
116       assert(isRegBase() && "Invalid base register access!");
117       return Base.Reg;
118     }
119 
120     void setFI(unsigned FI) {
121       assert(isFIBase() && "Invalid base frame index access!");
122       Base.FI = FI;
123     }
124 
125     unsigned getFI() const {
126       assert(isFIBase() && "Invalid base frame index access!");
127       return Base.FI;
128     }
129 
130     void setOffset(int64_t Offset_) { Offset = Offset_; }
131     int64_t getOffset() const { return Offset; }
132     void setGlobalValue(const GlobalValue *G) { GV = G; }
133     const GlobalValue *getGlobalValue() { return GV; }
134   };
135 
136   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
137   /// make the right decision when generating code for different targets.
138   const TargetMachine &TM;
139   const MipsSubtarget *Subtarget;
140   const TargetInstrInfo &TII;
141   const TargetLowering &TLI;
142   MipsFunctionInfo *MFI;
143 
144   // Convenience variables to avoid some queries.
145   LLVMContext *Context;
146 
147   bool fastLowerArguments() override;
148   bool fastLowerCall(CallLoweringInfo &CLI) override;
149   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
150 
151   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
152   // floating point but not reject doing fast-isel in other
153   // situations
154 
155 private:
156   // Selection routines.
157   bool selectLogicalOp(const Instruction *I);
158   bool selectLoad(const Instruction *I);
159   bool selectStore(const Instruction *I);
160   bool selectBranch(const Instruction *I);
161   bool selectSelect(const Instruction *I);
162   bool selectCmp(const Instruction *I);
163   bool selectFPExt(const Instruction *I);
164   bool selectFPTrunc(const Instruction *I);
165   bool selectFPToInt(const Instruction *I, bool IsSigned);
166   bool selectRet(const Instruction *I);
167   bool selectTrunc(const Instruction *I);
168   bool selectIntExt(const Instruction *I);
169   bool selectShift(const Instruction *I);
170   bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
171 
172   // Utility helper routines.
173   bool isTypeLegal(Type *Ty, MVT &VT);
174   bool isTypeSupported(Type *Ty, MVT &VT);
175   bool isLoadTypeLegal(Type *Ty, MVT &VT);
176   bool computeAddress(const Value *Obj, Address &Addr);
177   bool computeCallAddress(const Value *V, Address &Addr);
178   void simplifyAddress(Address &Addr);
179 
180   // Emit helper routines.
181   bool emitCmp(unsigned DestReg, const CmpInst *CI);
182   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
183                 unsigned Alignment = 0);
184   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
185                  MachineMemOperand *MMO = nullptr);
186   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
187                  unsigned Alignment = 0);
188   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
190 
191                   bool IsZExt);
192   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 
194   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196                        unsigned DestReg);
197   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
198                        unsigned DestReg);
199 
200   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
201 
202   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
203                          const Value *RHS);
204 
205   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
206   unsigned materializeGV(const GlobalValue *GV, MVT VT);
207   unsigned materializeInt(const Constant *C, MVT VT);
208   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
209   unsigned materializeExternalCallSym(MCSymbol *Syn);
210 
211   MachineInstrBuilder emitInst(unsigned Opc) {
212     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
213   }
214 
215   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
216     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
217                    DstReg);
218   }
219 
220   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
221                                     unsigned MemReg, int64_t MemOffset) {
222     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
223   }
224 
225   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
226                                    unsigned MemReg, int64_t MemOffset) {
227     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
228   }
229 
230   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
231                            const TargetRegisterClass *RC,
232                            unsigned Op0, bool Op0IsKill,
233                            unsigned Op1, bool Op1IsKill);
234 
235   // for some reason, this default is not generated by tablegen
236   // so we explicitly generate it here.
237   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
238                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
239                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
240     return 0;
241   }
242 
243   // Call handling routines.
244 private:
245   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
246   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
247                        unsigned &NumBytes);
248   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
249 
250   const MipsABIInfo &getABI() const {
251     return static_cast<const MipsTargetMachine &>(TM).getABI();
252   }
253 
254 public:
255   // Backend specific FastISel code.
256   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
257                         const TargetLibraryInfo *libInfo)
258       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
259         Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
260         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
261     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
262     Context = &funcInfo.Fn->getContext();
263     UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
264   }
265 
266   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
267   unsigned fastMaterializeConstant(const Constant *C) override;
268   bool fastSelectInstruction(const Instruction *I) override;
269 
270 #include "MipsGenFastISel.inc"
271 };
272 
273 } // end anonymous namespace
274 
275 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
276                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
277                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
278 
279 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
280                             CCValAssign::LocInfo LocInfo,
281                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
282   llvm_unreachable("should not be called");
283 }
284 
285 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
286                             CCValAssign::LocInfo LocInfo,
287                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
288   llvm_unreachable("should not be called");
289 }
290 
291 #include "MipsGenCallingConv.inc"
292 
293 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
294   return CC_MipsO32;
295 }
296 
297 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
298                                      const Value *LHS, const Value *RHS) {
299   // Canonicalize immediates to the RHS first.
300   if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
301     std::swap(LHS, RHS);
302 
303   unsigned Opc;
304   switch (ISDOpc) {
305   case ISD::AND:
306     Opc = Mips::AND;
307     break;
308   case ISD::OR:
309     Opc = Mips::OR;
310     break;
311   case ISD::XOR:
312     Opc = Mips::XOR;
313     break;
314   default:
315     llvm_unreachable("unexpected opcode");
316   }
317 
318   unsigned LHSReg = getRegForValue(LHS);
319   if (!LHSReg)
320     return 0;
321 
322   unsigned RHSReg;
323   if (const auto *C = dyn_cast<ConstantInt>(RHS))
324     RHSReg = materializeInt(C, MVT::i32);
325   else
326     RHSReg = getRegForValue(RHS);
327   if (!RHSReg)
328     return 0;
329 
330   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
331   if (!ResultReg)
332     return 0;
333 
334   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
335   return ResultReg;
336 }
337 
338 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
339   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
340          "Alloca should always return a pointer.");
341 
342   DenseMap<const AllocaInst *, int>::iterator SI =
343       FuncInfo.StaticAllocaMap.find(AI);
344 
345   if (SI != FuncInfo.StaticAllocaMap.end()) {
346     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
347     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
348             ResultReg)
349         .addFrameIndex(SI->second)
350         .addImm(0);
351     return ResultReg;
352   }
353 
354   return 0;
355 }
356 
357 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
358   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
359     return 0;
360   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
361   const ConstantInt *CI = cast<ConstantInt>(C);
362   return materialize32BitInt(CI->getZExtValue(), RC);
363 }
364 
365 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
366                                            const TargetRegisterClass *RC) {
367   unsigned ResultReg = createResultReg(RC);
368 
369   if (isInt<16>(Imm)) {
370     unsigned Opc = Mips::ADDiu;
371     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372     return ResultReg;
373   } else if (isUInt<16>(Imm)) {
374     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
375     return ResultReg;
376   }
377   unsigned Lo = Imm & 0xFFFF;
378   unsigned Hi = (Imm >> 16) & 0xFFFF;
379   if (Lo) {
380     // Both Lo and Hi have nonzero bits.
381     unsigned TmpReg = createResultReg(RC);
382     emitInst(Mips::LUi, TmpReg).addImm(Hi);
383     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
384   } else {
385     emitInst(Mips::LUi, ResultReg).addImm(Hi);
386   }
387   return ResultReg;
388 }
389 
390 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
391   if (UnsupportedFPMode)
392     return 0;
393   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
394   if (VT == MVT::f32) {
395     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
396     unsigned DestReg = createResultReg(RC);
397     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
398     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
399     return DestReg;
400   } else if (VT == MVT::f64) {
401     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
402     unsigned DestReg = createResultReg(RC);
403     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
404     unsigned TempReg2 =
405         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
406     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
407     return DestReg;
408   }
409   return 0;
410 }
411 
412 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
413   // For now 32-bit only.
414   if (VT != MVT::i32)
415     return 0;
416   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
417   unsigned DestReg = createResultReg(RC);
418   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
419   bool IsThreadLocal = GVar && GVar->isThreadLocal();
420   // TLS not supported at this time.
421   if (IsThreadLocal)
422     return 0;
423   emitInst(Mips::LW, DestReg)
424       .addReg(MFI->getGlobalBaseReg())
425       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
426   if ((GV->hasInternalLinkage() ||
427        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
428     unsigned TempReg = createResultReg(RC);
429     emitInst(Mips::ADDiu, TempReg)
430         .addReg(DestReg)
431         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
432     DestReg = TempReg;
433   }
434   return DestReg;
435 }
436 
437 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
438   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
439   unsigned DestReg = createResultReg(RC);
440   emitInst(Mips::LW, DestReg)
441       .addReg(MFI->getGlobalBaseReg())
442       .addSym(Sym, MipsII::MO_GOT);
443   return DestReg;
444 }
445 
446 // Materialize a constant into a register, and return the register
447 // number (or zero if we failed to handle it).
448 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
449   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
450 
451   // Only handle simple types.
452   if (!CEVT.isSimple())
453     return 0;
454   MVT VT = CEVT.getSimpleVT();
455 
456   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
457     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
458   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
459     return materializeGV(GV, VT);
460   else if (isa<ConstantInt>(C))
461     return materializeInt(C, VT);
462 
463   return 0;
464 }
465 
466 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
467   const User *U = nullptr;
468   unsigned Opcode = Instruction::UserOp1;
469   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
470     // Don't walk into other basic blocks unless the object is an alloca from
471     // another block, otherwise it may not have a virtual register assigned.
472     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
473         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
474       Opcode = I->getOpcode();
475       U = I;
476     }
477   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
478     Opcode = C->getOpcode();
479     U = C;
480   }
481   switch (Opcode) {
482   default:
483     break;
484   case Instruction::BitCast:
485     // Look through bitcasts.
486     return computeAddress(U->getOperand(0), Addr);
487   case Instruction::GetElementPtr: {
488     Address SavedAddr = Addr;
489     int64_t TmpOffset = Addr.getOffset();
490     // Iterate through the GEP folding the constants into offsets where
491     // we can.
492     gep_type_iterator GTI = gep_type_begin(U);
493     for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
494          ++i, ++GTI) {
495       const Value *Op = *i;
496       if (StructType *STy = GTI.getStructTypeOrNull()) {
497         const StructLayout *SL = DL.getStructLayout(STy);
498         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
499         TmpOffset += SL->getElementOffset(Idx);
500       } else {
501         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
502         while (true) {
503           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
504             // Constant-offset addressing.
505             TmpOffset += CI->getSExtValue() * S;
506             break;
507           }
508           if (canFoldAddIntoGEP(U, Op)) {
509             // A compatible add with a constant operand. Fold the constant.
510             ConstantInt *CI =
511                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
512             TmpOffset += CI->getSExtValue() * S;
513             // Iterate on the other operand.
514             Op = cast<AddOperator>(Op)->getOperand(0);
515             continue;
516           }
517           // Unsupported
518           goto unsupported_gep;
519         }
520       }
521     }
522     // Try to grab the base operand now.
523     Addr.setOffset(TmpOffset);
524     if (computeAddress(U->getOperand(0), Addr))
525       return true;
526     // We failed, restore everything and try the other options.
527     Addr = SavedAddr;
528   unsupported_gep:
529     break;
530   }
531   case Instruction::Alloca: {
532     const AllocaInst *AI = cast<AllocaInst>(Obj);
533     DenseMap<const AllocaInst *, int>::iterator SI =
534         FuncInfo.StaticAllocaMap.find(AI);
535     if (SI != FuncInfo.StaticAllocaMap.end()) {
536       Addr.setKind(Address::FrameIndexBase);
537       Addr.setFI(SI->second);
538       return true;
539     }
540     break;
541   }
542   }
543   Addr.setReg(getRegForValue(Obj));
544   return Addr.getReg() != 0;
545 }
546 
547 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
548   const User *U = nullptr;
549   unsigned Opcode = Instruction::UserOp1;
550 
551   if (const auto *I = dyn_cast<Instruction>(V)) {
552     // Check if the value is defined in the same basic block. This information
553     // is crucial to know whether or not folding an operand is valid.
554     if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
555       Opcode = I->getOpcode();
556       U = I;
557     }
558   } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
559     Opcode = C->getOpcode();
560     U = C;
561   }
562 
563   switch (Opcode) {
564   default:
565     break;
566   case Instruction::BitCast:
567     // Look past bitcasts if its operand is in the same BB.
568       return computeCallAddress(U->getOperand(0), Addr);
569     break;
570   case Instruction::IntToPtr:
571     // Look past no-op inttoptrs if its operand is in the same BB.
572     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
573         TLI.getPointerTy(DL))
574       return computeCallAddress(U->getOperand(0), Addr);
575     break;
576   case Instruction::PtrToInt:
577     // Look past no-op ptrtoints if its operand is in the same BB.
578     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
579       return computeCallAddress(U->getOperand(0), Addr);
580     break;
581   }
582 
583   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
584     Addr.setGlobalValue(GV);
585     return true;
586   }
587 
588   // If all else fails, try to materialize the value in a register.
589   if (!Addr.getGlobalValue()) {
590     Addr.setReg(getRegForValue(V));
591     return Addr.getReg() != 0;
592   }
593 
594   return false;
595 }
596 
597 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
598   EVT evt = TLI.getValueType(DL, Ty, true);
599   // Only handle simple types.
600   if (evt == MVT::Other || !evt.isSimple())
601     return false;
602   VT = evt.getSimpleVT();
603 
604   // Handle all legal types, i.e. a register that will directly hold this
605   // value.
606   return TLI.isTypeLegal(VT);
607 }
608 
609 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
610   if (Ty->isVectorTy())
611     return false;
612 
613   if (isTypeLegal(Ty, VT))
614     return true;
615 
616   // If this is a type than can be sign or zero-extended to a basic operation
617   // go ahead and accept it now.
618   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
619     return true;
620 
621   return false;
622 }
623 
624 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
625   if (isTypeLegal(Ty, VT))
626     return true;
627   // We will extend this in a later patch:
628   //   If this is a type than can be sign or zero-extended to a basic operation
629   //   go ahead and accept it now.
630   if (VT == MVT::i8 || VT == MVT::i16)
631     return true;
632   return false;
633 }
634 
635 // Because of how EmitCmp is called with fast-isel, you can
636 // end up with redundant "andi" instructions after the sequences emitted below.
637 // We should try and solve this issue in the future.
638 //
639 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
640   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
641   bool IsUnsigned = CI->isUnsigned();
642   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
643   if (LeftReg == 0)
644     return false;
645   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
646   if (RightReg == 0)
647     return false;
648   CmpInst::Predicate P = CI->getPredicate();
649 
650   switch (P) {
651   default:
652     return false;
653   case CmpInst::ICMP_EQ: {
654     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
655     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
656     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
657     break;
658   }
659   case CmpInst::ICMP_NE: {
660     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
661     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
662     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
663     break;
664   }
665   case CmpInst::ICMP_UGT:
666     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
667     break;
668   case CmpInst::ICMP_ULT:
669     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
670     break;
671   case CmpInst::ICMP_UGE: {
672     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
673     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
674     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
675     break;
676   }
677   case CmpInst::ICMP_ULE: {
678     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
679     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
680     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
681     break;
682   }
683   case CmpInst::ICMP_SGT:
684     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
685     break;
686   case CmpInst::ICMP_SLT:
687     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
688     break;
689   case CmpInst::ICMP_SGE: {
690     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
691     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
692     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
693     break;
694   }
695   case CmpInst::ICMP_SLE: {
696     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
697     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
698     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
699     break;
700   }
701   case CmpInst::FCMP_OEQ:
702   case CmpInst::FCMP_UNE:
703   case CmpInst::FCMP_OLT:
704   case CmpInst::FCMP_OLE:
705   case CmpInst::FCMP_OGT:
706   case CmpInst::FCMP_OGE: {
707     if (UnsupportedFPMode)
708       return false;
709     bool IsFloat = Left->getType()->isFloatTy();
710     bool IsDouble = Left->getType()->isDoubleTy();
711     if (!IsFloat && !IsDouble)
712       return false;
713     unsigned Opc, CondMovOpc;
714     switch (P) {
715     case CmpInst::FCMP_OEQ:
716       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
717       CondMovOpc = Mips::MOVT_I;
718       break;
719     case CmpInst::FCMP_UNE:
720       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
721       CondMovOpc = Mips::MOVF_I;
722       break;
723     case CmpInst::FCMP_OLT:
724       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
725       CondMovOpc = Mips::MOVT_I;
726       break;
727     case CmpInst::FCMP_OLE:
728       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
729       CondMovOpc = Mips::MOVT_I;
730       break;
731     case CmpInst::FCMP_OGT:
732       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
733       CondMovOpc = Mips::MOVF_I;
734       break;
735     case CmpInst::FCMP_OGE:
736       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
737       CondMovOpc = Mips::MOVF_I;
738       break;
739     default:
740       llvm_unreachable("Only switching of a subset of CCs.");
741     }
742     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
743     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
744     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
745     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
746     emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
747                  .addReg(RightReg);
748     emitInst(CondMovOpc, ResultReg)
749         .addReg(RegWithOne)
750         .addReg(Mips::FCC0)
751         .addReg(RegWithZero);
752     break;
753   }
754   }
755   return true;
756 }
757 
758 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
759                             unsigned Alignment) {
760   //
761   // more cases will be handled here in following patches.
762   //
763   unsigned Opc;
764   switch (VT.SimpleTy) {
765   case MVT::i32:
766     ResultReg = createResultReg(&Mips::GPR32RegClass);
767     Opc = Mips::LW;
768     break;
769   case MVT::i16:
770     ResultReg = createResultReg(&Mips::GPR32RegClass);
771     Opc = Mips::LHu;
772     break;
773   case MVT::i8:
774     ResultReg = createResultReg(&Mips::GPR32RegClass);
775     Opc = Mips::LBu;
776     break;
777   case MVT::f32:
778     if (UnsupportedFPMode)
779       return false;
780     ResultReg = createResultReg(&Mips::FGR32RegClass);
781     Opc = Mips::LWC1;
782     break;
783   case MVT::f64:
784     if (UnsupportedFPMode)
785       return false;
786     ResultReg = createResultReg(&Mips::AFGR64RegClass);
787     Opc = Mips::LDC1;
788     break;
789   default:
790     return false;
791   }
792   if (Addr.isRegBase()) {
793     simplifyAddress(Addr);
794     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
795     return true;
796   }
797   if (Addr.isFIBase()) {
798     unsigned FI = Addr.getFI();
799     unsigned Align = 4;
800     int64_t Offset = Addr.getOffset();
801     MachineFrameInfo &MFI = MF->getFrameInfo();
802     MachineMemOperand *MMO = MF->getMachineMemOperand(
803         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
804         MFI.getObjectSize(FI), Align);
805     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
806         .addFrameIndex(FI)
807         .addImm(Offset)
808         .addMemOperand(MMO);
809     return true;
810   }
811   return false;
812 }
813 
814 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
815                              unsigned Alignment) {
816   //
817   // more cases will be handled here in following patches.
818   //
819   unsigned Opc;
820   switch (VT.SimpleTy) {
821   case MVT::i8:
822     Opc = Mips::SB;
823     break;
824   case MVT::i16:
825     Opc = Mips::SH;
826     break;
827   case MVT::i32:
828     Opc = Mips::SW;
829     break;
830   case MVT::f32:
831     if (UnsupportedFPMode)
832       return false;
833     Opc = Mips::SWC1;
834     break;
835   case MVT::f64:
836     if (UnsupportedFPMode)
837       return false;
838     Opc = Mips::SDC1;
839     break;
840   default:
841     return false;
842   }
843   if (Addr.isRegBase()) {
844     simplifyAddress(Addr);
845     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
846     return true;
847   }
848   if (Addr.isFIBase()) {
849     unsigned FI = Addr.getFI();
850     unsigned Align = 4;
851     int64_t Offset = Addr.getOffset();
852     MachineFrameInfo &MFI = MF->getFrameInfo();
853     MachineMemOperand *MMO = MF->getMachineMemOperand(
854         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
855         MFI.getObjectSize(FI), Align);
856     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
857         .addReg(SrcReg)
858         .addFrameIndex(FI)
859         .addImm(Offset)
860         .addMemOperand(MMO);
861     return true;
862   }
863   return false;
864 }
865 
866 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
867   MVT VT;
868   if (!isTypeSupported(I->getType(), VT))
869     return false;
870 
871   unsigned ResultReg;
872   switch (I->getOpcode()) {
873   default:
874     llvm_unreachable("Unexpected instruction.");
875   case Instruction::And:
876     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
877     break;
878   case Instruction::Or:
879     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
880     break;
881   case Instruction::Xor:
882     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
883     break;
884   }
885 
886   if (!ResultReg)
887     return false;
888 
889   updateValueMap(I, ResultReg);
890   return true;
891 }
892 
893 bool MipsFastISel::selectLoad(const Instruction *I) {
894   // Atomic loads need special handling.
895   if (cast<LoadInst>(I)->isAtomic())
896     return false;
897 
898   // Verify we have a legal type before going any further.
899   MVT VT;
900   if (!isLoadTypeLegal(I->getType(), VT))
901     return false;
902 
903   // See if we can handle this address.
904   Address Addr;
905   if (!computeAddress(I->getOperand(0), Addr))
906     return false;
907 
908   unsigned ResultReg;
909   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
910     return false;
911   updateValueMap(I, ResultReg);
912   return true;
913 }
914 
915 bool MipsFastISel::selectStore(const Instruction *I) {
916   Value *Op0 = I->getOperand(0);
917   unsigned SrcReg = 0;
918 
919   // Atomic stores need special handling.
920   if (cast<StoreInst>(I)->isAtomic())
921     return false;
922 
923   // Verify we have a legal type before going any further.
924   MVT VT;
925   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
926     return false;
927 
928   // Get the value to be stored into a register.
929   SrcReg = getRegForValue(Op0);
930   if (SrcReg == 0)
931     return false;
932 
933   // See if we can handle this address.
934   Address Addr;
935   if (!computeAddress(I->getOperand(1), Addr))
936     return false;
937 
938   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
939     return false;
940   return true;
941 }
942 
943 // This can cause a redundant sltiu to be generated.
944 // FIXME: try and eliminate this in a future patch.
945 bool MipsFastISel::selectBranch(const Instruction *I) {
946   const BranchInst *BI = cast<BranchInst>(I);
947   MachineBasicBlock *BrBB = FuncInfo.MBB;
948   //
949   // TBB is the basic block for the case where the comparison is true.
950   // FBB is the basic block for the case where the comparison is false.
951   // if (cond) goto TBB
952   // goto FBB
953   // TBB:
954   //
955   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
956   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
957 
958   // Fold the common case of a conditional branch with a comparison
959   // in the same block.
960   unsigned ZExtCondReg = 0;
961   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
962     if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
963       ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
964       if (!emitCmp(ZExtCondReg, CI))
965         return false;
966     }
967   }
968 
969   // For the general case, we need to mask with 1.
970   if (ZExtCondReg == 0) {
971     unsigned CondReg = getRegForValue(BI->getCondition());
972     if (CondReg == 0)
973       return false;
974 
975     ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
976     if (ZExtCondReg == 0)
977       return false;
978   }
979 
980   BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
981       .addReg(ZExtCondReg)
982       .addMBB(TBB);
983   finishCondBranch(BI->getParent(), TBB, FBB);
984   return true;
985 }
986 
987 bool MipsFastISel::selectCmp(const Instruction *I) {
988   const CmpInst *CI = cast<CmpInst>(I);
989   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
990   if (!emitCmp(ResultReg, CI))
991     return false;
992   updateValueMap(I, ResultReg);
993   return true;
994 }
995 
996 // Attempt to fast-select a floating-point extend instruction.
997 bool MipsFastISel::selectFPExt(const Instruction *I) {
998   if (UnsupportedFPMode)
999     return false;
1000   Value *Src = I->getOperand(0);
1001   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1002   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1003 
1004   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1005     return false;
1006 
1007   unsigned SrcReg =
1008       getRegForValue(Src); // this must be a 32bit floating point register class
1009                            // maybe we should handle this differently
1010   if (!SrcReg)
1011     return false;
1012 
1013   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1014   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1015   updateValueMap(I, DestReg);
1016   return true;
1017 }
1018 
1019 bool MipsFastISel::selectSelect(const Instruction *I) {
1020   assert(isa<SelectInst>(I) && "Expected a select instruction.");
1021 
1022   LLVM_DEBUG(dbgs() << "selectSelect\n");
1023 
1024   MVT VT;
1025   if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1026     LLVM_DEBUG(
1027         dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1028     return false;
1029   }
1030 
1031   unsigned CondMovOpc;
1032   const TargetRegisterClass *RC;
1033 
1034   if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1035     CondMovOpc = Mips::MOVN_I_I;
1036     RC = &Mips::GPR32RegClass;
1037   } else if (VT == MVT::f32) {
1038     CondMovOpc = Mips::MOVN_I_S;
1039     RC = &Mips::FGR32RegClass;
1040   } else if (VT == MVT::f64) {
1041     CondMovOpc = Mips::MOVN_I_D32;
1042     RC = &Mips::AFGR64RegClass;
1043   } else
1044     return false;
1045 
1046   const SelectInst *SI = cast<SelectInst>(I);
1047   const Value *Cond = SI->getCondition();
1048   unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1049   unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1050   unsigned CondReg = getRegForValue(Cond);
1051 
1052   if (!Src1Reg || !Src2Reg || !CondReg)
1053     return false;
1054 
1055   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1056   if (!ZExtCondReg)
1057     return false;
1058 
1059   if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1060     return false;
1061 
1062   unsigned ResultReg = createResultReg(RC);
1063   unsigned TempReg = createResultReg(RC);
1064 
1065   if (!ResultReg || !TempReg)
1066     return false;
1067 
1068   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1069   emitInst(CondMovOpc, ResultReg)
1070     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1071   updateValueMap(I, ResultReg);
1072   return true;
1073 }
1074 
1075 // Attempt to fast-select a floating-point truncate instruction.
1076 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1077   if (UnsupportedFPMode)
1078     return false;
1079   Value *Src = I->getOperand(0);
1080   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1081   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1082 
1083   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1084     return false;
1085 
1086   unsigned SrcReg = getRegForValue(Src);
1087   if (!SrcReg)
1088     return false;
1089 
1090   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1091   if (!DestReg)
1092     return false;
1093 
1094   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1095   updateValueMap(I, DestReg);
1096   return true;
1097 }
1098 
1099 // Attempt to fast-select a floating-point-to-integer conversion.
1100 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1101   if (UnsupportedFPMode)
1102     return false;
1103   MVT DstVT, SrcVT;
1104   if (!IsSigned)
1105     return false; // We don't handle this case yet. There is no native
1106                   // instruction for this but it can be synthesized.
1107   Type *DstTy = I->getType();
1108   if (!isTypeLegal(DstTy, DstVT))
1109     return false;
1110 
1111   if (DstVT != MVT::i32)
1112     return false;
1113 
1114   Value *Src = I->getOperand(0);
1115   Type *SrcTy = Src->getType();
1116   if (!isTypeLegal(SrcTy, SrcVT))
1117     return false;
1118 
1119   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1120     return false;
1121 
1122   unsigned SrcReg = getRegForValue(Src);
1123   if (SrcReg == 0)
1124     return false;
1125 
1126   // Determine the opcode for the conversion, which takes place
1127   // entirely within FPRs.
1128   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1129   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1130   unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1131 
1132   // Generate the convert.
1133   emitInst(Opc, TempReg).addReg(SrcReg);
1134   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1135 
1136   updateValueMap(I, DestReg);
1137   return true;
1138 }
1139 
1140 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1141                                    SmallVectorImpl<MVT> &OutVTs,
1142                                    unsigned &NumBytes) {
1143   CallingConv::ID CC = CLI.CallConv;
1144   SmallVector<CCValAssign, 16> ArgLocs;
1145   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1146   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1147   // Get a count of how many bytes are to be pushed on the stack.
1148   NumBytes = CCInfo.getNextStackOffset();
1149   // This is the minimum argument area used for A0-A3.
1150   if (NumBytes < 16)
1151     NumBytes = 16;
1152 
1153   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1154   // Process the args.
1155   MVT firstMVT;
1156   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1157     CCValAssign &VA = ArgLocs[i];
1158     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1159     MVT ArgVT = OutVTs[VA.getValNo()];
1160 
1161     if (i == 0) {
1162       firstMVT = ArgVT;
1163       if (ArgVT == MVT::f32) {
1164         VA.convertToReg(Mips::F12);
1165       } else if (ArgVT == MVT::f64) {
1166         VA.convertToReg(Mips::D6);
1167       }
1168     } else if (i == 1) {
1169       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1170         if (ArgVT == MVT::f32) {
1171           VA.convertToReg(Mips::F14);
1172         } else if (ArgVT == MVT::f64) {
1173           VA.convertToReg(Mips::D7);
1174         }
1175       }
1176     }
1177     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1178          (ArgVT == MVT::i8)) &&
1179         VA.isMemLoc()) {
1180       switch (VA.getLocMemOffset()) {
1181       case 0:
1182         VA.convertToReg(Mips::A0);
1183         break;
1184       case 4:
1185         VA.convertToReg(Mips::A1);
1186         break;
1187       case 8:
1188         VA.convertToReg(Mips::A2);
1189         break;
1190       case 12:
1191         VA.convertToReg(Mips::A3);
1192         break;
1193       default:
1194         break;
1195       }
1196     }
1197     unsigned ArgReg = getRegForValue(ArgVal);
1198     if (!ArgReg)
1199       return false;
1200 
1201     // Handle arg promotion: SExt, ZExt, AExt.
1202     switch (VA.getLocInfo()) {
1203     case CCValAssign::Full:
1204       break;
1205     case CCValAssign::AExt:
1206     case CCValAssign::SExt: {
1207       MVT DestVT = VA.getLocVT();
1208       MVT SrcVT = ArgVT;
1209       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1210       if (!ArgReg)
1211         return false;
1212       break;
1213     }
1214     case CCValAssign::ZExt: {
1215       MVT DestVT = VA.getLocVT();
1216       MVT SrcVT = ArgVT;
1217       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1218       if (!ArgReg)
1219         return false;
1220       break;
1221     }
1222     default:
1223       llvm_unreachable("Unknown arg promotion!");
1224     }
1225 
1226     // Now copy/store arg to correct locations.
1227     if (VA.isRegLoc() && !VA.needsCustom()) {
1228       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1229               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1230       CLI.OutRegs.push_back(VA.getLocReg());
1231     } else if (VA.needsCustom()) {
1232       llvm_unreachable("Mips does not use custom args.");
1233       return false;
1234     } else {
1235       //
1236       // FIXME: This path will currently return false. It was copied
1237       // from the AArch64 port and should be essentially fine for Mips too.
1238       // The work to finish up this path will be done in a follow-on patch.
1239       //
1240       assert(VA.isMemLoc() && "Assuming store on stack.");
1241       // Don't emit stores for undef values.
1242       if (isa<UndefValue>(ArgVal))
1243         continue;
1244 
1245       // Need to store on the stack.
1246       // FIXME: This alignment is incorrect but this path is disabled
1247       // for now (will return false). We need to determine the right alignment
1248       // based on the normal alignment for the underlying machine type.
1249       //
1250       unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1251 
1252       unsigned BEAlign = 0;
1253       if (ArgSize < 8 && !Subtarget->isLittle())
1254         BEAlign = 8 - ArgSize;
1255 
1256       Address Addr;
1257       Addr.setKind(Address::RegBase);
1258       Addr.setReg(Mips::SP);
1259       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1260 
1261       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1262       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1263           MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1264           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1265       (void)(MMO);
1266       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1267       return false; // can't store on the stack yet.
1268     }
1269   }
1270 
1271   return true;
1272 }
1273 
1274 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1275                               unsigned NumBytes) {
1276   CallingConv::ID CC = CLI.CallConv;
1277   emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1278   if (RetVT != MVT::isVoid) {
1279     SmallVector<CCValAssign, 16> RVLocs;
1280     MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1281 
1282     CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1283                              CLI.Symbol ? CLI.Symbol->getName().data()
1284                                         : nullptr);
1285 
1286     // Only handle a single return value.
1287     if (RVLocs.size() != 1)
1288       return false;
1289     // Copy all of the result registers out of their specified physreg.
1290     MVT CopyVT = RVLocs[0].getValVT();
1291     // Special handling for extended integers.
1292     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1293       CopyVT = MVT::i32;
1294 
1295     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1296     if (!ResultReg)
1297       return false;
1298     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1299             TII.get(TargetOpcode::COPY),
1300             ResultReg).addReg(RVLocs[0].getLocReg());
1301     CLI.InRegs.push_back(RVLocs[0].getLocReg());
1302 
1303     CLI.ResultReg = ResultReg;
1304     CLI.NumResultRegs = 1;
1305   }
1306   return true;
1307 }
1308 
1309 bool MipsFastISel::fastLowerArguments() {
1310   LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1311 
1312   if (!FuncInfo.CanLowerReturn) {
1313     LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1314     return false;
1315   }
1316 
1317   const Function *F = FuncInfo.Fn;
1318   if (F->isVarArg()) {
1319     LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1320     return false;
1321   }
1322 
1323   CallingConv::ID CC = F->getCallingConv();
1324   if (CC != CallingConv::C) {
1325     LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1326     return false;
1327   }
1328 
1329   std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1330                                            Mips::A3}};
1331   std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1332   std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1333   auto NextGPR32 = GPR32ArgRegs.begin();
1334   auto NextFGR32 = FGR32ArgRegs.begin();
1335   auto NextAFGR64 = AFGR64ArgRegs.begin();
1336 
1337   struct AllocatedReg {
1338     const TargetRegisterClass *RC;
1339     unsigned Reg;
1340     AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1341         : RC(RC), Reg(Reg) {}
1342   };
1343 
1344   // Only handle simple cases. i.e. All arguments are directly mapped to
1345   // registers of the appropriate type.
1346   SmallVector<AllocatedReg, 4> Allocation;
1347   for (const auto &FormalArg : F->args()) {
1348     if (FormalArg.hasAttribute(Attribute::InReg) ||
1349         FormalArg.hasAttribute(Attribute::StructRet) ||
1350         FormalArg.hasAttribute(Attribute::ByVal)) {
1351       LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1352       return false;
1353     }
1354 
1355     Type *ArgTy = FormalArg.getType();
1356     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1357       LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1358       return false;
1359     }
1360 
1361     EVT ArgVT = TLI.getValueType(DL, ArgTy);
1362     LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1363                       << ArgVT.getEVTString() << "\n");
1364     if (!ArgVT.isSimple()) {
1365       LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1366       return false;
1367     }
1368 
1369     switch (ArgVT.getSimpleVT().SimpleTy) {
1370     case MVT::i1:
1371     case MVT::i8:
1372     case MVT::i16:
1373       if (!FormalArg.hasAttribute(Attribute::SExt) &&
1374           !FormalArg.hasAttribute(Attribute::ZExt)) {
1375         // It must be any extend, this shouldn't happen for clang-generated IR
1376         // so just fall back on SelectionDAG.
1377         LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1378         return false;
1379       }
1380 
1381       if (NextGPR32 == GPR32ArgRegs.end()) {
1382         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1383         return false;
1384       }
1385 
1386       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1387       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1388 
1389       // Allocating any GPR32 prohibits further use of floating point arguments.
1390       NextFGR32 = FGR32ArgRegs.end();
1391       NextAFGR64 = AFGR64ArgRegs.end();
1392       break;
1393 
1394     case MVT::i32:
1395       if (FormalArg.hasAttribute(Attribute::ZExt)) {
1396         // The O32 ABI does not permit a zero-extended i32.
1397         LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1398         return false;
1399       }
1400 
1401       if (NextGPR32 == GPR32ArgRegs.end()) {
1402         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1403         return false;
1404       }
1405 
1406       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1407       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1408 
1409       // Allocating any GPR32 prohibits further use of floating point arguments.
1410       NextFGR32 = FGR32ArgRegs.end();
1411       NextAFGR64 = AFGR64ArgRegs.end();
1412       break;
1413 
1414     case MVT::f32:
1415       if (UnsupportedFPMode) {
1416         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1417         return false;
1418       }
1419       if (NextFGR32 == FGR32ArgRegs.end()) {
1420         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1421         return false;
1422       }
1423       LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1424       Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1425       // Allocating an FGR32 also allocates the super-register AFGR64, and
1426       // ABI rules require us to skip the corresponding GPR32.
1427       if (NextGPR32 != GPR32ArgRegs.end())
1428         NextGPR32++;
1429       if (NextAFGR64 != AFGR64ArgRegs.end())
1430         NextAFGR64++;
1431       break;
1432 
1433     case MVT::f64:
1434       if (UnsupportedFPMode) {
1435         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1436         return false;
1437       }
1438       if (NextAFGR64 == AFGR64ArgRegs.end()) {
1439         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1440         return false;
1441       }
1442       LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1443       Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1444       // Allocating an FGR32 also allocates the super-register AFGR64, and
1445       // ABI rules require us to skip the corresponding GPR32 pair.
1446       if (NextGPR32 != GPR32ArgRegs.end())
1447         NextGPR32++;
1448       if (NextGPR32 != GPR32ArgRegs.end())
1449         NextGPR32++;
1450       if (NextFGR32 != FGR32ArgRegs.end())
1451         NextFGR32++;
1452       break;
1453 
1454     default:
1455       LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1456       return false;
1457     }
1458   }
1459 
1460   for (const auto &FormalArg : F->args()) {
1461     unsigned ArgNo = FormalArg.getArgNo();
1462     unsigned SrcReg = Allocation[ArgNo].Reg;
1463     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1464     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1465     // Without this, EmitLiveInCopies may eliminate the livein if its only
1466     // use is a bitcast (which isn't turned into an instruction).
1467     unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1468     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1469             TII.get(TargetOpcode::COPY), ResultReg)
1470         .addReg(DstReg, getKillRegState(true));
1471     updateValueMap(&FormalArg, ResultReg);
1472   }
1473 
1474   // Calculate the size of the incoming arguments area.
1475   // We currently reject all the cases where this would be non-zero.
1476   unsigned IncomingArgSizeInBytes = 0;
1477 
1478   // Account for the reserved argument area on ABI's that have one (O32).
1479   // It seems strange to do this on the caller side but it's necessary in
1480   // SelectionDAG's implementation.
1481   IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1482                                     IncomingArgSizeInBytes);
1483 
1484   MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1485                                                     false);
1486 
1487   return true;
1488 }
1489 
1490 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1491   CallingConv::ID CC = CLI.CallConv;
1492   bool IsTailCall = CLI.IsTailCall;
1493   bool IsVarArg = CLI.IsVarArg;
1494   const Value *Callee = CLI.Callee;
1495   MCSymbol *Symbol = CLI.Symbol;
1496 
1497   // Do not handle FastCC.
1498   if (CC == CallingConv::Fast)
1499     return false;
1500 
1501   // Allow SelectionDAG isel to handle tail calls.
1502   if (IsTailCall)
1503     return false;
1504 
1505   // Let SDISel handle vararg functions.
1506   if (IsVarArg)
1507     return false;
1508 
1509   // FIXME: Only handle *simple* calls for now.
1510   MVT RetVT;
1511   if (CLI.RetTy->isVoidTy())
1512     RetVT = MVT::isVoid;
1513   else if (!isTypeSupported(CLI.RetTy, RetVT))
1514     return false;
1515 
1516   for (auto Flag : CLI.OutFlags)
1517     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1518       return false;
1519 
1520   // Set up the argument vectors.
1521   SmallVector<MVT, 16> OutVTs;
1522   OutVTs.reserve(CLI.OutVals.size());
1523 
1524   for (auto *Val : CLI.OutVals) {
1525     MVT VT;
1526     if (!isTypeLegal(Val->getType(), VT) &&
1527         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1528       return false;
1529 
1530     // We don't handle vector parameters yet.
1531     if (VT.isVector() || VT.getSizeInBits() > 64)
1532       return false;
1533 
1534     OutVTs.push_back(VT);
1535   }
1536 
1537   Address Addr;
1538   if (!computeCallAddress(Callee, Addr))
1539     return false;
1540 
1541   // Handle the arguments now that we've gotten them.
1542   unsigned NumBytes;
1543   if (!processCallArgs(CLI, OutVTs, NumBytes))
1544     return false;
1545 
1546   if (!Addr.getGlobalValue())
1547     return false;
1548 
1549   // Issue the call.
1550   unsigned DestAddress;
1551   if (Symbol)
1552     DestAddress = materializeExternalCallSym(Symbol);
1553   else
1554     DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1555   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1556   MachineInstrBuilder MIB =
1557       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1558               Mips::RA).addReg(Mips::T9);
1559 
1560   // Add implicit physical register uses to the call.
1561   for (auto Reg : CLI.OutRegs)
1562     MIB.addReg(Reg, RegState::Implicit);
1563 
1564   // Add a register mask with the call-preserved registers.
1565   // Proper defs for return values will be added by setPhysRegsDeadExcept().
1566   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1567 
1568   CLI.Call = MIB;
1569 
1570   if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1571     // Attach callee address to the instruction, let asm printer emit
1572     // .reloc R_MIPS_JALR.
1573     if (Symbol)
1574       MIB.addSym(Symbol, MipsII::MO_JALR);
1575     else
1576       MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1577 	                   Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1578   }
1579 
1580   // Finish off the call including any return values.
1581   return finishCall(CLI, RetVT, NumBytes);
1582 }
1583 
1584 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1585   switch (II->getIntrinsicID()) {
1586   default:
1587     return false;
1588   case Intrinsic::bswap: {
1589     Type *RetTy = II->getCalledFunction()->getReturnType();
1590 
1591     MVT VT;
1592     if (!isTypeSupported(RetTy, VT))
1593       return false;
1594 
1595     unsigned SrcReg = getRegForValue(II->getOperand(0));
1596     if (SrcReg == 0)
1597       return false;
1598     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1599     if (DestReg == 0)
1600       return false;
1601     if (VT == MVT::i16) {
1602       if (Subtarget->hasMips32r2()) {
1603         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1604         updateValueMap(II, DestReg);
1605         return true;
1606       } else {
1607         unsigned TempReg[3];
1608         for (int i = 0; i < 3; i++) {
1609           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1610           if (TempReg[i] == 0)
1611             return false;
1612         }
1613         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1614         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1615         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1616         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1617         updateValueMap(II, DestReg);
1618         return true;
1619       }
1620     } else if (VT == MVT::i32) {
1621       if (Subtarget->hasMips32r2()) {
1622         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1623         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1624         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1625         updateValueMap(II, DestReg);
1626         return true;
1627       } else {
1628         unsigned TempReg[8];
1629         for (int i = 0; i < 8; i++) {
1630           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1631           if (TempReg[i] == 0)
1632             return false;
1633         }
1634 
1635         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1636         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1637         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1638         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1639 
1640         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1641         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1642 
1643         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1644         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1645         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1646         updateValueMap(II, DestReg);
1647         return true;
1648       }
1649     }
1650     return false;
1651   }
1652   case Intrinsic::memcpy:
1653   case Intrinsic::memmove: {
1654     const auto *MTI = cast<MemTransferInst>(II);
1655     // Don't handle volatile.
1656     if (MTI->isVolatile())
1657       return false;
1658     if (!MTI->getLength()->getType()->isIntegerTy(32))
1659       return false;
1660     const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1661     return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1662   }
1663   case Intrinsic::memset: {
1664     const MemSetInst *MSI = cast<MemSetInst>(II);
1665     // Don't handle volatile.
1666     if (MSI->isVolatile())
1667       return false;
1668     if (!MSI->getLength()->getType()->isIntegerTy(32))
1669       return false;
1670     return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1671   }
1672   }
1673   return false;
1674 }
1675 
1676 bool MipsFastISel::selectRet(const Instruction *I) {
1677   const Function &F = *I->getParent()->getParent();
1678   const ReturnInst *Ret = cast<ReturnInst>(I);
1679 
1680   LLVM_DEBUG(dbgs() << "selectRet\n");
1681 
1682   if (!FuncInfo.CanLowerReturn)
1683     return false;
1684 
1685   // Build a list of return value registers.
1686   SmallVector<unsigned, 4> RetRegs;
1687 
1688   if (Ret->getNumOperands() > 0) {
1689     CallingConv::ID CC = F.getCallingConv();
1690 
1691     // Do not handle FastCC.
1692     if (CC == CallingConv::Fast)
1693       return false;
1694 
1695     SmallVector<ISD::OutputArg, 4> Outs;
1696     GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1697 
1698     // Analyze operands of the call, assigning locations to each operand.
1699     SmallVector<CCValAssign, 16> ValLocs;
1700     MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1701                        I->getContext());
1702     CCAssignFn *RetCC = RetCC_Mips;
1703     CCInfo.AnalyzeReturn(Outs, RetCC);
1704 
1705     // Only handle a single return value for now.
1706     if (ValLocs.size() != 1)
1707       return false;
1708 
1709     CCValAssign &VA = ValLocs[0];
1710     const Value *RV = Ret->getOperand(0);
1711 
1712     // Don't bother handling odd stuff for now.
1713     if ((VA.getLocInfo() != CCValAssign::Full) &&
1714         (VA.getLocInfo() != CCValAssign::BCvt))
1715       return false;
1716 
1717     // Only handle register returns for now.
1718     if (!VA.isRegLoc())
1719       return false;
1720 
1721     unsigned Reg = getRegForValue(RV);
1722     if (Reg == 0)
1723       return false;
1724 
1725     unsigned SrcReg = Reg + VA.getValNo();
1726     unsigned DestReg = VA.getLocReg();
1727     // Avoid a cross-class copy. This is very unlikely.
1728     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1729       return false;
1730 
1731     EVT RVEVT = TLI.getValueType(DL, RV->getType());
1732     if (!RVEVT.isSimple())
1733       return false;
1734 
1735     if (RVEVT.isVector())
1736       return false;
1737 
1738     MVT RVVT = RVEVT.getSimpleVT();
1739     if (RVVT == MVT::f128)
1740       return false;
1741 
1742     // Do not handle FGR64 returns for now.
1743     if (RVVT == MVT::f64 && UnsupportedFPMode) {
1744       LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1745       return false;
1746     }
1747 
1748     MVT DestVT = VA.getValVT();
1749     // Special handling for extended integers.
1750     if (RVVT != DestVT) {
1751       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1752         return false;
1753 
1754       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1755         bool IsZExt = Outs[0].Flags.isZExt();
1756         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1757         if (SrcReg == 0)
1758           return false;
1759       }
1760     }
1761 
1762     // Make the copy.
1763     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1764             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1765 
1766     // Add register to return instruction.
1767     RetRegs.push_back(VA.getLocReg());
1768   }
1769   MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1770   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1771     MIB.addReg(RetRegs[i], RegState::Implicit);
1772   return true;
1773 }
1774 
1775 bool MipsFastISel::selectTrunc(const Instruction *I) {
1776   // The high bits for a type smaller than the register size are assumed to be
1777   // undefined.
1778   Value *Op = I->getOperand(0);
1779 
1780   EVT SrcVT, DestVT;
1781   SrcVT = TLI.getValueType(DL, Op->getType(), true);
1782   DestVT = TLI.getValueType(DL, I->getType(), true);
1783 
1784   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1785     return false;
1786   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1787     return false;
1788 
1789   unsigned SrcReg = getRegForValue(Op);
1790   if (!SrcReg)
1791     return false;
1792 
1793   // Because the high bits are undefined, a truncate doesn't generate
1794   // any code.
1795   updateValueMap(I, SrcReg);
1796   return true;
1797 }
1798 
1799 bool MipsFastISel::selectIntExt(const Instruction *I) {
1800   Type *DestTy = I->getType();
1801   Value *Src = I->getOperand(0);
1802   Type *SrcTy = Src->getType();
1803 
1804   bool isZExt = isa<ZExtInst>(I);
1805   unsigned SrcReg = getRegForValue(Src);
1806   if (!SrcReg)
1807     return false;
1808 
1809   EVT SrcEVT, DestEVT;
1810   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1811   DestEVT = TLI.getValueType(DL, DestTy, true);
1812   if (!SrcEVT.isSimple())
1813     return false;
1814   if (!DestEVT.isSimple())
1815     return false;
1816 
1817   MVT SrcVT = SrcEVT.getSimpleVT();
1818   MVT DestVT = DestEVT.getSimpleVT();
1819   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1820 
1821   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1822     return false;
1823   updateValueMap(I, ResultReg);
1824   return true;
1825 }
1826 
1827 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1828                                    unsigned DestReg) {
1829   unsigned ShiftAmt;
1830   switch (SrcVT.SimpleTy) {
1831   default:
1832     return false;
1833   case MVT::i8:
1834     ShiftAmt = 24;
1835     break;
1836   case MVT::i16:
1837     ShiftAmt = 16;
1838     break;
1839   }
1840   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1841   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1842   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1843   return true;
1844 }
1845 
1846 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1847                                    unsigned DestReg) {
1848   switch (SrcVT.SimpleTy) {
1849   default:
1850     return false;
1851   case MVT::i8:
1852     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1853     break;
1854   case MVT::i16:
1855     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1856     break;
1857   }
1858   return true;
1859 }
1860 
1861 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1862                                unsigned DestReg) {
1863   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1864     return false;
1865   if (Subtarget->hasMips32r2())
1866     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1867   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1868 }
1869 
1870 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1871                                unsigned DestReg) {
1872   int64_t Imm;
1873 
1874   switch (SrcVT.SimpleTy) {
1875   default:
1876     return false;
1877   case MVT::i1:
1878     Imm = 1;
1879     break;
1880   case MVT::i8:
1881     Imm = 0xff;
1882     break;
1883   case MVT::i16:
1884     Imm = 0xffff;
1885     break;
1886   }
1887 
1888   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1889   return true;
1890 }
1891 
1892 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1893                               unsigned DestReg, bool IsZExt) {
1894   // FastISel does not have plumbing to deal with extensions where the SrcVT or
1895   // DestVT are odd things, so test to make sure that they are both types we can
1896   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1897   // bail out to SelectionDAG.
1898   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1899       ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1900     return false;
1901   if (IsZExt)
1902     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1903   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1904 }
1905 
1906 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1907                                   bool isZExt) {
1908   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1909   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1910   return Success ? DestReg : 0;
1911 }
1912 
1913 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1914   EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1915   if (!DestEVT.isSimple())
1916     return false;
1917 
1918   MVT DestVT = DestEVT.getSimpleVT();
1919   if (DestVT != MVT::i32)
1920     return false;
1921 
1922   unsigned DivOpc;
1923   switch (ISDOpcode) {
1924   default:
1925     return false;
1926   case ISD::SDIV:
1927   case ISD::SREM:
1928     DivOpc = Mips::SDIV;
1929     break;
1930   case ISD::UDIV:
1931   case ISD::UREM:
1932     DivOpc = Mips::UDIV;
1933     break;
1934   }
1935 
1936   unsigned Src0Reg = getRegForValue(I->getOperand(0));
1937   unsigned Src1Reg = getRegForValue(I->getOperand(1));
1938   if (!Src0Reg || !Src1Reg)
1939     return false;
1940 
1941   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1942   emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1943 
1944   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1945   if (!ResultReg)
1946     return false;
1947 
1948   unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1949                        ? Mips::MFHI
1950                        : Mips::MFLO;
1951   emitInst(MFOpc, ResultReg);
1952 
1953   updateValueMap(I, ResultReg);
1954   return true;
1955 }
1956 
1957 bool MipsFastISel::selectShift(const Instruction *I) {
1958   MVT RetVT;
1959 
1960   if (!isTypeSupported(I->getType(), RetVT))
1961     return false;
1962 
1963   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1964   if (!ResultReg)
1965     return false;
1966 
1967   unsigned Opcode = I->getOpcode();
1968   const Value *Op0 = I->getOperand(0);
1969   unsigned Op0Reg = getRegForValue(Op0);
1970   if (!Op0Reg)
1971     return false;
1972 
1973   // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1974   if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1975     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1976     if (!TempReg)
1977       return false;
1978 
1979     MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1980     bool IsZExt = Opcode == Instruction::LShr;
1981     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1982       return false;
1983 
1984     Op0Reg = TempReg;
1985   }
1986 
1987   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1988     uint64_t ShiftVal = C->getZExtValue();
1989 
1990     switch (Opcode) {
1991     default:
1992       llvm_unreachable("Unexpected instruction.");
1993     case Instruction::Shl:
1994       Opcode = Mips::SLL;
1995       break;
1996     case Instruction::AShr:
1997       Opcode = Mips::SRA;
1998       break;
1999     case Instruction::LShr:
2000       Opcode = Mips::SRL;
2001       break;
2002     }
2003 
2004     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
2005     updateValueMap(I, ResultReg);
2006     return true;
2007   }
2008 
2009   unsigned Op1Reg = getRegForValue(I->getOperand(1));
2010   if (!Op1Reg)
2011     return false;
2012 
2013   switch (Opcode) {
2014   default:
2015     llvm_unreachable("Unexpected instruction.");
2016   case Instruction::Shl:
2017     Opcode = Mips::SLLV;
2018     break;
2019   case Instruction::AShr:
2020     Opcode = Mips::SRAV;
2021     break;
2022   case Instruction::LShr:
2023     Opcode = Mips::SRLV;
2024     break;
2025   }
2026 
2027   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2028   updateValueMap(I, ResultReg);
2029   return true;
2030 }
2031 
2032 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2033   switch (I->getOpcode()) {
2034   default:
2035     break;
2036   case Instruction::Load:
2037     return selectLoad(I);
2038   case Instruction::Store:
2039     return selectStore(I);
2040   case Instruction::SDiv:
2041     if (!selectBinaryOp(I, ISD::SDIV))
2042       return selectDivRem(I, ISD::SDIV);
2043     return true;
2044   case Instruction::UDiv:
2045     if (!selectBinaryOp(I, ISD::UDIV))
2046       return selectDivRem(I, ISD::UDIV);
2047     return true;
2048   case Instruction::SRem:
2049     if (!selectBinaryOp(I, ISD::SREM))
2050       return selectDivRem(I, ISD::SREM);
2051     return true;
2052   case Instruction::URem:
2053     if (!selectBinaryOp(I, ISD::UREM))
2054       return selectDivRem(I, ISD::UREM);
2055     return true;
2056   case Instruction::Shl:
2057   case Instruction::LShr:
2058   case Instruction::AShr:
2059     return selectShift(I);
2060   case Instruction::And:
2061   case Instruction::Or:
2062   case Instruction::Xor:
2063     return selectLogicalOp(I);
2064   case Instruction::Br:
2065     return selectBranch(I);
2066   case Instruction::Ret:
2067     return selectRet(I);
2068   case Instruction::Trunc:
2069     return selectTrunc(I);
2070   case Instruction::ZExt:
2071   case Instruction::SExt:
2072     return selectIntExt(I);
2073   case Instruction::FPTrunc:
2074     return selectFPTrunc(I);
2075   case Instruction::FPExt:
2076     return selectFPExt(I);
2077   case Instruction::FPToSI:
2078     return selectFPToInt(I, /*isSigned*/ true);
2079   case Instruction::FPToUI:
2080     return selectFPToInt(I, /*isSigned*/ false);
2081   case Instruction::ICmp:
2082   case Instruction::FCmp:
2083     return selectCmp(I);
2084   case Instruction::Select:
2085     return selectSelect(I);
2086   }
2087   return false;
2088 }
2089 
2090 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2091                                                            bool IsUnsigned) {
2092   unsigned VReg = getRegForValue(V);
2093   if (VReg == 0)
2094     return 0;
2095   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2096 
2097   if (VMVT == MVT::i1)
2098     return 0;
2099 
2100   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2101     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2102     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2103       return 0;
2104     VReg = TempReg;
2105   }
2106   return VReg;
2107 }
2108 
2109 void MipsFastISel::simplifyAddress(Address &Addr) {
2110   if (!isInt<16>(Addr.getOffset())) {
2111     unsigned TempReg =
2112         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2113     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2114     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2115     Addr.setReg(DestReg);
2116     Addr.setOffset(0);
2117   }
2118 }
2119 
2120 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2121                                        const TargetRegisterClass *RC,
2122                                        unsigned Op0, bool Op0IsKill,
2123                                        unsigned Op1, bool Op1IsKill) {
2124   // We treat the MUL instruction in a special way because it clobbers
2125   // the HI0 & LO0 registers. The TableGen definition of this instruction can
2126   // mark these registers only as implicitly defined. As a result, the
2127   // register allocator runs out of registers when this instruction is
2128   // followed by another instruction that defines the same registers too.
2129   // We can fix this by explicitly marking those registers as dead.
2130   if (MachineInstOpcode == Mips::MUL) {
2131     unsigned ResultReg = createResultReg(RC);
2132     const MCInstrDesc &II = TII.get(MachineInstOpcode);
2133     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2134     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2135     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2136       .addReg(Op0, getKillRegState(Op0IsKill))
2137       .addReg(Op1, getKillRegState(Op1IsKill))
2138       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2139       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2140     return ResultReg;
2141   }
2142 
2143   return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2144                                    Op1IsKill);
2145 }
2146 
2147 namespace llvm {
2148 
2149 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2150                                const TargetLibraryInfo *libInfo) {
2151   return new MipsFastISel(funcInfo, libInfo);
2152 }
2153 
2154 } // end namespace llvm
2155