1//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MSP430 register file 12//===----------------------------------------------------------------------===// 13 14class MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> { 15 field bits<4> Num = num; 16 let Namespace = "MSP430"; 17 let HWEncoding{3-0} = num; 18 let AltNames = alt; 19} 20 21class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs, 22 list<string> alt = []> 23 : RegisterWithSubRegs<n, subregs> { 24 field bits<4> Num = num; 25 let Namespace = "MSP430"; 26 let HWEncoding{3-0} = num; 27 let AltNames = alt; 28} 29 30//===----------------------------------------------------------------------===// 31// Registers 32//===----------------------------------------------------------------------===// 33 34def PCB : MSP430Reg<0, "r0", ["pc"]>; 35def SPB : MSP430Reg<1, "r1", ["sp"]>; 36def SRB : MSP430Reg<2, "r2", ["sr"]>; 37def CGB : MSP430Reg<3, "r3", ["cg"]>; 38def FPB : MSP430Reg<4, "r4", ["fp"]>; 39def R5B : MSP430Reg<5, "r5">; 40def R6B : MSP430Reg<6, "r6">; 41def R7B : MSP430Reg<7, "r7">; 42def R8B : MSP430Reg<8, "r8">; 43def R9B : MSP430Reg<9, "r9">; 44def R10B : MSP430Reg<10, "r10">; 45def R11B : MSP430Reg<11, "r11">; 46def R12B : MSP430Reg<12, "r12">; 47def R13B : MSP430Reg<13, "r13">; 48def R14B : MSP430Reg<14, "r14">; 49def R15B : MSP430Reg<15, "r15">; 50 51def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } 52 53let SubRegIndices = [subreg_8bit] in { 54def PC : MSP430RegWithSubregs<0, "r0", [PCB], ["pc"]>; 55def SP : MSP430RegWithSubregs<1, "r1", [SPB], ["sp"]>; 56def SR : MSP430RegWithSubregs<2, "r2", [SRB], ["sr"]>; 57def CG : MSP430RegWithSubregs<3, "r3", [CGB], ["cg"]>; 58def FP : MSP430RegWithSubregs<4, "r4", [FPB], ["fp"]>; 59def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; 60def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; 61def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; 62def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; 63def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; 64def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; 65def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; 66def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; 67def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; 68def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; 69def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; 70} 71 72def GR8 : RegisterClass<"MSP430", [i8], 8, 73 // Volatile registers 74 (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, 75 // Frame pointer, sometimes allocable 76 FPB, 77 // Volatile, but not allocable 78 PCB, SPB, SRB, CGB)>; 79 80def GR16 : RegisterClass<"MSP430", [i16], 16, 81 // Volatile registers 82 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, 83 // Frame pointer, sometimes allocable 84 FP, 85 // Volatile, but not allocable 86 PC, SP, SR, CG)>; 87