1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "arm-subtarget"
38 
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #define GET_SUBTARGETINFO_CTOR
41 #include "ARMGenSubtargetInfo.inc"
42 
43 static cl::opt<bool>
44 UseFusedMulOps("arm-use-mulops",
45                cl::init(true), cl::Hidden);
46 
47 enum ITMode {
48   DefaultIT,
49   RestrictedIT,
50   NoRestrictedIT
51 };
52 
53 static cl::opt<ITMode>
54 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55    cl::ZeroOrMore,
56    cl::values(clEnumValN(DefaultIT, "arm-default-it",
57                          "Generate IT block based on arch"),
58               clEnumValN(RestrictedIT, "arm-restrict-it",
59                          "Disallow deprecated IT based on ARMv8"),
60               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
61                          "Allow IT blocks based on ARMv7"),
62               clEnumValEnd));
63 
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68                cl::init(false), cl::Hidden);
69 
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73                                                             StringRef FS) {
74   initializeEnvironment();
75   initSubtargetFeatures(CPU, FS);
76   return *this;
77 }
78 
79 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80                                                         StringRef FS) {
81   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82   if (STI.isThumb1Only())
83     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84 
85   return new ARMFrameLowering(STI);
86 }
87 
88 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89                            const std::string &FS,
90                            const ARMBaseTargetMachine &TM, bool IsLittle)
91     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
92       ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
93       IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
94       FrameLowering(initializeFrameLowering(CPU, FS)),
95       // At this point initializeSubtargetDependencies has been called so
96       // we can query directly.
97       InstrInfo(isThumb1Only()
98                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99                     : !isThumb()
100                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102       TLInfo(TM, *this) {}
103 
104 void ARMSubtarget::initializeEnvironment() {
105   HasV4TOps = false;
106   HasV5TOps = false;
107   HasV5TEOps = false;
108   HasV6Ops = false;
109   HasV6MOps = false;
110   HasV6KOps = false;
111   HasV6T2Ops = false;
112   HasV7Ops = false;
113   HasV8Ops = false;
114   HasV8_1aOps = false;
115   HasV8_2aOps = false;
116   HasVFPv2 = false;
117   HasVFPv3 = false;
118   HasVFPv4 = false;
119   HasFPARMv8 = false;
120   HasNEON = false;
121   UseNEONForSinglePrecisionFP = false;
122   UseMulOps = UseFusedMulOps;
123   SlowFPVMLx = false;
124   HasVMLxForwarding = false;
125   SlowFPBrcc = false;
126   InThumbMode = false;
127   UseSoftFloat = false;
128   HasThumb2 = false;
129   NoARM = false;
130   ReserveR9 = false;
131   NoMovt = false;
132   SupportsTailCall = false;
133   HasFP16 = false;
134   HasFullFP16 = false;
135   HasD16 = false;
136   HasHardwareDivide = false;
137   HasHardwareDivideInARM = false;
138   HasT2ExtractPack = false;
139   HasDataBarrier = false;
140   Pref32BitThumb = false;
141   AvoidCPSRPartialUpdate = false;
142   AvoidMOVsShifterOperand = false;
143   HasRAS = false;
144   HasMPExtension = false;
145   HasVirtualization = false;
146   FPOnlySP = false;
147   HasPerfMon = false;
148   HasTrustZone = false;
149   HasCrypto = false;
150   HasCRC = false;
151   HasZeroCycleZeroing = false;
152   StrictAlign = false;
153   HasDSP = false;
154   UseNaClTrap = false;
155   GenLongCalls = false;
156   UnsafeFPMath = false;
157 
158   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
159   // directly from it, but we can try to make sure they're consistent when both
160   // available.
161   UseSjLjEH = isTargetDarwin() && !isTargetWatchOS();
162   assert((!TM.getMCAsmInfo() ||
163           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
164            ExceptionHandling::SjLj) == UseSjLjEH) &&
165          "inconsistent sjlj choice between CodeGen and MC");
166 }
167 
168 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
169   if (CPUString.empty()) {
170     CPUString = "generic";
171 
172     if (isTargetDarwin()) {
173       StringRef ArchName = TargetTriple.getArchName();
174       if (ArchName.endswith("v7s"))
175         // Default to the Swift CPU when targeting armv7s/thumbv7s.
176         CPUString = "swift";
177       else if (ArchName.endswith("v7k"))
178         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
179         // ARMv7k does not use SjLj exception handling.
180         CPUString = "cortex-a7";
181     }
182   }
183 
184   // Insert the architecture feature derived from the target triple into the
185   // feature string. This is important for setting features that are implied
186   // based on the architecture version.
187   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
188   if (!FS.empty()) {
189     if (!ArchFS.empty())
190       ArchFS = (Twine(ArchFS) + "," + FS).str();
191     else
192       ArchFS = FS;
193   }
194   ParseSubtargetFeatures(CPUString, ArchFS);
195 
196   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
197   // Assert this for now to make the change obvious.
198   assert(hasV6T2Ops() || !hasThumb2());
199 
200   // Keep a pointer to static instruction cost data for the specified CPU.
201   SchedModel = getSchedModelForCPU(CPUString);
202 
203   // Initialize scheduling itinerary for the specified CPU.
204   InstrItins = getInstrItineraryForCPU(CPUString);
205 
206   // FIXME: this is invalid for WindowsCE
207   if (isTargetWindows())
208     NoARM = true;
209 
210   if (isAAPCS_ABI())
211     stackAlignment = 8;
212   if (isTargetNaCl() || isAAPCS16_ABI())
213     stackAlignment = 16;
214 
215   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
216   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
217   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
218   // support in the assembler and linker to be used. This would need to be
219   // fixed to fully support tail calls in Thumb1.
220   //
221   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
222   // LR.  This means if we need to reload LR, it takes an extra instructions,
223   // which outweighs the value of the tail call; but here we don't know yet
224   // whether LR is going to be used.  Probably the right approach is to
225   // generate the tail call here and turn it back into CALL/RET in
226   // emitEpilogue if LR is used.
227 
228   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
229   // but we need to make sure there are enough registers; the only valid
230   // registers are the 4 used for parameters.  We don't currently do this
231   // case.
232 
233   SupportsTailCall = !isThumb1Only();
234 
235   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
236     SupportsTailCall = false;
237 
238   switch (IT) {
239   case DefaultIT:
240     RestrictIT = hasV8Ops();
241     break;
242   case RestrictedIT:
243     RestrictIT = true;
244     break;
245   case NoRestrictedIT:
246     RestrictIT = false;
247     break;
248   }
249 
250   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
251   const FeatureBitset &Bits = getFeatureBits();
252   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
253       (Options.UnsafeFPMath || isTargetDarwin()))
254     UseNEONForSinglePrecisionFP = true;
255 }
256 
257 bool ARMSubtarget::isAPCS_ABI() const {
258   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
259   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
260 }
261 bool ARMSubtarget::isAAPCS_ABI() const {
262   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
263   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
264          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
265 }
266 bool ARMSubtarget::isAAPCS16_ABI() const {
267   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
268   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
269 }
270 
271 
272 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
273 bool
274 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
275                                  Reloc::Model RelocM) const {
276   if (RelocM == Reloc::Static)
277     return false;
278 
279   bool isDef = GV->isStrongDefinitionForLinker();
280 
281   if (!isTargetMachO()) {
282     // Extra load is needed for all externally visible.
283     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
284       return false;
285     return true;
286   } else {
287     // If this is a strong reference to a definition, it is definitely not
288     // through a stub.
289     if (isDef)
290       return false;
291 
292     // Unless we have a symbol with hidden visibility, we have to go through a
293     // normal $non_lazy_ptr stub because this symbol might be resolved late.
294     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
295       return true;
296 
297     if (RelocM == Reloc::PIC_) {
298       // If symbol visibility is hidden, we have a stub for common symbol
299       // references and external declarations.
300       if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
301         // Hidden $non_lazy_ptr reference.
302         return true;
303     }
304   }
305 
306   return false;
307 }
308 
309 unsigned ARMSubtarget::getMispredictionPenalty() const {
310   return SchedModel.MispredictPenalty;
311 }
312 
313 bool ARMSubtarget::hasSinCos() const {
314   return isTargetWatchOS() ||
315     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
316 }
317 
318 bool ARMSubtarget::enableMachineScheduler() const {
319   // Enable the MachineScheduler before register allocation for out-of-order
320   // architectures where we do not use the PostRA scheduler anymore (for now
321   // restricted to swift).
322   return getSchedModel().isOutOfOrder() && isSwift();
323 }
324 
325 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
326 bool ARMSubtarget::enablePostRAScheduler() const {
327   // No need for PostRA scheduling on out of order CPUs (for now restricted to
328   // swift).
329   if (getSchedModel().isOutOfOrder() && isSwift())
330     return false;
331   return (!isThumb() || hasThumb2());
332 }
333 
334 bool ARMSubtarget::enableAtomicExpand() const {
335   return hasAnyDataBarrier() && !isThumb1Only();
336 }
337 
338 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
339   // For general targets, the prologue can grow when VFPs are allocated with
340   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
341   // format which it's more important to get right.
342   return isTargetWatchOS() || (isSwift() && !MF.getFunction()->optForMinSize());
343 }
344 
345 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
346   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
347   // immediates as it is inherently position independent, and may be out of
348   // range otherwise.
349   return !NoMovt && hasV6T2Ops() &&
350          (isTargetWindows() || !MF.getFunction()->optForMinSize());
351 }
352 
353 bool ARMSubtarget::useFastISel() const {
354   // Enable fast-isel for any target, for testing only.
355   if (ForceFastISel)
356     return true;
357 
358   // Limit fast-isel to the targets that are or have been tested.
359   if (!hasV6Ops())
360     return false;
361 
362   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
363   return TM.Options.EnableFastISel &&
364          ((isTargetMachO() && !isThumb1Only()) ||
365           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
366 }
367