1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARM.h"
15
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "MCTargetDesc/ARMMCTargetDesc.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCTargetOptions.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/TargetParser.h"
40 #include "llvm/Target/TargetOptions.h"
41
42 using namespace llvm;
43
44 #define DEBUG_TYPE "arm-subtarget"
45
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
49
50 static cl::opt<bool>
51 UseFusedMulOps("arm-use-mulops",
52 cl::init(true), cl::Hidden);
53
54 enum ITMode {
55 DefaultIT,
56 RestrictedIT,
57 NoRestrictedIT
58 };
59
60 static cl::opt<ITMode>
61 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
62 cl::ZeroOrMore,
63 cl::values(clEnumValN(DefaultIT, "arm-default-it",
64 "Generate IT block based on arch"),
65 clEnumValN(RestrictedIT, "arm-restrict-it",
66 "Disallow deprecated IT based on ARMv8"),
67 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
68 "Allow IT blocks based on ARMv7")));
69
70 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
71 /// currently supported (for testing only).
72 static cl::opt<bool>
73 ForceFastISel("arm-force-fast-isel",
74 cl::init(false), cl::Hidden);
75
76 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
77 /// so that we can use initializer lists for subtarget initialization.
initializeSubtargetDependencies(StringRef CPU,StringRef FS)78 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
79 StringRef FS) {
80 initializeEnvironment();
81 initSubtargetFeatures(CPU, FS);
82 return *this;
83 }
84
initializeFrameLowering(StringRef CPU,StringRef FS)85 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
86 StringRef FS) {
87 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
88 if (STI.isThumb1Only())
89 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
90
91 return new ARMFrameLowering(STI);
92 }
93
ARMSubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const ARMBaseTargetMachine & TM,bool IsLittle)94 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
95 const std::string &FS,
96 const ARMBaseTargetMachine &TM, bool IsLittle)
97 : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
98 CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
99 TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
100 // At this point initializeSubtargetDependencies has been called so
101 // we can query directly.
102 InstrInfo(isThumb1Only()
103 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
104 : !isThumb()
105 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107 TLInfo(TM, *this) {
108
109 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
110 Legalizer.reset(new ARMLegalizerInfo(*this));
111
112 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
113
114 // FIXME: At this point, we can't rely on Subtarget having RBI.
115 // It's awkward to mix passing RBI and the Subtarget; should we pass
116 // TII/TRI as well?
117 InstSelector.reset(createARMInstructionSelector(
118 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
119
120 RegBankInfo.reset(RBI);
121 }
122
getCallLowering() const123 const CallLowering *ARMSubtarget::getCallLowering() const {
124 return CallLoweringInfo.get();
125 }
126
getInstructionSelector() const127 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
128 return InstSelector.get();
129 }
130
getLegalizerInfo() const131 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
132 return Legalizer.get();
133 }
134
getRegBankInfo() const135 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
136 return RegBankInfo.get();
137 }
138
isXRaySupported() const139 bool ARMSubtarget::isXRaySupported() const {
140 // We don't currently suppport Thumb, but Windows requires Thumb.
141 return hasV6Ops() && hasARMOps() && !isTargetWindows();
142 }
143
initializeEnvironment()144 void ARMSubtarget::initializeEnvironment() {
145 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
146 // directly from it, but we can try to make sure they're consistent when both
147 // available.
148 UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() &&
149 Options.ExceptionModel == ExceptionHandling::None) ||
150 Options.ExceptionModel == ExceptionHandling::SjLj;
151 assert((!TM.getMCAsmInfo() ||
152 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
153 ExceptionHandling::SjLj) == UseSjLjEH) &&
154 "inconsistent sjlj choice between CodeGen and MC");
155 }
156
initSubtargetFeatures(StringRef CPU,StringRef FS)157 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
158 if (CPUString.empty()) {
159 CPUString = "generic";
160
161 if (isTargetDarwin()) {
162 StringRef ArchName = TargetTriple.getArchName();
163 ARM::ArchKind AK = ARM::parseArch(ArchName);
164 if (AK == ARM::ArchKind::ARMV7S)
165 // Default to the Swift CPU when targeting armv7s/thumbv7s.
166 CPUString = "swift";
167 else if (AK == ARM::ArchKind::ARMV7K)
168 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
169 // ARMv7k does not use SjLj exception handling.
170 CPUString = "cortex-a7";
171 }
172 }
173
174 // Insert the architecture feature derived from the target triple into the
175 // feature string. This is important for setting features that are implied
176 // based on the architecture version.
177 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
178 if (!FS.empty()) {
179 if (!ArchFS.empty())
180 ArchFS = (Twine(ArchFS) + "," + FS).str();
181 else
182 ArchFS = FS;
183 }
184 ParseSubtargetFeatures(CPUString, ArchFS);
185
186 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
187 // Assert this for now to make the change obvious.
188 assert(hasV6T2Ops() || !hasThumb2());
189
190 // Execute only support requires movt support
191 if (genExecuteOnly()) {
192 NoMovt = false;
193 assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
194 }
195
196 // Keep a pointer to static instruction cost data for the specified CPU.
197 SchedModel = getSchedModelForCPU(CPUString);
198
199 // Initialize scheduling itinerary for the specified CPU.
200 InstrItins = getInstrItineraryForCPU(CPUString);
201
202 // FIXME: this is invalid for WindowsCE
203 if (isTargetWindows())
204 NoARM = true;
205
206 if (isAAPCS_ABI())
207 stackAlignment = 8;
208 if (isTargetNaCl() || isAAPCS16_ABI())
209 stackAlignment = 16;
210
211 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
212 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
213 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
214 // support in the assembler and linker to be used. This would need to be
215 // fixed to fully support tail calls in Thumb1.
216 //
217 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
218 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
219 // means if we need to reload LR, it takes extra instructions, which outweighs
220 // the value of the tail call; but here we don't know yet whether LR is going
221 // to be used. We take the optimistic approach of generating the tail call and
222 // perhaps taking a hit if we need to restore the LR.
223
224 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
225 // but we need to make sure there are enough registers; the only valid
226 // registers are the 4 used for parameters. We don't currently do this
227 // case.
228
229 SupportsTailCall = !isThumb() || hasV8MBaselineOps();
230
231 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
232 SupportsTailCall = false;
233
234 switch (IT) {
235 case DefaultIT:
236 RestrictIT = hasV8Ops();
237 break;
238 case RestrictedIT:
239 RestrictIT = true;
240 break;
241 case NoRestrictedIT:
242 RestrictIT = false;
243 break;
244 }
245
246 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
247 const FeatureBitset &Bits = getFeatureBits();
248 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
249 (Options.UnsafeFPMath || isTargetDarwin()))
250 UseNEONForSinglePrecisionFP = true;
251
252 if (isRWPI())
253 ReserveR9 = true;
254
255 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
256 switch (ARMProcFamily) {
257 case Others:
258 case CortexA5:
259 break;
260 case CortexA7:
261 LdStMultipleTiming = DoubleIssue;
262 break;
263 case CortexA8:
264 LdStMultipleTiming = DoubleIssue;
265 break;
266 case CortexA9:
267 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
268 PreISelOperandLatencyAdjustment = 1;
269 break;
270 case CortexA12:
271 break;
272 case CortexA15:
273 MaxInterleaveFactor = 2;
274 PreISelOperandLatencyAdjustment = 1;
275 PartialUpdateClearance = 12;
276 break;
277 case CortexA17:
278 case CortexA32:
279 case CortexA35:
280 case CortexA53:
281 case CortexA55:
282 case CortexA57:
283 case CortexA72:
284 case CortexA73:
285 case CortexA75:
286 case CortexR4:
287 case CortexR4F:
288 case CortexR5:
289 case CortexR7:
290 case CortexM3:
291 case CortexR52:
292 break;
293 case Exynos:
294 LdStMultipleTiming = SingleIssuePlusExtras;
295 MaxInterleaveFactor = 4;
296 if (!isThumb())
297 PrefLoopAlignment = 3;
298 break;
299 case Kryo:
300 break;
301 case Krait:
302 PreISelOperandLatencyAdjustment = 1;
303 break;
304 case Swift:
305 MaxInterleaveFactor = 2;
306 LdStMultipleTiming = SingleIssuePlusExtras;
307 PreISelOperandLatencyAdjustment = 1;
308 PartialUpdateClearance = 12;
309 break;
310 }
311 }
312
isTargetHardFloat() const313 bool ARMSubtarget::isTargetHardFloat() const { return TM.isTargetHardFloat(); }
314
isAPCS_ABI() const315 bool ARMSubtarget::isAPCS_ABI() const {
316 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
317 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
318 }
isAAPCS_ABI() const319 bool ARMSubtarget::isAAPCS_ABI() const {
320 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
321 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
322 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
323 }
isAAPCS16_ABI() const324 bool ARMSubtarget::isAAPCS16_ABI() const {
325 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
326 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
327 }
328
isROPI() const329 bool ARMSubtarget::isROPI() const {
330 return TM.getRelocationModel() == Reloc::ROPI ||
331 TM.getRelocationModel() == Reloc::ROPI_RWPI;
332 }
isRWPI() const333 bool ARMSubtarget::isRWPI() const {
334 return TM.getRelocationModel() == Reloc::RWPI ||
335 TM.getRelocationModel() == Reloc::ROPI_RWPI;
336 }
337
isGVIndirectSymbol(const GlobalValue * GV) const338 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
339 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
340 return true;
341
342 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
343 // the section that is being relocated. This means we have to use o load even
344 // for GVs that are known to be local to the dso.
345 if (isTargetMachO() && TM.isPositionIndependent() &&
346 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
347 return true;
348
349 return false;
350 }
351
isGVInGOT(const GlobalValue * GV) const352 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
353 return isTargetELF() && TM.isPositionIndependent() &&
354 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
355 }
356
getMispredictionPenalty() const357 unsigned ARMSubtarget::getMispredictionPenalty() const {
358 return SchedModel.MispredictPenalty;
359 }
360
enableMachineScheduler() const361 bool ARMSubtarget::enableMachineScheduler() const {
362 // Enable the MachineScheduler before register allocation for subtargets
363 // with the use-misched feature.
364 return useMachineScheduler();
365 }
366
367 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
enablePostRAScheduler() const368 bool ARMSubtarget::enablePostRAScheduler() const {
369 if (disablePostRAScheduler())
370 return false;
371 // Don't reschedule potential IT blocks.
372 return !isThumb1Only();
373 }
374
enableAtomicExpand() const375 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
376
useStride4VFPs(const MachineFunction & MF) const377 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
378 // For general targets, the prologue can grow when VFPs are allocated with
379 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
380 // format which it's more important to get right.
381 return isTargetWatchABI() ||
382 (useWideStrideVFP() && !MF.getFunction().optForMinSize());
383 }
384
useMovt(const MachineFunction & MF) const385 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
386 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
387 // immediates as it is inherently position independent, and may be out of
388 // range otherwise.
389 return !NoMovt && hasV8MBaselineOps() &&
390 (isTargetWindows() || !MF.getFunction().optForMinSize() || genExecuteOnly());
391 }
392
useFastISel() const393 bool ARMSubtarget::useFastISel() const {
394 // Enable fast-isel for any target, for testing only.
395 if (ForceFastISel)
396 return true;
397
398 // Limit fast-isel to the targets that are or have been tested.
399 if (!hasV6Ops())
400 return false;
401
402 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
403 return TM.Options.EnableFastISel &&
404 ((isTargetMachO() && !isThumb1Only()) ||
405 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
406 }
407