1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMGenSubtarget.inc"
16 #include "llvm/GlobalValue.h"
17 #include "llvm/Target/TargetOptions.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
20 using namespace llvm;
21 
22 static cl::opt<bool>
23 ReserveR9("arm-reserve-r9", cl::Hidden,
24           cl::desc("Reserve R9, making it unavailable as GPR"));
25 
26 static cl::opt<bool>
27 UseMOVT("arm-use-movt",
28         cl::init(true), cl::Hidden);
29 
30 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
31                            bool isT)
32   : ARMArchVersion(V4)
33   , ARMFPUType(None)
34   , UseNEONForSinglePrecisionFP(false)
35   , SlowVMLx(false)
36   , IsThumb(isT)
37   , ThumbMode(Thumb1)
38   , PostRAScheduler(false)
39   , IsR9Reserved(ReserveR9)
40   , UseMovt(UseMOVT)
41   , HasFP16(false)
42   , HasHardwareDivide(false)
43   , HasT2ExtractPack(false)
44   , stackAlignment(4)
45   , CPUString("generic")
46   , TargetType(isELF) // Default to ELF unless otherwise specified.
47   , TargetABI(ARM_ABI_APCS) {
48   // default to soft float ABI
49   if (FloatABIType == FloatABI::Default)
50     FloatABIType = FloatABI::Soft;
51 
52   // Determine default and user specified characteristics
53 
54   // Parse features string.
55   CPUString = ParseSubtargetFeatures(FS, CPUString);
56 
57   // When no arch is specified either by CPU or by attributes, make the default
58   // ARMv4T.
59   if (CPUString == "generic" && (FS.empty() || FS == "generic"))
60     ARMArchVersion = V4T;
61 
62   // Set the boolean corresponding to the current target triple, or the default
63   // if one cannot be determined, to true.
64   unsigned Len = TT.length();
65   unsigned Idx = 0;
66 
67   if (Len >= 5 && TT.substr(0, 4) == "armv")
68     Idx = 4;
69   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
70     IsThumb = true;
71     if (Len >= 7 && TT[5] == 'v')
72       Idx = 6;
73   }
74   if (Idx) {
75     unsigned SubVer = TT[Idx];
76     if (SubVer >= '7' && SubVer <= '9') {
77       ARMArchVersion = V7A;
78       if (Len >= Idx+2 && TT[Idx+1] == 'm')
79         ARMArchVersion = V7M;
80     } else if (SubVer == '6') {
81       ARMArchVersion = V6;
82       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
83         ARMArchVersion = V6T2;
84     } else if (SubVer == '5') {
85       ARMArchVersion = V5T;
86       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
87         ARMArchVersion = V5TE;
88     } else if (SubVer == '4') {
89       if (Len >= Idx+2 && TT[Idx+1] == 't')
90         ARMArchVersion = V4T;
91       else
92         ARMArchVersion = V4;
93     }
94   }
95 
96   // Thumb2 implies at least V6T2.
97   if (ARMArchVersion >= V6T2)
98     ThumbMode = Thumb2;
99   else if (ThumbMode >= Thumb2)
100     ARMArchVersion = V6T2;
101 
102   if (Len >= 10) {
103     if (TT.find("-darwin") != std::string::npos)
104       // arm-darwin
105       TargetType = isDarwin;
106   }
107 
108   if (TT.find("eabi") != std::string::npos)
109     TargetABI = ARM_ABI_AAPCS;
110 
111   if (isAAPCS_ABI())
112     stackAlignment = 8;
113 
114   if (isTargetDarwin())
115     IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
116 
117   if (!isThumb() || hasThumb2())
118     PostRAScheduler = true;
119 }
120 
121 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
122 bool
123 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
124                                  Reloc::Model RelocM) const {
125   if (RelocM == Reloc::Static)
126     return false;
127 
128   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
129   // load from stub.
130   bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
131 
132   if (!isTargetDarwin()) {
133     // Extra load is needed for all externally visible.
134     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
135       return false;
136     return true;
137   } else {
138     if (RelocM == Reloc::PIC_) {
139       // If this is a strong reference to a definition, it is definitely not
140       // through a stub.
141       if (!isDecl && !GV->isWeakForLinker())
142         return false;
143 
144       // Unless we have a symbol with hidden visibility, we have to go through a
145       // normal $non_lazy_ptr stub because this symbol might be resolved late.
146       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
147         return true;
148 
149       // If symbol visibility is hidden, we have a stub for common symbol
150       // references and external declarations.
151       if (isDecl || GV->hasCommonLinkage())
152         // Hidden $non_lazy_ptr reference.
153         return true;
154 
155       return false;
156     } else {
157       // If this is a strong reference to a definition, it is definitely not
158       // through a stub.
159       if (!isDecl && !GV->isWeakForLinker())
160         return false;
161 
162       // Unless we have a symbol with hidden visibility, we have to go through a
163       // normal $non_lazy_ptr stub because this symbol might be resolved late.
164       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
165         return true;
166     }
167   }
168 
169   return false;
170 }
171 
172 bool ARMSubtarget::enablePostRAScheduler(
173            CodeGenOpt::Level OptLevel,
174            TargetSubtarget::AntiDepBreakMode& Mode,
175            RegClassVector& CriticalPathRCs) const {
176   Mode = TargetSubtarget::ANTIDEP_CRITICAL;
177   CriticalPathRCs.clear();
178   CriticalPathRCs.push_back(&ARM::GPRRegClass);
179   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
180 }
181