1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 
23 using namespace llvm;
24 
25 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
26   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27   if (DwarfReg < 32) {
28     EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
29   } else {
30     EmitOp(dwarf::DW_OP_regx, Comment);
31     EmitUnsigned(DwarfReg);
32   }
33 }
34 
35 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
36   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37   if (DwarfReg < 32) {
38     EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
39   } else {
40     EmitOp(dwarf::DW_OP_bregx);
41     EmitUnsigned(DwarfReg);
42   }
43   EmitSigned(Offset);
44   if (Deref)
45     EmitOp(dwarf::DW_OP_deref);
46 }
47 
48 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
49   assert(SizeInBits > 0 && "piece has size zero");
50   const unsigned SizeOfByte = 8;
51   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52     EmitOp(dwarf::DW_OP_bit_piece);
53     EmitUnsigned(SizeInBits);
54     EmitUnsigned(OffsetInBits);
55   } else {
56     EmitOp(dwarf::DW_OP_piece);
57     unsigned ByteSize = SizeInBits / SizeOfByte;
58     EmitUnsigned(ByteSize);
59   }
60 }
61 
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63   EmitOp(dwarf::DW_OP_constu);
64   EmitUnsigned(ShiftBy);
65   EmitOp(dwarf::DW_OP_shr);
66 }
67 
68 void DwarfExpression::AddOpStackValue() {
69   if (DwarfVersion >= 4)
70     EmitOp(dwarf::DW_OP_stack_value);
71 }
72 
73 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
74   if (isFrameRegister(MachineReg)) {
75     // If variable offset is based in frame register then use fbreg.
76     EmitOp(dwarf::DW_OP_fbreg);
77     EmitSigned(Offset);
78     return true;
79   }
80 
81   int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
82   if (DwarfReg < 0)
83     return false;
84 
85   AddRegIndirect(DwarfReg, Offset);
86   return true;
87 }
88 
89 bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
90                                          unsigned PieceSizeInBits,
91                                          unsigned PieceOffsetInBits) {
92   if (!TRI.isPhysicalRegister(MachineReg))
93     return false;
94 
95   int Reg = TRI.getDwarfRegNum(MachineReg, false);
96 
97   // If this is a valid register number, emit it.
98   if (Reg >= 0) {
99     AddReg(Reg);
100     if (PieceSizeInBits)
101       AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
102     return true;
103   }
104 
105   // Walk up the super-register chain until we find a valid number.
106   // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
107   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
108     Reg = TRI.getDwarfRegNum(*SR, false);
109     if (Reg >= 0) {
110       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
111       unsigned Size = TRI.getSubRegIdxSize(Idx);
112       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
113       AddReg(Reg, "super-register");
114       if (PieceOffsetInBits == RegOffset) {
115         AddOpPiece(Size, RegOffset);
116       } else {
117         // If this is part of a variable in a sub-register at a
118         // non-zero offset, we need to manually shift the value into
119         // place, since the DW_OP_piece describes the part of the
120         // variable, not the position of the subregister.
121         if (RegOffset)
122           AddShr(RegOffset);
123         AddOpPiece(Size, PieceOffsetInBits);
124       }
125       return true;
126     }
127   }
128 
129   // Otherwise, attempt to find a covering set of sub-register numbers.
130   // For example, Q0 on ARM is a composition of D0+D1.
131   //
132   // Keep track of the current position so we can emit the more
133   // efficient DW_OP_piece.
134   unsigned CurPos = PieceOffsetInBits;
135   // The size of the register in bits, assuming 8 bits per byte.
136   unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
137   // Keep track of the bits in the register we already emitted, so we
138   // can avoid emitting redundant aliasing subregs.
139   SmallBitVector Coverage(RegSize, false);
140   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
141     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
142     unsigned Size = TRI.getSubRegIdxSize(Idx);
143     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
144     Reg = TRI.getDwarfRegNum(*SR, false);
145 
146     // Intersection between the bits we already emitted and the bits
147     // covered by this subregister.
148     SmallBitVector Intersection(RegSize, false);
149     Intersection.set(Offset, Offset + Size);
150     Intersection ^= Coverage;
151 
152     // If this sub-register has a DWARF number and we haven't covered
153     // its range, emit a DWARF piece for it.
154     if (Reg >= 0 && Intersection.any()) {
155       AddReg(Reg, "sub-register");
156       AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
157       CurPos = Offset + Size;
158 
159       // Mark it as emitted.
160       Coverage.set(Offset, Offset + Size);
161     }
162   }
163 
164   return CurPos > PieceOffsetInBits;
165 }
166 
167 void DwarfExpression::AddSignedConstant(int Value) {
168   EmitOp(dwarf::DW_OP_consts);
169   EmitSigned(Value);
170   // The proper way to describe a constant value is
171   // DW_OP_constu <const>, DW_OP_stack_value.
172   // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
173   // so we will continue to generate DW_OP_constu <const> for DWARF-2
174   // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
175   // actually describes a value at a constant addess, not a constant value.
176   // However, in the past there was no better way  to describe a constant
177   // value, so the producers and consumers started to rely on heuristics
178   // to disambiguate the value vs. location status of the expression.
179   // See PR21176 for more details.
180   AddOpStackValue();
181 }
182 
183 void DwarfExpression::AddUnsignedConstant(unsigned Value) {
184   EmitOp(dwarf::DW_OP_constu);
185   EmitUnsigned(Value);
186   // cf. comment in DwarfExpression::AddSignedConstant().
187   AddOpStackValue();
188 }
189 
190 static unsigned getOffsetOrZero(unsigned OffsetInBits,
191                                 unsigned PieceOffsetInBits) {
192   if (OffsetInBits == PieceOffsetInBits)
193     return 0;
194   assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
195   return OffsetInBits;
196 }
197 
198 bool DwarfExpression::AddMachineRegExpression(const DIExpression *Expr,
199                                               unsigned MachineReg,
200                                               unsigned PieceOffsetInBits) {
201   auto I = Expr->expr_op_begin();
202   auto E = Expr->expr_op_end();
203   if (I == E)
204     return AddMachineRegPiece(MachineReg);
205 
206   // Pattern-match combinations for which more efficient representations exist
207   // first.
208   bool ValidReg = false;
209   switch (I->getOp()) {
210   case dwarf::DW_OP_bit_piece: {
211     unsigned OffsetInBits = I->getArg(0);
212     unsigned SizeInBits   = I->getArg(1);
213     // Piece always comes at the end of the expression.
214     return AddMachineRegPiece(MachineReg, SizeInBits,
215                getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
216   }
217   case dwarf::DW_OP_plus: {
218     auto N = I.getNext();
219     unsigned Offset = I->getArg(0);
220     // First combine all DW_OP_plus until we hit either a DW_OP_deref or a
221     // DW_OP_bit_piece
222     while (N != E && N->getOp() == dwarf::DW_OP_plus) {
223       Offset += N->getArg(0);
224       ++I;
225       N = I.getNext();
226     }
227     if (N != E && N->getOp() == dwarf::DW_OP_deref) {
228       // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
229       ValidReg = AddMachineRegIndirect(MachineReg, Offset);
230       std::advance(I, 2);
231     } else {
232       assert ((N == E) || (N->getOp() == dwarf::DW_OP_bit_piece));
233       if (Offset == 0) {
234         ValidReg = AddMachineRegPiece(MachineReg);
235       } else {
236         ValidReg = AddMachineRegIndirect(MachineReg, Offset);
237         AddOpStackValue();
238       }
239       ++I;
240     }
241     break;
242   }
243   case dwarf::DW_OP_deref: {
244       // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
245       ValidReg = AddMachineRegIndirect(MachineReg);
246       ++I;
247       break;
248   }
249   default:
250     llvm_unreachable("unsupported operand");
251   }
252 
253   if (!ValidReg)
254     return false;
255 
256   // Emit remaining elements of the expression.
257   AddExpression(I, E, PieceOffsetInBits);
258 
259   return true;
260 }
261 
262 void DwarfExpression::AddExpression(DIExpression::expr_op_iterator I,
263                                     DIExpression::expr_op_iterator E,
264                                     unsigned PieceOffsetInBits) {
265   for (; I != E; ++I) {
266     switch (I->getOp()) {
267     case dwarf::DW_OP_bit_piece: {
268       unsigned OffsetInBits = I->getArg(0);
269       unsigned SizeInBits   = I->getArg(1);
270       AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
271       break;
272     }
273     case dwarf::DW_OP_plus:
274       EmitOp(dwarf::DW_OP_plus_uconst);
275       EmitUnsigned(I->getArg(0));
276       break;
277     case dwarf::DW_OP_deref:
278       EmitOp(dwarf::DW_OP_deref);
279       break;
280     default:
281       llvm_unreachable("unhandled opcode found in expression");
282     }
283   }
284 }
285