1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "DwarfExpression.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #include "llvm/IR/DebugInfoMetadata.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <algorithm>
22 #include <cassert>
23 #include <cstdint>
24 
25 using namespace llvm;
26 
emitConstu(uint64_t Value)27 void DwarfExpression::emitConstu(uint64_t Value) {
28   if (Value < 32)
29     emitOp(dwarf::DW_OP_lit0 + Value);
30   else if (Value == std::numeric_limits<uint64_t>::max()) {
31     // Only do this for 64-bit values as the DWARF expression stack uses
32     // target-address-size values.
33     emitOp(dwarf::DW_OP_lit0);
34     emitOp(dwarf::DW_OP_not);
35   } else {
36     emitOp(dwarf::DW_OP_constu);
37     emitUnsigned(Value);
38   }
39 }
40 
addReg(int DwarfReg,const char * Comment)41 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
42  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
43  assert((LocationKind == Unknown || LocationKind == Register) &&
44         "location description already locked down");
45  LocationKind = Register;
46  if (DwarfReg < 32) {
47    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
48   } else {
49     emitOp(dwarf::DW_OP_regx, Comment);
50     emitUnsigned(DwarfReg);
51   }
52 }
53 
addBReg(int DwarfReg,int Offset)54 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
55   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
56   assert(LocationKind != Register && "location description already locked down");
57   if (DwarfReg < 32) {
58     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
59   } else {
60     emitOp(dwarf::DW_OP_bregx);
61     emitUnsigned(DwarfReg);
62   }
63   emitSigned(Offset);
64 }
65 
addFBReg(int Offset)66 void DwarfExpression::addFBReg(int Offset) {
67   emitOp(dwarf::DW_OP_fbreg);
68   emitSigned(Offset);
69 }
70 
addOpPiece(unsigned SizeInBits,unsigned OffsetInBits)71 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
72   if (!SizeInBits)
73     return;
74 
75   const unsigned SizeOfByte = 8;
76   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
77     emitOp(dwarf::DW_OP_bit_piece);
78     emitUnsigned(SizeInBits);
79     emitUnsigned(OffsetInBits);
80   } else {
81     emitOp(dwarf::DW_OP_piece);
82     unsigned ByteSize = SizeInBits / SizeOfByte;
83     emitUnsigned(ByteSize);
84   }
85   this->OffsetInBits += SizeInBits;
86 }
87 
addShr(unsigned ShiftBy)88 void DwarfExpression::addShr(unsigned ShiftBy) {
89   emitConstu(ShiftBy);
90   emitOp(dwarf::DW_OP_shr);
91 }
92 
addAnd(unsigned Mask)93 void DwarfExpression::addAnd(unsigned Mask) {
94   emitConstu(Mask);
95   emitOp(dwarf::DW_OP_and);
96 }
97 
addMachineReg(const TargetRegisterInfo & TRI,unsigned MachineReg,unsigned MaxSize)98 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
99                                     unsigned MachineReg, unsigned MaxSize) {
100   if (!TRI.isPhysicalRegister(MachineReg)) {
101     if (isFrameRegister(TRI, MachineReg)) {
102       DwarfRegs.push_back({-1, 0, nullptr});
103       return true;
104     }
105     return false;
106   }
107 
108   int Reg = TRI.getDwarfRegNum(MachineReg, false);
109 
110   // If this is a valid register number, emit it.
111   if (Reg >= 0) {
112     DwarfRegs.push_back({Reg, 0, nullptr});
113     return true;
114   }
115 
116   // Walk up the super-register chain until we find a valid number.
117   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
118   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
119     Reg = TRI.getDwarfRegNum(*SR, false);
120     if (Reg >= 0) {
121       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
122       unsigned Size = TRI.getSubRegIdxSize(Idx);
123       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
124       DwarfRegs.push_back({Reg, 0, "super-register"});
125       // Use a DW_OP_bit_piece to describe the sub-register.
126       setSubRegisterPiece(Size, RegOffset);
127       return true;
128     }
129   }
130 
131   // Otherwise, attempt to find a covering set of sub-register numbers.
132   // For example, Q0 on ARM is a composition of D0+D1.
133   unsigned CurPos = 0;
134   // The size of the register in bits.
135   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
136   unsigned RegSize = TRI.getRegSizeInBits(*RC);
137   // Keep track of the bits in the register we already emitted, so we
138   // can avoid emitting redundant aliasing subregs. Because this is
139   // just doing a greedy scan of all subregisters, it is possible that
140   // this doesn't find a combination of subregisters that fully cover
141   // the register (even though one may exist).
142   SmallBitVector Coverage(RegSize, false);
143   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
144     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
145     unsigned Size = TRI.getSubRegIdxSize(Idx);
146     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
147     Reg = TRI.getDwarfRegNum(*SR, false);
148     if (Reg < 0)
149       continue;
150 
151     // Intersection between the bits we already emitted and the bits
152     // covered by this subregister.
153     SmallBitVector CurSubReg(RegSize, false);
154     CurSubReg.set(Offset, Offset + Size);
155 
156     // If this sub-register has a DWARF number and we haven't covered
157     // its range, emit a DWARF piece for it.
158     if (CurSubReg.test(Coverage)) {
159       // Emit a piece for any gap in the coverage.
160       if (Offset > CurPos)
161         DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
162       DwarfRegs.push_back(
163           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
164       if (Offset >= MaxSize)
165         break;
166 
167       // Mark it as emitted.
168       Coverage.set(Offset, Offset + Size);
169       CurPos = Offset + Size;
170     }
171   }
172   // Failed to find any DWARF encoding.
173   if (CurPos == 0)
174     return false;
175   // Found a partial or complete DWARF encoding.
176   if (CurPos < RegSize)
177     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
178   return true;
179 }
180 
addStackValue()181 void DwarfExpression::addStackValue() {
182   if (DwarfVersion >= 4)
183     emitOp(dwarf::DW_OP_stack_value);
184 }
185 
addSignedConstant(int64_t Value)186 void DwarfExpression::addSignedConstant(int64_t Value) {
187   assert(LocationKind == Implicit || LocationKind == Unknown);
188   LocationKind = Implicit;
189   emitOp(dwarf::DW_OP_consts);
190   emitSigned(Value);
191 }
192 
addUnsignedConstant(uint64_t Value)193 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
194   assert(LocationKind == Implicit || LocationKind == Unknown);
195   LocationKind = Implicit;
196   emitConstu(Value);
197 }
198 
addUnsignedConstant(const APInt & Value)199 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
200   assert(LocationKind == Implicit || LocationKind == Unknown);
201   LocationKind = Implicit;
202 
203   unsigned Size = Value.getBitWidth();
204   const uint64_t *Data = Value.getRawData();
205 
206   // Chop it up into 64-bit pieces, because that's the maximum that
207   // addUnsignedConstant takes.
208   unsigned Offset = 0;
209   while (Offset < Size) {
210     addUnsignedConstant(*Data++);
211     if (Offset == 0 && Size <= 64)
212       break;
213     addStackValue();
214     addOpPiece(std::min(Size - Offset, 64u), Offset);
215     Offset += 64;
216   }
217 }
218 
addMachineRegExpression(const TargetRegisterInfo & TRI,DIExpressionCursor & ExprCursor,unsigned MachineReg,unsigned FragmentOffsetInBits)219 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
220                                               DIExpressionCursor &ExprCursor,
221                                               unsigned MachineReg,
222                                               unsigned FragmentOffsetInBits) {
223   auto Fragment = ExprCursor.getFragmentInfo();
224   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
225     LocationKind = Unknown;
226     return false;
227   }
228 
229   bool HasComplexExpression = false;
230   auto Op = ExprCursor.peek();
231   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
232     HasComplexExpression = true;
233 
234   // If the register can only be described by a complex expression (i.e.,
235   // multiple subregisters) it doesn't safely compose with another complex
236   // expression. For example, it is not possible to apply a DW_OP_deref
237   // operation to multiple DW_OP_pieces.
238   if (HasComplexExpression && DwarfRegs.size() > 1) {
239     DwarfRegs.clear();
240     LocationKind = Unknown;
241     return false;
242   }
243 
244   // Handle simple register locations.
245   if (LocationKind != Memory && !HasComplexExpression) {
246     for (auto &Reg : DwarfRegs) {
247       if (Reg.DwarfRegNo >= 0)
248         addReg(Reg.DwarfRegNo, Reg.Comment);
249       addOpPiece(Reg.Size);
250     }
251     DwarfRegs.clear();
252     return true;
253   }
254 
255   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
256   if (DwarfVersion < 4)
257     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
258           return Op.getOp() == dwarf::DW_OP_stack_value;
259         })) {
260       DwarfRegs.clear();
261       LocationKind = Unknown;
262       return false;
263     }
264 
265   assert(DwarfRegs.size() == 1);
266   auto Reg = DwarfRegs[0];
267   bool FBReg = isFrameRegister(TRI, MachineReg);
268   int SignedOffset = 0;
269   assert(Reg.Size == 0 && "subregister has same size as superregister");
270 
271   // Pattern-match combinations for which more efficient representations exist.
272   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
273   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
274     SignedOffset = Op->getArg(0);
275     ExprCursor.take();
276   }
277 
278   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
279   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
280   // If Reg is a subregister we need to mask it out before subtracting.
281   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
282     auto N = ExprCursor.peekNext();
283     if (N && (N->getOp() == dwarf::DW_OP_plus ||
284              (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
285       int Offset = Op->getArg(0);
286       SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
287       ExprCursor.consume(2);
288     }
289   }
290 
291   if (FBReg)
292     addFBReg(SignedOffset);
293   else
294     addBReg(Reg.DwarfRegNo, SignedOffset);
295   DwarfRegs.clear();
296   return true;
297 }
298 
299 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
isMemoryLocation(DIExpressionCursor ExprCursor)300 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
301   while (ExprCursor) {
302     auto Op = ExprCursor.take();
303     switch (Op->getOp()) {
304     case dwarf::DW_OP_deref:
305     case dwarf::DW_OP_LLVM_fragment:
306       break;
307     default:
308       return false;
309     }
310   }
311   return true;
312 }
313 
addExpression(DIExpressionCursor && ExprCursor,unsigned FragmentOffsetInBits)314 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
315                                     unsigned FragmentOffsetInBits) {
316   // If we need to mask out a subregister, do it now, unless the next
317   // operation would emit an OpPiece anyway.
318   auto N = ExprCursor.peek();
319   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
320     maskSubRegister();
321 
322   while (ExprCursor) {
323     auto Op = ExprCursor.take();
324     switch (Op->getOp()) {
325     case dwarf::DW_OP_LLVM_fragment: {
326       unsigned SizeInBits = Op->getArg(1);
327       unsigned FragmentOffset = Op->getArg(0);
328       // The fragment offset must have already been adjusted by emitting an
329       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
330       // location.
331       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
332 
333       // If addMachineReg already emitted DW_OP_piece operations to represent
334       // a super-register by splicing together sub-registers, subtract the size
335       // of the pieces that was already emitted.
336       SizeInBits -= OffsetInBits - FragmentOffset;
337 
338       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
339       // sub-register that is smaller than the current fragment's size, use it.
340       if (SubRegisterSizeInBits)
341         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
342 
343       // Emit a DW_OP_stack_value for implicit location descriptions.
344       if (LocationKind == Implicit)
345         addStackValue();
346 
347       // Emit the DW_OP_piece.
348       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
349       setSubRegisterPiece(0, 0);
350       // Reset the location description kind.
351       LocationKind = Unknown;
352       return;
353     }
354     case dwarf::DW_OP_plus_uconst:
355       assert(LocationKind != Register);
356       emitOp(dwarf::DW_OP_plus_uconst);
357       emitUnsigned(Op->getArg(0));
358       break;
359     case dwarf::DW_OP_plus:
360     case dwarf::DW_OP_minus:
361     case dwarf::DW_OP_mul:
362     case dwarf::DW_OP_div:
363     case dwarf::DW_OP_mod:
364     case dwarf::DW_OP_or:
365     case dwarf::DW_OP_and:
366     case dwarf::DW_OP_xor:
367     case dwarf::DW_OP_shl:
368     case dwarf::DW_OP_shr:
369     case dwarf::DW_OP_shra:
370     case dwarf::DW_OP_lit0:
371     case dwarf::DW_OP_not:
372     case dwarf::DW_OP_dup:
373       emitOp(Op->getOp());
374       break;
375     case dwarf::DW_OP_deref:
376       assert(LocationKind != Register);
377       if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
378         // Turning this into a memory location description makes the deref
379         // implicit.
380         LocationKind = Memory;
381       else
382         emitOp(dwarf::DW_OP_deref);
383       break;
384     case dwarf::DW_OP_constu:
385       assert(LocationKind != Register);
386       emitConstu(Op->getArg(0));
387       break;
388     case dwarf::DW_OP_stack_value:
389       LocationKind = Implicit;
390       break;
391     case dwarf::DW_OP_swap:
392       assert(LocationKind != Register);
393       emitOp(dwarf::DW_OP_swap);
394       break;
395     case dwarf::DW_OP_xderef:
396       assert(LocationKind != Register);
397       emitOp(dwarf::DW_OP_xderef);
398       break;
399     default:
400       llvm_unreachable("unhandled opcode found in expression");
401     }
402   }
403 
404   if (LocationKind == Implicit)
405     // Turn this into an implicit location description.
406     addStackValue();
407 }
408 
409 /// add masking operations to stencil out a subregister.
maskSubRegister()410 void DwarfExpression::maskSubRegister() {
411   assert(SubRegisterSizeInBits && "no subregister was registered");
412   if (SubRegisterOffsetInBits > 0)
413     addShr(SubRegisterOffsetInBits);
414   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
415   addAnd(Mask);
416 }
417 
finalize()418 void DwarfExpression::finalize() {
419   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
420   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
421   if (SubRegisterSizeInBits == 0)
422     return;
423   // Don't emit a DW_OP_piece for a subregister at offset 0.
424   if (SubRegisterOffsetInBits == 0)
425     return;
426   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
427 }
428 
addFragmentOffset(const DIExpression * Expr)429 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
430   if (!Expr || !Expr->isFragment())
431     return;
432 
433   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
434   assert(FragmentOffset >= OffsetInBits &&
435          "overlapping or duplicate fragments");
436   if (FragmentOffset > OffsetInBits)
437     addOpPiece(FragmentOffset - OffsetInBits);
438   OffsetInBits = FragmentOffset;
439 }
440